SILVACO TCAD

Square gate all around MOSFETs are a very promising device structures allowing to continue scaling due to their superior control over the short channel effects. In this work a numerical study of a square structure with single channel is compared to a structure with 4 channels in order to highlight the impact of channels number on the device's DC parameters (drain current and threshold voltage). Our single channel rectangular GAA MOSFET showed reasonable ratio Ion/Ioff of 10 4 , while our four channels GAA MOSFET showed a value of 10 3. In addition, a low value of drain induced barrier lowering (DIBL) of 60mV/V was obtained for our single channel GAA and a lower value of with 40mv/v has been obtained for our four channel one. Also, an extrinsic transconductance of 88ms/µm have been obtained for our four channels GAA compared to the single channel that is equal to 7ms/µm. Keyword: Channels DIBL Gate-all-around MOSFETS Multiple SCEs Silicon Silvaco-TCAD

This work presents a SILVACO TCAD based fabrication and device simulation of a top-gated graphene field-effect transistor. Effects of channel length and channel doping concentrations on the characteristics curves (transfer and output characteristics) of the GFET are also investigated and analyzed physically to obtain more physical insight.

In this work, we present the effects of gate electrode work function and the doping profile terminating within and outside the drain on the performance of the double gate tunnelling field effect transistor (TFET). The key parameters, used in this simulation study, are the ambipolar
current, ION/IOFF ratio and subthreshold swing (SS). The results show that, Gaussian doping profile terminating within the drain is the most promising design for the ON/OFF ratio. All the simulations have been performed and obtained with the help of ATLAS device simulator (Silvaco) and MATLAB.

Reactively sputtered copper indium sulfide (CIS) chalcopyrite semiconductor has been actively studied as the potential absorber layer for solar cell thin film application. Using sputtering technique however could result in the formation of several types of defects for example microscopic defects. Microscopic defects are formed within the absorber layer due to the formation of pinholes after surface treatment process. Since the effects of the formation of pinholes in CIS-based thin film solar cell is not well understood yet, a detail study is therefore necessary. In this work, a solar cell model was developed and simulated using Silvaco TCAD tools. Cylindrical pinholes of various diameters and depths were created and analyzed. The simulation results predicted that the number and depth of the pinholes affect the performance of the CIS-based thin film solar cell. The variation of pinhole diameter however did not exhibit any significant effect. It was found that the increases in the number of the pinholes resulted in the increases of solar cell efficiency. The efficiency was predicted to be of around 17.5% when ten pinholes existed within the CIS layer. No significant effect was found as the diameter of the pinhole became wider. Deeper the pinhole depth into the layer however produced the solar cell efficiency of only 1.37%.

This presents a two D analytical model for the surface potential, field and drain current for SiO2/High-k stacked gate compound double gate tunnel field impact semiconductor unit. Parabolic approximation technique uses two dimensional Poisson's equation which has been resolved to get surface potential and any used to derive the electrical field of the device. Kane's model is employed to judge the drain current of the device. Drain current, Surface potential model are studied with impact to the varied device parameters victimisation MATLAB. The planned results are in glorious agreement with the TCAD simulation results and having higher performance in tiny dimensions.

—2D numerical simulation of normally off vertical N-channel JFET with novel internal lateral gate configuration designed on a 9.4 μm, 7 × 1015 cm−3 doped drift layer is presented. The study covers an interval of blocking voltages ranging from 600 V to 933 V for various temperatures and channel widths. The effect of elimination of vertical JFET gates and variation in channel width on the on-state/breakdown performance is carefully investigated. The device performance has been compared in terms of blocking voltages, specific on-state resistance and maximum output current density in the temperature range from room temperature up to 473 K. Normally-off operation with blocking voltage (Vbl) of 933 V is demonstrated for a gate voltage of-20 V. The goal of this work is to predict the performance of lateral gate VJFET configuration and have a deep insight into the relationship between the device's electrical/thermal characteristics and channel thickness. The detailed investigation reveals that lateral gate configuration offers less resistance to leakage current reducing the blocking capability of the device. Though, it's excellent on state performance in terms of high saturation current (1.23A) and low on-resistance (3.6 m Ω) makes this VJFET an excellent device for fast power switching applications.

This work presents a SILVACO TCAD based fabrication and device simulation of a top-gated graphene field-effect transistor. Effects of channel length and channel doping concentrations on the characteristics curves (transfer and output characteristics) of the GFET are also investigated and analyzed physically to obtain more physical insight.

A simulation based design evaluation is reported for SOI FinFETs at 22nm gate length. The impact of device parameters on the static power dissipation and delay of a CMOS inverter is presented. Fin dimensions such as Fin width and height are varied. For a given gate oxide thickness increasing the fin height and fin width degrades the SCEs, while improves the performance. It was found that reducing the fin thickness was beneficial in reducing the off state leakage current (IOFF), while reducing the fin height was beneficial in reducing the gate leakage current (IGATE). It was found that Static power dissipation of the inverter increases with fin height due to the increase in leakage current, whereas delay decreased with increase fin width due to higher on current. The performance of the inverter decreased with the downscaling of the gate oxide thickness due to higher gate leakage current and gate capacitance.

A simulation based design evaluation is reported for SOI FinFETs at 22nm gate length. The impact of device parameters on the static power dissipation and delay of a CMOS inverter is presented. Fin dimensions such as Fin width and height are varied. For a given gate oxide thickness increasing the fin height and fin width degrades the SCEs, while improves the performance. It was found that reducing the fin thickness was beneficial in reducing the off state leakage current (IOFF), while reducing the fin height was beneficial in reducing the gate leakage current (IGATE). It was found that Static power dissipation of the inverter increases with fin height due to the increase in leakage current, whereas delay decreased with increase fin width due to higher on current. The performance of the inverter decreased with the downscaling of the gate oxide thickness due to higher gate leakage current and gate capacitance.

lnAlAs/lnGaAs/InP high electron mobility transistor (HEMT) offers excellent high frequency operation.In this work, the DC and RF performance of a 20 nm gate length enhancement mode InAlAs/InGaAs/InP high electron mobility transistor (HEMT) on InP substrate are presented. The SILVACO-TCAD simulations performed at room temperature using the appropriate model sshowed that the studied device exhibit excellent pinch-off characteristics, with a maximum transconductance of 1100ms/mm, a threshold voltage of 0,62V, and an Ion/Ioff ratio of 2.106. The cutoff frequency and maximum frequency of oscillation are 980 GHz and 1.3THz respectively. These promising results allow us to affirm that this device is intended to be used in high frequency applications. 1. INTRODUCTION High electron mobility transistors (HEMTs) technology is usually used for high frequency, high speed and low power applications [1] due to the enhanced electron mobility and velocity at high electron density in the channel. This provides an important drive current ID, an improved transconductance gm, an important cutoff frequency fT, and an important output gain, and also provided a low value of noise, low noise and high gain performances. Accordingly, HEMT devices became a significantly competitive candidate for various high-speed circuits [2, 3] millimeter wave systems [4, 5] and even terahertz applications [6-8]. In another hand High electron mobility devices based in the InAlAs/InGaAs material system showed the best high frequency response obtained until now and have exhibited excellent performances in terms of noise parameters compared to MOSFET devices at RF and microwave fields [9]. Also, diverse research groups work hard to increase the maximum frequency fmax of InP and succeeded in bringing up its fmax up to 1 THz. Actually, several technologies are based todayon InGaAs/InAlAs quantum well HEMT devices [10]. InAlAs/InGaAs HEMTs play a leading role in the communication domain ranging from cell phones to electronic warfare systems such as radar and radio astronomy and amplificator application like LNA using an inductive drain feedback technique for wireless application at 5.8GHz and was used in LNA that designed using T-network as a matching technique was used at the input and output terminal, inductive generation to the source and an inductive drain feedback [11, 12]. The particular carrier transport properties of III-V materials are very attractive for THz applications, where outstanding high frequency characteristics have been reported [13-15]. InP-based electron mobility HEMTs are progressively becoming important for the fabrication of millimeter wave-MMICs (monolithic microwave integrated circuits) with high frequency and low noise applications and used for

The FBAR (Film Bulk Acoustic Resonator) is an ultrasonic transducer consisting of a piezoelectric film which is taken as sandwich between two planar metallic electrodes. The lateral dimensions of this MEMS (Micro Electro Machinated System) are considered very large compared to its thickness [1-3].
In a first approach, an analytical one-dimensional propagation model (Mason’s Model [4, 5]) is adopted. This model allowed us to determine the evolution of the electrical impedance of the transducer as a function of frequency. In a second step, we considered a FBAR transducer with 130x130x1.52 μm3 dimensions. We present the simulation of the manufactured process technology of the real structure. We perform, first, the harmonic study of the structure without embedding. Then, we study the embedding effect.
Manufacturing process steps simulation was performed under SILVACO tools (Athena, Atlas and DevEdit) [6]. Electromechanical characterization was conducted using a Finite Element Method FEM simulation [7, 8]. We perform; first, a comparison of electrical characterization results obtained using these tools with those of the one-dimensional analytical study. Then, we study the effect of embedment of the structure on the electromechanical behavior of the system.

In this paper, we are interested in simulations and modeling of ZnGeN2/GaN quantum wells solar cell, like all other solar cells as we know always are sensitive to the temperature, many effects like number of quantum wells (NQWs), temperature (T) on photovoltaic properties such as current density-voltage I(V), power density-voltage P(V) and the external quantum efficiency (EQE) are investigated. The most parameter affected by the change in temperature is the open circuit voltage (V oc ). We found in a temperature of 280 K gives better results of open circuit voltage (V oc ), maximum power output (P m ), and conversion efficiency (η) their values are 2.87 V, 21.12 mW/cm 2 , and 21.22% respectively.

This paper presents a 1μm×1.25μm×1µm heterojunction thin film photovoltaic cell having "p-i1-i2-n" cell structure. The designed "ITO/p-CdTe/i1-CdTe/i2-a-Si/n-a-Si/ITO" photovoltaic cell is investigated, optimized and simulated in Silvaco TCAD. Finite Element Analysis (FEA) has been carried out to cater all physical and numerical models to generate practical results. For improvement in cell efficiency, a 1.52 eV wide-bandgap player of CdTe is used which specifically improves the short circuit current (JSC). JSC is directly involved in the improvement of conversion efficiency. For the active region, an intrinsic CdTe layer is combined with an intrinsic amorphous silicon (a-Si) layer. This combination of intrinsic layers in active region is responsible for maximum absorption of photons with a wide range of energies and results in additional electron hole pair generation. Selective absorption is used to maximize light trapping and strong scattering of incident light into active region. Indium Tin Oxide (ITO) is used as front layer and back contact layer with Aluminum (Al) because it offers low resistivity of ~10-4 Ωcm and a transmittance of greater than 90%. Results have been validated by implementing two reported cells with p-ii-n and p-in structures. The results indicate achievement of 28.05% conversion efficiency of the proposed heterojunction cell. The achieved efficiency is better than the efficiencies of the related cells compared in this work and also higher than that of the 25.6% of conventional Heterojunction Intrinsic Thin-film (HIT) silicon solar cells.

In this work, we present the effects of gate electrode work function and the doping profile terminating within and outside the drain on the performance of the double gate tunnelling field effect transistor (TFET). The key parameters, used in this simulation study, are the ambipolar current, ION/IOFF ratio and subthreshold swing (SS). The results show that, Gaussian doping profile terminating within the drain is the most promising design for the ON/OFF ratio. All the simulations have been performed and obtained with the help of ATLAS device simulator (Silvaco) and MATLAB.

In this paper, w e are interested in the simulation and modeling of ZnGexSn1-xN2 /GaN quantum wells (QWs) solar cell, according to many studies before the solar cells always are sensitive to the temperature, for this case, the effect of the temperature on photovoltaic characteristics such as power density-voltage P(V), current density-voltage I(V), and the external quantum efficiency EQE are investigated. The most parameter affected by the changing in the temperature is the open circuit voltage Voc. for optimization. It has been found at 280 K the cell gives better results of open circuit voltage and conversion efficiency their values are 2.18 V and 2.75% respectively.

The use of nanometer CMOS technologies (below 90nm) however brings along significant challenges for circuit design (both analog and digital). By reducing the dimensions of transistors many physical phenomenon like gate leakage, drain induced barrier lowering and many more effects comes into picture. Reducing the feature size in the technology of device with the addition of ever more interconnect layers, the density of the digital as well as analog circuit will increase while intrinsic gate switching delay is reduced. We have simulated conventional and DMG MOSFET at 30nm scale using Silvaco TAD tool and obtained result. A two dimensional device simulation was carried out and observed that DMG MOSFET has a low leakage current as compared to conventional MOSFET and find suitable application in analog circuits.

In this work,theforward current-voltagecharacteristics of n-type Al implanted 4H-SiC pin diodeshave been investigated experimentally and by mean of numerical simulations in the 298-378K temperature range. Our simulations were performed using proprietary simulations software. The model parameters to be calibrated in the simulation are the electron and hole minority carriers lifetimes.The measured forward I-V characteristics showed two differentbehaviour, the leaky behaved and well behaved diode. The later diodes were considered for simulation comparison.Employing temperature-dependent carrier lifetimes as a fitting parameter, the simulation indicates that drift layer and bulk carrier lifetime ranging from 10ns to 50ns. We achieved a good agreement between simulations and measured data. The measured and the simulated forward characteristics indicate an ideality factor of about1.3for the region 2.5V-2.78Vand 2.14 in the low injection region. Activation energies of about 1.61eV and 2.51...

This paper reports the simulation and optimization of an organic/inorganic perovskite-based photovoltaic solar cell. Several structures for PSC are found in literature in order to enhance the conversion efficiency. The objectif of this work is to study and investigate different structures of solar cells based on perovskite materials to improve their performances. The simulated solar cell is made by sandwiching TiO2/Perovskite/spiro-OMeTAD layers where TiO2 is the electron transport layer (ETL), spiro-OMeTAD is the hole transport layer (HTL) and both CH3NH3PbI3 CH3NH3SnI3 are the perovskite (PVK) absorber layers. Therefore, the layer thicknesses of different materials are modified in order to find the better conversion efficiency of solar cells. The obtained results show that layer thicknesses that provide the maximum power conversion efficiency of 18.16% and 9.56% for both perovskite materials CH3NH3PbI3 and CH3NH3SnI3, respectively are 200 nm, 100 nm and 500 nm for spiro-OMeTAD, TiO2 and PVK materials, respectively. The numerical simulation was performed using the ATLAS device simulation software.

lnAlAs/lnGaAs/InP high electron mobility transistor (HEMT) offers excellent high frequency operation.In this work,the DC and RF performance of a 20 nm gate length enhancement mode InAlAs/InGaAs/InP high electron mobility transistor (HEMT) on InP substrate are presented.The SILVACO-TCAD simulations performed at room temperature using the appropriate model sshowed that the studied device exhibit excellent pinch-off characteristics, with a maximum transconductance of 1100ms/mm, a threshold voltage of 0,62V, and an Ion/Ioff ratio of 2.106. The cut-off frequency and maximum frequency of oscillation are 980 GHz and 1.3THz respectively. These promising results allow us to affirm that this device is intended to be used in high frequency applications.

The objectives of this work are focused on the application of strained silicon on MOSFET transistor. To do this, impact and benefits obtained with the use of strained silicon technology on p-channel MOSFETs are presented. This research attempt to create conventional and two-strained silicon MOSFETs fabricated from the use of TCAD, which is a simulation tool from Silvaco. In our research, two-dimensional simulation of conventional MOSFET, biaxial strained PMOSFET and dual channel strained P-MOSFET has been achieved to extract their characteristics. ATHENA and ATLAS have been used to simulate the process and validate the electronic characteristics. Our results allow showing improvements obtained by comparing the three structures and their characteristics. The maximum of carrier mobility improvement is achieved with percentage of 35.29 % and 70.59 % respectively, by result an improvement in drive current with percentage of 36.54 % and 236.71 %, and reduction of leakage current with per...

This paper presents a systematic study to show the impact of channel length on the Analog/RF performances of gate stack (GS) silicon on insulator (SOI) architecture. The downscaling of channel length becomes the biggest challenge to maintain higher speed, low power and better electrostatic integrity for each generation. This investigation is done to find out the potential of the channel length in view of analog and RF performance measures of sub-100nm GS-double gate (DG) MOSFETs. The threshold voltage (Vth) is made constant by tuning the gate metal work function while downscale the channel length (L). The impact of channel length variation on subthreshold slope (SS), drain induced barrier lowering (DIBL), transconductance (gm), output conductance (gd), early voltage (VEA), transconductance generation factor (TGF), intrinsic gain (AV), cut-off frequency (fT), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP) are ...

The objectives of this work are focused on the application of strained silicon on MOSFET transistor. To do this, impact and benefits obtained with the use of strained silicon technology on p-channel MOSFETs are presented. This research attempt to create conventional and two-strained silicon MOSFETs fabricated from the use of TCAD, which is a simulation tool from Silvaco. In our research, two-dimensional simulation of conventional MOSFET, biaxial strained PMOSFET and dual channel strained P-MOSFET has been achieved to extract their characteristics. ATHENA and ATLAS have been used to simulate the process and validate the electronic characteristics. Our results allow showing improvements obtained by comparing the three structures and their characteristics. The maximum of carrier mobility improvement is achieved with percentage of 35.29 % and 70.59 % respectively, by result an improvement in drive current with percentage of 36.54 % and 236.71 %, and reduction of leakage current with percentage of 59.45 % and 82.75 %, the threshold voltage is also enhaced with percentage of: 60 % and 61.4%. Our simulation results highlight the importance of incorporating strain technology in MOSFET transistors.

Zinc oxide (ZnO) is a semiconductor with promising electrical and optical properties. Pure ZnO is an n-type degenerate semiconductor and is almost entirely transparent in the optical region of the electromagnetic spectrum. Thus, the interest in ZnO study as a suitable material for photo detectors and solar cells has increased significantly. Sol–gel spin-coating method was used to grow ZnO thin films from Zinc acetate decomposition. The transmittance (T), reflectance (R), absorption coefficient (alpha (α)), optical band gap (Eg), refractive index (n), extinction coefficient (k), real dielectric constant ( 1), and imaginary dielectric constant ( 2) were investigated to use them in the simulation. However, real ZnO/Cu 2 O heterostructure solar cell based on ZnO (Zinc acetate decomposition) shows poor photovoltaic performance compared to zinc nitrate and diethyl zinc decompositions. Numerical simulation is used to elucidate this poor performance. The same structure has been simulated by considering two cases. The first is that ZnO is a perfect material. The second models ZnO as a semiconductor with continuous distribution of states in its band gap similar to an amorphous semiconductor. The density of states model used here is composed of four bands: two tail bands (a donor-like g TD (E) and an acceptor-like g TA (E)) and two Gaussian distribution deep level bands (an acceptor-like g GA (E) and a donor-like g GT (E)). Evidently the first case gave results far from reality. In the second case, however, and by adjusting the constituents of the band gap states we were able to reproduce a good agreement between simulated and measured J-V characteristics of the solar cell.

This paper presents the design parameters for a thin film 3J <em>InGaP/GaAs/Ge </em>solar cell with a simulated maximum efficiency of 32.11% using Tcad Silvaco. Design parameters include the doping concentration, molar fraction, layers' thickness and tunnel junction characteristics. An initial dual junction InGaP/GaAs model of a previous published heterojunction cell was simulated in Tcad Silvaco to accurately predict solar cell performance. To improve the solar cell's performance, we have fixed meshing, material properties, models and numerical methods. However, thickness and layer doping concentration were taken as variables. We, first simulate the InGaP\GaAs dual junction cell by changing the doping concentrations and thicknesses which showed an increase in efficiency. Next, a triple junction <em>InGaP/GaAs/Ge </em>cell was modeled by adding a Ge layer to the previous dual junction InGaP/GaAs model with an InGaP /GaAs tunnel junction.

Abstract:- In this paper a new method for developing a realistic model of any type of solar cell is presented. Taking into account the high cost of research and experimentation involved with the development of advanced cells, we present here this novel methodology. In our opinion, the introduction of this modeling technique to the Photovoltaic community will prove to be of great importance in aiding the design and developing of advanced solar cells. A model of an InGaP/GaAs/Ge multi-junction solar cell is prepared and is fully simulated. The major stages of the process are explained and the simulation results are compared to published experimental data. The flexibility of the proposed methodology is demonstrated and example results are shown throughout the whole process.

Square gate all around MOSFETs are a very promising device structures allowing to continue scaling due to their superior control over the short channel effects. In this work a numerical study of a square structure with single channel is compared to a structure with 4 channels in order to highlight the impact of channels number on the device’s DC parameters (drain current and threshold voltage). Our single channel rectangular GAA MOSFET showed reasonable ratio Ion/Ioff of 10 4 , while our four channels GAA MOSFET showed a value of 10 3 . In addition, a low value of drain induced barrier lowering (DIBL) of 60mV/V was obtained for our single channel GAA and a lower value of with 40mv/v has been obtained for our four channel one. Also, an extrinsic transconductance of 88ms/µm have been obtained for our four channels GAA compared to the single channel that is equal to 7ms/µm.

We report a highly stable, nanocrystalline, zinc oxide (ZnO) thin-film transistor (TFT) fabricated by spray pyrolysis using purified ZrOₓ as a gate insulator. The crystalline ZnO layer shows an average grain size of 30 nm and a smooth surface with an average rms roughness value of 1.21 nm. The smoothness of the ZnO film is due to the alignment of all grains with the (002) c-axis. The TFTs exhibit a saturation mobility of 12.76 cm²/V· s, a subthreshold swing of 260 mV/dec, and an on/off current ratio of ~10⁸ with negligible hysteresis voltage. The ZnO TFT shows excellent stability under bias stress because of the high-quality ZnO film and its excellent interface with ZrOₓ. The conduction band tail width of ZnO was obtained from the TCAD fitting to the measurement data and was found to be 65 meV.