Static Timing Analyis

Chips for various end applications come in two types, one as ASIC and the other as FPGA. Different parameters like cost, R&D expenses, programmability are considered before implementing logic on an ASIC or FPGA. In addition to the previously mentioned parameters, back-end flow is another crucial parameter that must be considered. Before taping out a chip in ASIC flow, the design goes through several phases like Floor Planning, Clock Tree Synthesis, Place and Route, Physical Verification, etc. in back-end flow while in FPGA flow the implementation tool takes care of most of the backend flow with less human interaction. Be it the ASIC flow or FPGA flow, closing timing for a design with appropriate timing constraints is crucial else the design would violate setup or hold time constraints that will eventually lead to metastability in design. So, in this article, we will go through the basics of timing closure and learn about different parameters that affect timing with practical examples.