TAP

An implementation of IEEE 1149.1 TAP controller is presented in this paper. JTAG is an established technology and industry standard for on-chip boundary scan testing of SoCs. JTAG TAP controllers are becoming a delivery and control mechanism for Design For Test. The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications.

Ilgar Gurbanov, "Southern Gas Corridor Gains New Momentum", The Jamestown Foundation, Eurasia Daily Monitor, Volume 13 Issue 108, www.jamestown.org/single/?tx_ttnews%5Btt_news%5D=45518&tx_ttnews%5BbackPid%5D=7&cHash=74eea786174922333fc0874a2809e641#.V493ybuLSUl

We propose an approach to test whether an abstract specification is refined or not by a more concrete one. The specifications are input $\slash$ output symbolic transition systems (IOSTS). The refinement relation requires that all traces of the abstract system are also traces of the concrete system, up to some signature inclusion. Our work takes inspiration from the conformance testing area. Symbolic execution techniques allow us to select traces of the abstract system and to submit them on the concrete specification. Each trace execution leads to a verdict Fail, Pass or Warning. The verdict Pass is provided with a formula which has to be verified by the values only manipulated at the level of the concrete specification in order to ensure the refinement relation. The verdict Warning reports that the concrete specification has not been sufficiently explored to give a reliable verdict. This is thus a partial verification process, related to the quality of the set of selected traces and of the exploration of the concrete specification. Our approach has been implemented and is demonstrated on a simple example.

Abstract. A design specification is the artifact intermediate between implemented code and the customer requirements. In this paper we argue that customer requirements and design specifications should be testable and testable early in the design cycle leading to early detection of re-quirement and specification errors. The core idea behind early testable requirements is that the problem is described before we search for a so-lution that can be tested against the problem description. We also want the problem description to drive the design. We provide a method for describing early testable requirements and specifications and a support tool called ESpec. ESpec allows for the description of testable require-ments via Fit tables as well as testable design specifications via contracts written in Eiffel using mathematical models following the single model principle. The tool can mechanically check the requirements and specifi-cations. 1

Ilgar Gurbanov, "Between TAP and Nabucco: Who is the “WINNER” of pipeline selection? – Azerbaijan or Russia?", Bilgesam, 2013, http://www.bilgesam.org/en/incele/448/-between-tap-and-nabucco--who-is-the-%C2%93winner%C2%94--azerbaijan-or-russia-/#.Vj0Cj7fhDIV