TMR

The study was undertaken to assess the effect of some tannin and saponin containing herbs, viz. Anarchal, Amla, Baheda and Rohitaka at four levels (0–3% of substrate) on digestibility of nutrients and enteric methane (CH4) production under different feeding systems (roughage to concentrate (R:C) ratios; 80:20, 75:25, 70:30 and
65:35 on DM basis) in vitro in 4×4×4 factorial design. Irrespective of level of herbs and R:C ratios, the fermentation parameters and CH4 mitigation potential varied significantly among different herbs. Digestibility of OM, TVFA and A:P ratio for Anarchal whereas NGP, ME availability, VFA efficiency and depression in CH4 production as % of DM at t1/2 for Rohitaka were observed to be highest. Irrespective of type of herbs and R:C ratios, the net gas
production (NGP), digestibility of NDF, ME availability and TVFA increased linearly with increase in the level of supplementation of herbs and was significantly higher at 2 and 3% level; however, 2%, level had an edge over 3% level w.r.t. partitioning factor, VFA efficiency and A:P ratio. At t1/2, CH4 production as percent of NGP was observed to be lowest at 2 and 3% level. Irrespective of type of herb and their level, NGP, digestibility, ME availability, and TVFAs increased linearly with increase in concentrate in TMRs. At t1/2, CH4 production as percent of NGP was lowest at 65:35 in comparison to others. It was concluded that best results on digestibility of nutrients, VFA production, ME availability and in reducing CH4 production was given by Anarchal and Rohitaka supplemented @ 2% of TMR with R:C ratio of 65:35 on DM basis.

Even a small transition delays and little faults create major concern in digital circuits. It Produce greater impact on
not only for simple memory but also for most of the memory applications.  This paper presents an error-detection method for
difference-set cyclic codes with majority logic decoding. Majority logic decodable codes are suitable for memory applications due to
their capability to correct a large number of errors. However, they require a large decoding time that impacts memory performance.
The proposed fault-detection method significantly reduces memory access time when there is no error in the data read. The
technique uses the majority logic decoder itself to detect failures, which makes the area overhead minimal and keeps the extra
power consumption low. The proposed method detects the occurrences of single error, double error ,triple error in the received
code words obtained from the memory system.

The mitigation of single-event upsets (SEUs) in field-programmable gate arrays (FPGAs) is an increasingly important subject as FPGAs are used in radiation environments such as space. Triple modular redundancy (TMR) is the most frequently used SEU mitigation technique but is very expensive in terms of area and power costs. These costs can be reduced by sacrificing some reliability and applying TMR to only part of the FPGA design. Our Partial TMR method focuses on the most critical sections of the design and increases reliability by applying TMR to continuous sections of the circuit. We introduce an automated software tool that uses the Partial TMR method to apply TMR incrementally until the specified percentage of resources are utilized. Thus the tool gives the maximum reliability gain for the specified area cost. The amount of mitigation applied can be chosen at a very fine level, giving the designer maximum flexibility when producing the final mitigated design.

Radiation and extreme temperature are the main inhibitors for the use of electronic devices in space applications. Radiation challenges the normal and stable operation of DC-DC converters, used as power supply for onboard systems in satellites and spacecrafts. In this situation, special design techniques known as radiation hardening or radiation tolerant designs have to be employed. In this work, a module level design approach for radiation hardening is addressed. A module in this sense is a constituent of a digital controller, which includes an analog to digital converter (ADC), a digital proportional-integral-derivative (PID) controller, and a digital pulse width modulator (DPWM). As a new Radiation Hardening by Design technique (RHBD), a four module redundancy technique is proposed and applied to the digital voltage mode controller driving a synchronous buck converter, which has been implemented as hardware-in-the-loop (HIL) simulation block in MATLAB/Simulink using Xilinx system...

This study assessed the profitability and viability for the commercialization of green corn-based silage production for dairy in Cagayan Valley. Specifically, a.) Determine the cost and return analysis of producing corn green silage; b.) Compare the cost and return for the different opportunities of dairy farmers in engaging silage production; and c.) Assess the profitability and viability of dairy as fed with green corn silage. Malaya Development Cooperative (MDC) has operated with Dairy Buffalo while, San Agustin Dairy Cooperative (SADACO) is engaged in Dairy Carabao production. There were various packages of technologies introduced for adoption like green corn production, green corn silage. Option 3 (planting corn, processed as silage, and sold as silage) has contributed with the highest net return of Php145,565.00 annually while, option 4 (plant corn, process it as green corn silage, feed it as silage to 3 heads dairy Carabao) with net income of Php71,184.63 annually. For viability, option 3 has showed with the best viability results, the lowest payback period of 0.82 year; higher net present value of Php459,634.71 and higher Internal rate of return with 124.21%.

This paper presents the design of reconfigurable adaptive fault tolerant system for 32 bit ALU. In electronic industry, billions of components are built in a single VLSI chip. If the testing cost is reduced to small amount then there will be a benefit of huge amount to produce large number of VLSI circuits. This implemented 32 bit ALU addresses the low power, area efficient with less delay. One of the fundamental issues joined with the plan of FT frameworks incorporate shortcoming/mistake location and fix during framework activity, to take the framework back to the state wherein it works effectively. To handle these issues, with the plan of the FT frameworks, the idea of online checkers and excess must be consolidated. In this paper have designed 32 bit Arithmetic Logic Unit (ALU) using various hardware redundancy techniques with partial dynamic reconfiguration and fault coverage achieved 100%

This paper presents the design of reconfigurable adaptive fault tolerant system for 32 bit ALU. In electronic industry, billions of components are built in a single VLSI chip. If the testing cost is reduced to small amount then there will be a benefit of huge amount to produce large number of VLSI circuits. This implemented 32 bit ALU addresses the low power, area efficient with less delay. One of the fundamental issues joined with the plan of FT frameworks incorporate shortcoming/mistake location and fix during framework activity, to take the framework back to the state wherein it works effectively. To handle these issues, with the plan of the FT frameworks, the idea of on-line checkers and excess must be consolidated. In this paper have designed 32 bit Arithmetic Logic Unit (ALU) using various hardware redundancy techniques with partial dynamic reconfiguration and fault coverage achieved 100%.

Testing core based System on Chip [1] is a challenge for the test engineers. To test the complete SOC at one time with maximum fault coverage, test engineers prefer to test each IP-core separately. At speed testing using external testers is more expensive because of gigahertz processor. The purpose of this paper is to develop cost efficient and flexible test methodology for testing digital IP-cores [2]. The prominent feature of the approach is to use microcontroller to test IP-core. The novel feature is that there is no need of test pattern generator and output response analyzer as microcontroller performs the function of both. This approach has various advantages such as at speed testing, low cost, less area overhead and greater flexibility since most of the testing process is based on software.