XOR gate

This paper presents a comprehensive survey and analysis of various subthreshold leakage power reduction techniques. Moreover, a new technique for low leakage and high speed is also proposed here. As the technology scales down to deep sub micron level, leakage power dissipation increases very rapidly due to the high transistor density, low threshold and ultrathin dielectric. The new proposed circuit technique includes NMOS sleep and helper transistors to reduce leakage current with appropriate W/L ratio. The proposed design gives high speed performance because it includes NMOS transistor in the design which is having higher electron mobility. Post layout simulation of XOR gate using microwind tool with 45nm Berkeley predictive technology model shows that the new circuit technique achieves significant power reduction during a standby mode with lesser delay.

We introduce novel ten (10T) and eight (8T) transistor full-adder logic gates based on recently proposed gate work-function engineering (WFE) approach. When applied to sub-10 nm Schottky-barrier (SB) independent-gate FinFETs, WFE leads to hitherto unexplored 4T and 3T XOR implementations that operate with either only one or no inverted input, respectively. The novel 4T and 3T XOR gates eliminate the need for inverted inputs provided that ambipolar I-V characteristics is shifted by the associated gate work-function in the right direction, where another conduction channel exists. Following the logic verification of the novel 4T and 3T XOR gates via TCAD simulations, we then continue to show how these novel gates can be put to use in building ultra-compact 10T and 8T full-adder circuits, which would normally require up to 20 FinFETs in conventional CMOS architecture. Simulated power-delay products of the novel full-adders show significant (⇠ 5⇥) improvement in dynamic performance attributed largely to the 50% reduction in total area as well as parasitics, at the expense of loss in noise margins. Besides the full-adders explored, the presented WFE approach could in general provide area and performance gains also for other logic building blocks that can be redesigned using SB-FinFETs.

We introduce novel ten (10T) and eight (8T) transistor full-adder logic gates based on recently proposed gate work-function engineering (WFE) approach. When applied to sub-10 nm Schottky-barrier (SB) independent-gate FinFETs, WFE leads to hitherto unexplored 4T and 3T XOR implementations that operate with either only one or no inverted input, respectively. The novel 4T and 3T XOR gates eliminate the need for inverted inputs provided that ambipolar I-V characteristics is shifted by the associated gate work-function in the right direction, where another conduction channel exists. Following the logic verification of the novel 4T and 3T XOR gates via TCAD simulations, we then continue to show how these novel gates can be put to use in building ultra-compact 10T and 8T full-adder circuits, which would normally require up to 20 FinFETs in conventional CMOS architecture. Simulated power-delay products of the novel full-adders show significant (⇠ 5⇥) improvement in dynamic performance attri...

One of the important codes, a gray code is normally used to detect correction of error in digital systems. Gray codes use a binary encoding scheme through grouping of the order of the bits and changing one bit of the group. Quantum-dot cellular automata (QCA) is a promising and a future technology for semiconductor transistor based technologies. We propose an extendable QCA binary to gray code converter in this paper. An Exclusive-OR gate is a core element in binary-to-code converter so we used an XOR gate using Nand-Nor-Inverter (NNI) gate which can simplify to logic circuits. The NNI gates are universal gates and can efficiently design XOR gates. A first proposed design is a 2-bit circuit and we extend it to 3-bit and to 4-bit designs. The proposed circuits are compared to previous designs and it shown its efficiency.

One of the important codes, a gray code is normally used to detect correction of error
in digital systems. Gray codes use a binary encoding scheme through grouping of the
order of the bits and changing one bit of the group. Quantum-dot cellular automata
(QCA) is a promising and a future technology for semiconductor transistor based
technologies. We propose an extendable QCA binary to gray code converter in this paper.
An Exclusive-OR gate is a core element in binary-to-code converter so we used an XOR
gate using Nand-Nor-Inverter (NNI) gate which can simplify to logic circuits. The NNI
gates are universal gates and can efficiently design XOR gates. A first proposed design is
a 2-bit circuit and we extend it to 3-bit and to 4-bit designs. The proposed circuits are
compared to previous designs and it shown its efficiency.Q

We introduce novel ten (10T) and eight (8T) transistor full-adder logic gates based on recently proposed gate work-function engineering (WFE) approach. When applied to sub-10 nm Schottky-barrier (SB) independent-gate FinFETs, WFE leads to hitherto unexplored 4T and 3T XOR implementations that operate with either only one or no inverted input, respectively. The novel 4T and 3T XOR gates eliminate the need for inverted inputs provided that ambipolar I-V characteristics is shifted by the associated gate work-function in the right direction, where another conduction channel exists. Following the logic verification of the novel 4T and 3T XOR gates via TCAD simulations, we then continue to show how these novel gates can be put to use in building ultra-compact 10T and 8T full-adder circuits, which would normally require up to 20 FinFETs in conventional CMOS architecture. Simulated power-delay products of the novel full-adders show significant (⇠ 5⇥) improvement in dynamic performance attri...

A parity generator is a circuit that generates redundant bits used for error detection
and is used when transmitting binary information. Previous parity generator circuits
based on quantum-dot cellular automata (QCA) are designed to reduce the area of the
circuit. Input cells of existing circuit are designed inside the circuit and the circuit’s
signal is not propagated properly due to the influence between adjacent wires. In
addition, existing circuits consume many clocks because the XOR gate, which is an
essential component of the parity generator circuit, consumes many clocks. In order to
solve this problem, we design a 3-bit odd parity generator circuit using QCA for fast
operation. The proposed circuit uses an XOR gate that can operate one clock faster
than the existing XOR gate to reduce the clock, and by extending this XOR gate, the
output value can be obtained faster than the conventional circuit. In the proposed
circuit, the result is verified through simulation and the performance is compared with
the existing circuit.

A parity generator is a circuit that generates redundant bits used for error detection and is used when transmitting binary information. Previous parity generator circuits based on quantum-dot cellular automata (QCA) are designed to reduce the area of the circuit. Input cells of existing circuit are designed inside the circuit and the circuit’s signal is not propagated properly due to the influence between adjacent wires. In addition, existing circuits consume many clocks because the XOR gate, which is an essential component of the parity generator circuit, consumes many clocks. In order to solve this problem, we design a 3-bit odd parity generator circuit using QCA for fast operation. The proposed circuit uses an XOR gate that can operate one clock faster than the existing XOR gate to reduce the clock, and by extending this XOR gate, the output value can be obtained faster than the conventional circuit. In the proposed circuit, the result is verified through simulation and the performance is compared with the existing circuit.

Surface plasmon polaritons (SPPs) may serve as ultimate data processing expedients in future nanophotonic applications. SPPs combine the high localization of electrons with the bandwidth, frequency, and propagation properties of photons, thus supplying nature with the best out of two worlds. However, although plasmonics have recently gained constantly growing scientific attention, logic devices that operate on SPPs in deep nanometer scale are yet to be demonstrated. In this chapter, we present the preliminary design, fabrication, and experimental verification of the smallest all-optical nanoplasmonic XOR logic gate.

In modern era, the number of transistors are reduced in the circuit and ultra low power design have emerged as an active research topic due to its various applications. A full adder is one of the  essential component in digital  circuit design, many improvements have been made to reduce the architecture of a full adder.The main aim of this paper is to reduce the power dissipation and area by redusing the number of transistors.By using general logic of   pmos transistor, the two transistor xor gate can be implemented.  In this paper proposes the novel design of a 2T XOR gate. The design has been compared with earlier proposed 3T, 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An 8-T full adder has been designed using the proposed 2-T XOR gate and its performance has been obtained. the design is simulated in Mentor graphics tool .

We present a web-based environment along with an interactive interface for VLSI schematic design, simulation, and layout design. It consist of 10 experiments starting from transistor level design of inverter, then some basic gates such as NAND, NOR, XOR etc, finally design of D latch and flip flop. In each experiment student will learn how to design VLSI circuits both schematic and layout. It also consists of experiment components such as objective, introduction, quiz, and theory etc. which gives step by step explanation of each experiment. It is a powerful self learning supplement for the VLSI design course offered in undergraduate engineering program. Along with teaching schematics and layouts of circuits, this virtual lab also consists of some experiment explaining about SPICE coding, VHDL and Verilog coding. An interactive panel is given in which student will write programming codes, simulate and see real time waveforms. The web based schematic and layout editor is designed to m...