COSC 243

Computer Architecture
And
Operating Systems

COSC 243 (Computer Lecture 6 - Memory and Storage 1

Architecture) Systems
 Overview
• This Lecture
– Memory and Storage Systems
– Source: Chapters 4, 5.1, 6
– Reading assignment
• Section 5.1: Semiconductor Main Memory
• Chapter 6: External Memory
– Read magnetic disk section (6.1) in detail
– Understand general concepts of RAID section (6.2)
– Read Optical memory section (6.3)
• Next Lecture
– Input/Output

COSC 243 (Computer Lecture 6 - Memory and Storage 2

Architecture) Systems
 Memory Hierarchy

COSC 243 (Computer Lecture 6 - Memory and Storage 3

Architecture) Systems
 Memory Hierarchy (cont)
• Registers
– 8-64 typical
• Cache
– 2K-512K typical
– Level 1 and Level 2
• Main memory
– 512MB - 4GB
• Secondary storage
Disk, . . .
COSC 243 (Computer Lecture 6 - Memory and Storage 4
Architecture) Systems
 Memory Hierarchy (cont)
• Tradeoffs
– Shorter access time -> Greater cost per bit
– Greater capacity -> Smaller cost per bit
– Greater capacity -> Longer access time
• Going down the hierarchy diagram
– Decreasing cost per bit
– Increasing capacity
– Increasing access time
– Decreasing frequency of access by CPU
COSC 243 (Computer Lecture 6 - Memory and Storage 5
Architecture) Systems
 Secondary Storage
• External to the CPU
• Access via a bus
• Bus examples
– IDE
– EIDE
– USB
– Firewire
– ATA, SATA
COSC 243 (Computer Lecture 6 - Memory and Storage 6
Architecture) Systems
 Secondary Storage (cont)
• Secondary storage examples
– Disk
– USB drive
– Memory cards (cameras, etc)
– Tape
– CD-ROM
– DVD

COSC 243 (Computer Lecture 6 - Memory and Storage 7

Architecture) Systems
 Magnetic Disk

COSC 243 (Computer Lecture 6 - Memory and Storage 8

Architecture) Systems
 Magnetic Disk (cont)

COSC 243 (Computer Lecture 6 - Memory and Storage 9

Architecture) Systems
 Magnetic Disk (cont)

COSC 243 (Computer Lecture 6 - Memory and Storage 10

Architecture) Systems
 Characteristics of Magnetic
Disk
• Number of platters
• Single vs. two sided
• Number of tracks
• Number of sectors per track
• Number of bytes per sector
• Cylinders

COSC 243 (Computer Lecture 6 - Memory and Storage 11

Architecture) Systems
 Speed Characteristics of
Magnetic Disk
• Seek time
• Rotational latency
• Access time
• Block transfer time
• Which is longest?

COSC 243 (Computer Lecture 6 - Memory and Storage 12

Architecture) Systems
 RAID
• Redundant Array of Inexpensive
(Independent) Disks
• A set of disk drives is viewed by the OS
as a single logical drive
• Data is distributed across drives
• Parallelism
• Redundant disk capacity used to store
additional bits for reliability
COSC 243 (Computer Lecture 6 - Memory and Storage 13
Architecture) Systems
 RAID (cont)

COSC 243 (Computer Lecture 6 - Memory and Storage 14

Architecture) Systems
 RAID (cont)

COSC 243 (Computer Lecture 6 - Memory and Storage 15

Architecture) Systems
 CD-ROM

COSC 243 (Computer Lecture 6 - Memory and Storage 16

Architecture) Systems
 Other Media
• Writable versions of CD
• DVD
• Writable versions of DVD
• Tapes
• Memory cards (cameras, etc)

COSC 243 (Computer Lecture 6 - Memory and Storage 17

Architecture) Systems
 Primary Storage
• Often called main memory
• Unique address for each location
• n address bits can address 2n locations
• Access one word at a time
• Basic operations are read and write
• Storage cells exhibit two stable states: 0, 1
• Can be written into (at least once) to set the
state
• Can be read to sense the state

COSC 243 (Computer Lecture 6 - Memory and Storage 18

Architecture) Systems
 Operation of Memory
• Example (assuming 8 bit address and data sizes)

Read Write

Address Memory Data bus

Basic Memory Structure

COSC 243 (Computer Lecture 6 - Memory and Storage 19

Architecture) Systems
 Operation of Memory (cont)
• Read
– Load the address register with 175
– Set the read control signal
– Some time later, the contents of word 175, 38 in this
example, will be on the data output lines of the memory
• Write
– Load the address register with 175
– Load the data buffer register with the new contents of word
175
– Set the write control signal
– Some time later, the contents of word 175 will have the new
value.

COSC 243 (Computer Lecture 6 - Memory and Storage 20

Architecture) Systems
 Properties of Main Memory
• Random access (RAM)
– Same access time to access any memory
location
– Contrast to tapes and disks
– Synonymous with read-write memory
• Cycle time
– Minimum time required between two
successive read or write operations
– Physical property of the memory

COSC 243 (Computer Lecture 6 - Memory and Storage 21

Architecture) Systems
 Properties of Main Memory
(cont)
• Access time
– Delay between the start and finish of a
memory operation - usually measured in
nanoseconds (10-9) or picoseconds (10-12)
• Volatility
– Semiconductor RAM memories lose data
when power is removed.
– Disks and tape retain data for years
– Some memories have battery backup
COSC 243 (Computer Lecture 6 - Memory and Storage 22
Architecture) Systems
 Properties of Main Memory
(cont)

COSC 243 (Computer Lecture 6 - Memory and Storage 23

Architecture) Systems
 Static vs. Dynamic Memory
• Static
– No action is required to maintain a stored value
• Dynamic
– Value stored as a charge on a capacitor
– Gradually disappears
– Must be recharged continually (refreshed)
– Read operation is destructive so special circuitry is
included to rewrite the contents after a read
– 1-2 millisecond refresh interval
– Refresh by dummy reads when not in use

COSC 243 (Computer Lecture 6 - Memory and Storage 24

Architecture) Systems
 Static vs. Dynamic Memory
(cont)
• Comparison
– Dynamic cells are smaller (1/4) than static
– Dynamic is cheaper
– Dynamic requires less chips

COSC 243 (Computer Lecture 6 - Memory and Storage 25

Architecture) Systems
 Types of Memory

COSC 243 (Computer Lecture 6 - Memory and Storage 26

Architecture) Systems
 A Typical Static RAM
• Convenient for small memories
• 2048 (211) words of memory
• 11 address lines
• Each word is 8 bits wide
• 8 data lines
• 2 control signals

COSC 243 (Computer Lecture 6 - Memory and Storage 27

Architecture) Systems
 A Typical EPROM
• Similar to a static RAM
• Erasable by exposure to ultraviolet light of the correct
wavelength

COSC 243 (Computer Lecture 6 - Memory and Storage 28

Architecture) Systems
 A Typical Dynamic RAM

COSC 243 (Computer Lecture 6 - Memory and Storage 29

Architecture) Systems
 A Typical Dynamic RAM
(cont)
• 4M x 4
• 22 address bits normally required
• Only 11 pins available owing to technological
limitations on the number of pins
• 22 bits are multiplexed on the eleven pins
• Organised as 2048 x 2048 array (4,194,305) which
are addressed separately by row and column (RAS
and CAS)
• 4 bits of data in each location
• Refresh by cycling through all rows of memory with
RAS low and CAS high

COSC 243 (Computer Lecture 6 - Memory and Storage 30

Architecture) Systems
 Other Memory Issues
• Simultaneous multiple word access
• Parity
• ECC

COSC 243 (Computer Lecture 6 - Memory and Storage 31

Architecture) Systems
 Cache Memory
• Memory is slow compared to the time
required to execute instructions.
• Memory becomes more expensive as it
gets faster
• Compromise
– Place a small amount of very high speed
memory to temporarily hold a portion of the
memory being accessed.

COSC 243 (Computer Lecture 6 - Memory and Storage 32

Architecture) Systems
 Cache Memory (cont)
• If the addressed location is in cache, it
is used. Otherwise a block of memory
is transferred from memory to cache.
• Principle of locality

COSC 243 (Computer Lecture 6 - Memory and Storage 33

Architecture) Systems
 Cache Memory (cont)

COSC 243 (Computer Lecture 6 - Memory and Storage 34

Architecture) Systems
 Cache Memory (cont)

COSC 243 (Computer Lecture 6 - Memory and Storage 35

Architecture) Systems
 Cache Memory (cont)

COSC 243 (Computer Lecture 6 - Memory and Storage 36

Architecture) Systems
 Cache Memory (cont)
• Performance is measured by hit ratio
• Typical hit ratios are 0.9 - 1.0
• Update of main memory
– Write through - write memory when cache
is updated
– Write behind (back) - a flag (valid bit)
indicates cache location was changed.
Write memory when cache must be
reused.
COSC 243 (Computer Lecture 6 - Memory and Storage 37
Architecture) Systems
 Cache Examples
• Main memory is 16 MBytes
– 24 bit address
– Byte addressable
• Memory block is 4 bytes
• Memory is 4M blocks of 4 bytes each

• Cache can hold 64 KBytes

• Cache is 16K lines of 4 bytes each

COSC 243 (Computer Lecture 6 - Memory and Storage 38

Architecture) Systems
 Cache Mapping
• Direct mapping cache
• Associative cache
• Set Associative cache

COSC 243 (Computer Lecture 6 - Memory and Storage 39

Architecture) Systems
 Direct Mapping Cache
• Least expensive form
• Maps each block of main memory into only one
possible line of cache
Cache Line Main memory blocks assigned
0 0, m, 2m, . . ., 2s-m
1 1, m+1, 2m+1, . . ., 2s-m+1
2 2, m+2, 2m+2, . . ., 2s-m-2
.
.
.
m-1 m-1, 2m-1, . . ., 2s-1

COSC 243 (Computer Lecture 6 - Memory and Storage 40

Architecture) Systems
 Direct Mapping Cache (cont)

i = j modulo m
where
i = cache line number
m = number of lines in the cache
j = main memory block number

COSC 243 (Computer Lecture 6 - Memory and Storage 41

Architecture) Systems
 Direct Mapping Cache (cont)
• Split the full address into tag, line, and
word fields
• Address the cache with the line
• Check that the tag in cache matches
tag field of address

COSC 243 (Computer Lecture 6 - Memory and Storage 42

Architecture) Systems
 Direct Mapping Cache (cont)

COSC 243 (Computer Lecture 6 - Memory and Storage 43

Architecture) Systems
 Direct Mapping Cache (cont)
• w=2
– (4 words in each cache line)
• s = 22
• r = 14
– (16K lines of cache)
• s-r = 8

COSC 243 (Computer Lecture 6 - Memory and Storage 44

Architecture) Systems
 Associative Cache
• Most expensive form
• No fixed mapping between main
memory and cache lines
• Split the full address into tag and word
fields
• Comparison between the required
address tag and all stored tags is done
simultaneously
COSC 243 (Computer Lecture 6 - Memory and Storage 45
Architecture) Systems
 Associative Cache (cont)
• Cache replacement is typically round
robin, FIFO(first in first out), or LRU
(least recently used)
• w=2
• s = 22

COSC 243 (Computer Lecture 6 - Memory and Storage 46

Architecture) Systems
 Associative Cache (cont)

COSC 243 (Computer Lecture 6 - Memory and Storage 47

Architecture) Systems
 Set Associative Cache
• Cost compromise
• Cache is split into v sets of k lines
• number of lines in cache = v * k
i = j modulo v
where
i = cache set number
j = main memory block number
v = number of sets in the cache

COSC 243 (Computer Lecture 6 - Memory and Storage 48

Architecture) Systems
 Set Associative Cache (cont)
• A main memory block Bj can be
mapped into any of the lines of set i
• Several main memory blocks map to
the same set, but can be put into any of
the lines of the set
• Split the full address into tag, set, and
word fields
• Common values of k (number of lines in
a set) are 2, 4
COSC 243 (Computer Lecture 6 - Memory and Storage 49
Architecture) Systems
 Set Associative Cache (cont)
s+w Cache
Main Memory
Tag Data
Memory Address
B0
Tag Set Word
Set 0
s-d d w B1

B2

Set 1
X Bj
X
s+w
Compare

(hit in cache)

(miss in cache)

Two-way set associative cache organisation

COSC 243 (Computer Lecture 6 - Memory and Storage 50

Architecture) Systems
 Set Associative Cache (cont)
• w=2
– (4 words in each cache line)
• s = 22
• d = 13
– (1 less than before since there are one-half
as many sets as the 16 K lines of cache)
• s-d = 9

COSC 243 (Computer Lecture 6 - Memory and Storage 51

Architecture) Systems
 Cache Replacement
Algorithms
• LRU
– least recently used
• FIFO
– first in first out
• LFU
– least frequently used

COSC 243 (Computer Lecture 6 - Memory and Storage 52

Architecture) Systems
 Other Cache Issues
• Single vs. 2-level cache
• Unified vs. split cache

COSC 243 (Computer Lecture 6 - Memory and Storage 53

Architecture) Systems