Computer Organization and Architecture

CSEN 2202
Lecture 9 – 10
03/02/2020

Dr. Debranjan Sarkar

Different addressing modes
(Class III : Address field is memory address)
• Memory Direct (or absolute) addressing mode
• Instruction contains the memory address of the operand explicitly
• If there are 2m memory locations, m bits are required for address field
• Not necessary to calculate effective address
• Example:
• STA 2500H (Store the content of accumulator in memory location 2500H)
• Memory indirect addressing mode
• The instruction specifies a memory address in its address field which holds the address of the operand in
memory (show figure)
• Advantage: Flexibility because of the scope of changing the address during run-time, without changing the
instruction
• Useful for implementing pointers in C language
• Disadvantage: Instruction cycle time increases as there are two memory access
• Example: MOV R1, (X) (The content of the memory location whose address is given in X is moved into
register R1)
Different addressing modes
(Class IV : Address field does not contain an effective
address)
• The Effective Address (EA) is calculated from the following relation:
• EA = address part of the instruction + Content of a special register

• Relative (or PC-relative) addressing mode

• EA = address part of the instruction + content of Program Counter (PC)
• Specifies the memory address of operand as the relative position of the
current instruction address
• Generally, used to specify relative branch instruction
Different addressing modes
(Class IV : Address field does not contain an effective
address)
• Indexed addressing mode
• EA = address part of the instruction + content of Index Register (XR)
• Useful in accessing operand array
• The address part of the instruction gives the starting address and the index register
contains an index value for the operand
• The index value for the operand is the distance between the starting address and the
address of the operand
• Base register addressing mode
• EA = address part of the instruction + content of Base Register (BR)
• Used for relocation of the program in the memory
• Relocation means moving program or data segments from one part of memory to another
• Relocation is an important feature of multiprogramming systems
Complex Instruction Set Computer (CISC)
• Design of Instruction set – an important aspect
• Early computers had small and simple instruction sets
• Because hardware was very costly
• With the advent of Integrated circuits,
• Computer instructions tended to increase in number and complexity
• Many computers had more than 100 or even > 200 instructions
• Variety of data types
• Large number of addressing modes
• A computer with a large number of instructions is called Complex
Instruction Set Computer (CISC)
Reduced Instruction Set Computer (RISC)
• In early 1980’s, computer designers recommended
• Computers should use fewer instructions
• Instructions should have simple constructs
• Instructions can be executed much faster within the CPU
• Not necessary to use memory very often
• A computer with a reduced number of instructions is called Reduced
Instruction Set Computer (RISC)
CISC vs. RISC Architecture
Complex Instruction Set Computer Reduced Instruction Set Computer
(CISC) (RISC)
• More instructions for complex tasks • Reduced number of instructions
• Complex instructions require relatively • This lowers processor cost, without much
complex processing circuits, and too much impact on performance.
expensive • Simple addressing modes (Register, Register
• More complex addressing modes (auto- indirect etc.)
increment, auto-decrement etc.) • Large register set
• Small number of General Purpose Registers • uniform (no distinction between e.g. address
(GPR) and data registers)
• Variable-length Instruction formats • All instructions have same length (one word)
(spanning more than one word) • More suitable for pipelining
• Less suitable for pipelining
CISC vs. RISC Architecture
Complex Instruction Set Computer Reduced Instruction Set Computer
(CISC) (RISC)
• Operands for the arithmetic / logic • Operands for the arithmetic / logic
operations may be in the register or in operations are always in the registers
memory
• Memory-to-memory data transfer not
• Memory-to-memory data transfer possible
possible
• Fewer instructions executed per program
• More instructions executed per
• Complex instructions reduce program size
but does not necessarily translate into faster program
execution • Though the program size is more,
• Not constrained to load/store architecture. overall execution is faster
Typically use two-operand instruction format, • Instruction Set Architecture: Load/ store
with at least one operand in a register
CISC vs. RISC Architecture
Complex Instruction Set Computer Reduced Instruction Set Computer
(CISC) (RISC)
• As the number of memory access is • Reduces the impact of von Neumann
more, the impact of von Neumann bottleneck by reducing the total
bottleneck is more number of the memory access made
• Mostly micro-programmed control by the CPU
units • Mostly hardwired control unit
• Example of CISC (IBM 370/168, VAX • Example of RISC (MIPS, SUN Sparc,
11/780, Intel x86, PDP-11, Motorola Intel i860, Motorola 88000, IBM
68000 etc.) RS6000, PowerPC, ARM etc.)
 Module 2
Memory & I/O Organization
Memory Hierarchy
• What is memory?
• Needed for storing program and data
• We want memory to be
• Fast
• Large
• Inexpensive
• Problems of meeting all these requirements simultaneously
• Basic parameters in choosing memory
• Capacity
• Speed (Access time)
• Bandwidth or data transfer rate
Memory Hierarchy
• Level (i) Type (Characteristics)
• 0: Internal Memory (Registers) (Highest speed and cost, least capacity)
• 1: Cache Memory (SRAM)
• 2: Main Memory (DRAM, ROM)
• 3: Disk Storage (Solid State, Magnetic)
• 4: Backup Storage (Mag Tape, Optical disk) (Slowest, Inexpensive, maximum capacity)
or Auxiliary Memory

• Parameters for each level

• Access time (ti) : ti-1 < ti
• Memory Size (si) : si-1 < si
• Cost per byte (ci) : ci-1 > ci
• Data transfer rate or Bandwidth (bi) : bi-1 > bi
• Unit of transfer (xi) : xi-1 < xi
Memory Hierarchy
Auxiliary memory
(not presently being used)

Magnetic
Tapes
IO Processor Main
Memory

Magnetic
Disks

Cache
(Heavily used
CPU
By
CPU)
Memory Hierarchy
• Registers
• Parts of processor
• Register assignment is made by the compiler
• Register transfer operations are directly controlled by the processor
• Register transfer takes place at processor speed (one clock cycle)
• Some designers may not consider register as a level in memory hierarchy
• Caches
• Multi-level caches are built either on processor chip or on processor board
• On-chip cache is faster than off-chip cache
• Cache is controlled by the Memory Management Unit (MMU)
• Cache is programmer-transparent
• As processor speed has increased at a faster rate than memory speed, multi-level cache system has
become essential
• There could be separate instruction cache and data cache
Memory Hierarchy
• Main Memory
• Also known as Primary memory
• Much larger in size than the cache
• Much smaller in size than the secondary storage
• Implemented by the most cost-effective RAM chips (Dynamic RAM)
• Managed by a Memory Management Unit (MMU) in cooperation with OS
• Disk Drives
• Highest level of online memory
• Holds the system program (OS, compilers), User programs and the data sets
• Also available in the form of RAID
• Backup Storage
• Optical disks and magnetic tape units are offline memory
• Used for archival and backup storage
• Holds copies of present and past user programs, data, processed results and files
Main Memory
• Random Access Memory (RAM)
• Static RAM
• Contains Flip Flops that store binary information
• Volatile (information erased when electrical power is off)
• Easier to use and shorter read and write cycles
• Dynamic RAM
• Stores information in the form of electric charges applied to capacitors
• Capacitors are provided inside the chip by MOS transistors
• Capacitors must have to be recharged by refreshing the dynamic memory
• Refreshing is done every few milliseconds to restore the decaying charge
• Reduced power consumption and larger storage capacity per chip
• Read Only Memory (ROM)
• Storing programs that are permanently resident in the computer
• Storing tables of constants that do not change
Memory Technology
• Different types of semiconductor memory
• Non-Volatile Memory
• Read Only Memory (ROM)
• Programmable Read Only memory (PROM)
• Electrically Erasable Programmable Read Only memory (EEPROM)
• Flash memory
• Volatile Memory
• Random Access Memory (RAM)
• Static Random Access Memory (SRAM)
• Dynamic Random Access Memory (DRAM)
• Synchronous DRAM (SDRAM)
• Rambus DRAM (RDRAM)
Memory Technology (RAM)
• Static Random Access Memory (SRAM)
• Six transistors per cell or bit
• Refreshing not required
• More power efficient
• Access time is much faster compared to DRAM
• Used as cache memory
• Package density is poor compared to DRAM
• More expensive than DRAM and not used as Main memory
• Dynamic Random Access Memory (DRAM)
• Each memory cell consists of a single transistor and a capacitor
• Presence or absence of charge designates bit 1 or 0
• Stored charge tend to decay over time due to leakage
• Charge on the capacitor needs to be refreshed periodically (~ 1msec)
• Refreshing does take time and increases the latency of DRAM
• Advantage: Package density is high, so the cost per bit is low
• Disadvantage: Access time is rather large and leakage current makes it power hungry
• DRAM is used as main memory and not as cache memory
Memory Technology (Dynamic RAM)
• Synchronous Dynamic Random Access Memory (SDRAM)
• Normally DRAM uses asynchronous memory access
• When a memory access request is issued by the CPU, the time by which the requested
data become available, is unpredictable
• In SDRAM, memory access is synchronized by the processor clock
• In Double Data Rate (DDR) SDRAM, data transfer takes place both in the rising and the
falling edge of the clock
• This results in faster data transfer rate and memory access time
• Rambus Dynamic Random Access Memory (RDRAM)
• Developed by Rambus Inc in collaboration with Intel
• Advantage: Faster access time than SDRAM
• Disadvantage: Larger power consumption
Inclusion, Coherence and Locality
• Information stored in a memory hierarchy (M1, M2, …, Mn) should
satisfy three important properties:
• Inclusion
• Coherence
• Locality
• Consider cache memory the innermost level M1, which directly
communicates with CPU registers
• The outermost level Mn contains all the information words
• The collection of all addressable words in Mn forms the virtual address
space of a computer.
Inclusion property
• The inclusion property is mathematically stated as
• M1 is a subset of M2 which is a subset of M3 ……Mn-1 which is a subset of Mn)
• All information items are originally stored in Mn
• During processing, subsets of Mn are copied into Mn-1
• Similarly, subsets of Mn-1 are copied into Mn-2 , and so on.
• If an information word is found in Mi, then copies of the same word would be found in
all upper levels Mi+1, Mi+2, Mi+3, ………., Mn
• A word stored in Mi+1 may not be found in Mi.
• A word miss in Mi implies that it is also missing in from all lower levels Mi-1, Mi-2, ………., M1.
• The highest level is the backup level, where everything can be found.
Coherence property
• Requires that the copies of the same information item at successive memory
levels be consistent
• If a word is modified in cache, then copies of that word must be updated
immediately or eventually at all higher levels
• Frequently used information is often found in the lower levels in order to
minimize the effective access time of the memory hierarchy.
• Two strategies for maintaining the coherence in memory hierarchy:
• Write Through (WT): This demands immediate update in Mi+1 if a word is modified in
Mi, for i = 1, 2, 3, …, n-1
• Write Back (WB): This delays the update in Mi+1 until the word being modified in Mi is
replaced or removed from Mi.
Locality of reference
• Memory references are generated by the CPU for
• Instruction
• Data
• These accesses tend to be clustered in certain regions in
• Time
• Space
• Ordering
• A typical program spends 90% of its execution time on only 10% of the codes, such as,
innermost loop of a nested looping operation.
• Three type of locality:
• Temporal
• Spatial
• Sequential
Locality of reference
• Temporal Locality
• Recently referenced items (instruction/ data) are likely to be referenced again in near future
• Iterative loops, process stacks, temporary variables, subroutines
• Once a loop is entered or a subroutine is called, a small code segment will be referenced repeatedly many
times
• Spatial locality
• Tendency of a process to access items whose addresses are near one another
• Example: Operations on tables or arrays
• Program segments such as routines and macros, tend to be stored in the same neighbourhood of memory
space
• Sequential locality
• Normally the execution of instructions follow a sequential order, unless there is a branch instruction.
• Normally, the ratio of in-order execution to out-of-order execution is 5:1
• The access of a large data array also follows a sequential order.
Thank you