1

Vector Control of Three-Phase Front End

Converter (FEC)





N
vs1
vs2
vs3
is1
is2
is3
Ls
Rs
Ls
Rs
Ls
Rs
T1 T3 T5
T4 T6 T2
C
Ro
Vdc








2
I. INTRODUCTION

A three-phase AC to DC converter is often used to obtain a DC supply from three-
phase AC mains. Typical applications are UPS, battery charger, static frequency changer,
motor drives etc. As this type of converter is normally connected at the front end / utility
end of most of the power electronic systems, these are also called the front-end converter
(FEC). The use of three-phase diode/thyristor bridge rectifiers, as the frond-end converter
lead to the degradation in the power quality due to the input current distortion caused by
them. In the attempt to reduce their effects, various standards (IEEE-519 and IEC-555)
and recommendations have been introduced in order to limit the harmonics that an
individual load can inject into the utility.
The input current distortion caused by the bridge rectifiers (diode/thyristor bridge) can
be reduced by using a bulk input filter or harmonic traps. Sometimes it is also required to
have a converter with bi-directional power flow capability as in drives applications. In
such applications the attractive solution is to use a three-phase PWM AC to DC
converter. Hence the ideal requirements of an FEC are,
1. Sinusoidal input current at any given power factor (preferably unity)
2. DC bus voltage control
3. Bi-directional power flow
4. Fast dynamic response
- Should be able to track DC bus voltage reference and power reference
quickly.
The FEC can be controlled in a number of ways to satisfy the above objectives. In this
report the vector control approach is explained in detail along with the design of the
controller.

II. VECTOR CONTROL

In vector control method, the control is done on a rotating reference frame where the
sinusoidal quantities (voltage, current) appear stationary. It is easier to handle the active
3
and reactive powers separately. The controllers handle the DC quantities. Hence the
following points can be concluded,
- Decoupled control of active and reactive power
- Easy reference generation
- Controllers handle DC quantity

A. Three-phase PWM FEC

Fig.1 shows a three-phase PWM ac-dc converter. It has a three-phase PWM inverter.
The three-phase input is connected to the output of the three-phase inverter through three
inductors. The power circuit is similar to that of any three-phase electrical machine when
fed from a three-phase inverter. Three balanced input phase voltages v
s1,
v
s2
and v
s3
can be
thought of as the motor per-phase back emf with L
s
and R
s
as the per-phase inductance
and resistance respectively. The input to the system is the output of the three-phase PWM
inverter.
N
vs1
vs2
vs3
is1
is2
is3
Ls Rs
Ls Rs
Ls Rs
T1 T3 T5
T4 T6 T2
C
Ro
Vdc
Fig.1
v
i1
v
i2
v
i3

Let us define the input voltages as follows,

1
0
2
2 cos( ).......................................................................................(1)
2 cos( 120 )...........................................................................(2
=
=
s s
s s
v V t
v V t

0
3
)
2 cos( 240 )...........................................................................(3) =
s s
v V t

4
Where V
s
is the rms value of the phase voltage. Transforming these voltages from three-
phase to two-phase stationary a-b reference frame we have,

3
2 cos( )...................................................................................(4)
2
3
2 sin( )..................................................................................
2
=
=
sa s
sb s
v V t
v V t

..(5)


The voltage space vector
s
v can be defined as

3
2 ........................................................................(6)
2
= + =
j t
s sa sb s
v v jv V e



Similarly considering any arbitrary phase angle, we can write the current space vector as

( )
3
2 ....................................................................(7)
2

= + =
j t
s sa sb s
i i ji I e



Here a synchronous d-q reference frame, similar to vector control of electrical machines,
is selected such a way that the voltage space vector
s
v is directed along q axis as shown
in Fig.2 The reason for aligning
s
v along q axis is that in case of rotating electrical
machine the d axis represents the machine flux and q axis the input voltage.


a
b
q
d
s
v

Fig.2

5
Similar analogy is followed here. However it is possible to direct
s
v along d axis. In the
present report we will consider the previous convention, i.e. q-axis corresponds to the
active power and d-axis corresponds to the reactive power.
Writing KVL (Fig.1) around the input side of the FEC,

1
1 1 1
2
2 2 2
................................................................................(8)
.........................................................................
= + +
= + +
s
s i s s s
s
s i s s s
di
v v L R i
dt
di
v v L R i
dt
3
3 3 3
.....(9)
..............................................................................(10) = + +
s
s i s s s
di
v v L R i
dt

Where v
i1
, v
i2
and v
i3
are the voltages across the output terminals of the inverter. The
equations (8-10) correspond to the three-phase, three-winding systems of any three-phase
rotating electrical machines. These can be transformed to equivalent two-phase two
winding system with same L
s
and R
s
. Multiplying both sides of (8) by 3/2 and then
multiplying both sides of (9) and (10) by
3
2
we have
1
1 1 1
2
2 2 2
3
3
3 3 3 2
.........................................................(11)
2 2 2
3
2
3 3 3
...........................................(12)
2 2 2
3 3
2 2




= + +






= + +


=
s
s i s s s
s
s i s s s
s
d i
v v L R i
dt
d i
v v L R i
dt
v
3
3 3
3
2
3
............................................(13)
2




+ +


s
i s s s
d i
v L R i
dt


Subtracting (13) from (12) and using three-phase to two-phase transformation, we
have the corresponding equations in a-b reference frame as
...........................................................................(14)
...........................................................................(1
= + +
= + +
sa
sa ia s s sa
sb
sb ib s s sb
di
v v L R i
dt
di
v v L R i
dt
5)

6
These equations can be written in terms of space phasor as

.............................................................(16) = + = + +
s
s sa sb i s s s
d i
v v jv v L R i
dt


Where
i
v is the voltage space phasor corresponding to inverter output voltages v
i1
, v
i2

and v
i3
. Equation (16) represents the space phasor equation in a-b (stationary) reference.

a
b
q
d
s
v

s
i
I
sd
I
sq

V
sq

Fig.3

This needs to be transferred to synchronously rotating d-q reference frame. Referring to
Fig.3 let us assume that the d-q frame is rotating counterclockwise direction at the
synchronous speed ( =2f) with f as the supply frequency in Hz. The d axis is
making an angle with respect to stationary a axis. The voltage and current space
phasors
s
v and
s
i are shown in the same figure. It is assumed that the current space
phasor
s
i is lagging the voltage space phasor by an angle , which is the power factor
angle. Equation (6) and (7) define the space phasors with respect to stationary a-b
reference frame. The same quantities can be defined with respect to synchronously
rotating d-q reference frame as,

0 ...........................................................................(17) = + = +
s sd sq sq
v v jv jv

.............................................................................................(18) = +
s sd sq
i i ji
7
The same space phasors can also be expressed with respect to stationary a-b reference
frame as

( ) ( ) ( )
0 ...................................(19) = + = + = +
j j
s sa sb sd sq sq
v v jv v jv e jv e

( ) ( )
................................................................(20) = + = +
j
s sa sb sd sq
i i ji i ji e


( ) ( )
...............................................................(21) = + = +
j
i ia ib id iq
v v jv v jv e



Substituting (19 21) in (16) the space phasor equation with respect to stationary a-b
reference frame becomes

( ) ( ) ( ) ( )
( ) ( ) ( ) ( )
0
j j j j
sq id iq s sd sq s sd sq
j j j j j
sq id iq s sd sq s sd sq s sd sq
d
jv e v jv e L i ji e R i ji e
dt
d d
jv e v jv e L e i ji jL i ji e R i ji e
dt dt

+ = + + + + +


= + + + + + + +




The above equation is still in stationary a-b reference frame. This can be transformed
to synchronously rotating d-q reference frame by multiplying both sides of it by
j
e

as,

( ) ( ) ( ) ( )
..........(22)

= + + + + + + +


sq id iq s sd sq s sd sq s sd sq
d d
jv v jv L i ji jL i ji R i ji
dt dt

Equation (22) represents the space phasor equation of the system with respect to
synchronously rotating d-q reference frame. Separating the real and imaginary parts of
(22), we have two sets of equations corresponding to d-axis and q-axis respectively as
follows,
0...........................................................................(23)
...............................................................
+ + =
+ + + =
id s sd s s sq s sd
iq s sq s s sd s sq sq
d
v L i L i R i
dt
d
v L i L i R i v
dt

..........(24)


Rearranging the above equations, we have,

8
'
'
( )..........................................................(25)
(say)...................................................(26)
+ = + =
+ = + =
s sd s sd id s s sq id
s sq s sq iq s s sd sq iq
d
L i R i v L i v say
dt
d
L i R i v L i v v
dt

The left hand sides of the above two equations (23) and (24) corresponds to simple R-
L circuit of first order type. This is called the plant. The right hand sides of the same two
equations correspond to the DC excitations to the respective plants (also shown in fig.4).

'
( )
id id s s sq
v v L i = +
Ls
Rs
isd
Ls
Rs
isq
'
( )
iq iq s s sd sq
v v L i v = +
d-axis
q-axis
Fig.4


III. CONTROL OF FEC

There are two quantities to be controlled
(i) DC bus voltage
(ii) Input current
Hence there are two control loops
(1) DC bus voltage control loop
(2) Current control loop
In the control circuit DC bus voltage control loop is the outer loop as it is much slower
compared to inner current control loop. The control block diagram of the FEC is shown
in figure 5.
9



+
+
+
-
+
-
-1
*
ia
v
*
dc
V
dc-fb
V
*
sq
i
sq-fb
i
''
iq
v
s s sd
L i
G
sq
v
G
+
-
-1
*
ib
v
s s sq
L i
G

''
id
v
+
-
+
-
*
sd
i
sd-fb
i
d-axis current
controller
q-axis current
controller
DC bus Voltage
controller
Feed forward term
e
j
d-q to a-b
transformation
Two-ph
to
Three-ph
a-b to three-phase
transformation
*
iq
v
*
id
v
cos sin
1
*
i
v
3
*
i
v
2
*
i
v
1
*
i
v
3
*
i
v
2
*
i
v
Sine-Triangle
P WM
Three-phase
inverter
1
G
2
G
3
G
4
G
5
G
6
G
Vs1
Vs2
Vs3
is1
is2
is3
Ls Rs
Ls Rs
Ls Rs
is1
is2
vs1
vs2
dc
V
dc-fb
V
DC bus voltage
sensor
V
i1
V
i2
V
i3
vs1
vs2
Vs1+Vs2+Vs3=0
vs1
vs2
Three-ph
to
two-ph
Three-phase to
a-b transformation
Two-ph to
d-q transformation
e
j
vsa
vsb
cos sin
vsd
vsq
vs3
is1+is2+is3=0
Three-ph
to
two-ph
is1
is2
is1
is2
Three-phase to
a-b transformation
Two-ph to
d-q transformation
e
j
isa
isb
cos sin
isd-fb
isq-fb is3
Fig. 5



10
IV. FEED FORWARD / DECOUPLING TERMS

Equation (23) shows that d axis current
sd
i is not only depend on the d axis voltage
but also on q axis current
sq
i . Similarly q axis current
sq
i (equation (24)) depends
on the d axis current
sd
i . Referring to Fig.5, the control objectives are as follows.
1. The d axis controller output
''
id
v should only drive d axis current

sd
i through d axis plant as per equation (27).
''
.............................................................................(27) + =
s sd s sd id
d
L i R i Gv
dt


2. The q axis controller output
''
iq
v should only drive q axis current

sq
i through q axis plant as per equation (28).

''
..............................................................................(28) + =
s sq s sq iq
d
L i R i Gv
dt


Where G is the converter gain. Equating right hand sides of equations (25) and (27)
we have,

[ ]
[ ]
[ ]
''
''
''
*
* ''

1
1
........................................................................................(29)
1
+ =

=


=


=

id s s sq id
id id s s sq
s s sq
id id
id id
s s sq
id id
v L i Gv
v Gv L i
L i
v v G
G
v v G
L i
v v
G

................................................................(30)

Similarly equating right hand sides of equations (26) and (28) we have,


11
[ ]
[ ]
[ ]
''
''
''
*
*

1
1
.....................................................................................(31( ))
1
iq s s sd sq iq
iq iq s s sd sq
sq
s s sd
iq iq
iq iq
iq iq
v L i v Gv
v Gv L i v
v
L i
v v G
G G
v v G a
v v

+ =

= +


= +


=
=
''
...................................................(31( ))
sq
s s sd
v
L i
b
G G

+




Equation (30) and (31) may be used to find out the required feed forward terms for d-
axis and q-axis control. This is also shown in fig.5.

V. DESIGN OF CONTROLLERS

(1 )
V V
V
K ST
ST
+
+_
(1 )
C C
C
K ST
ST
+
+_
1
d
G
ST +
+_
1
SC
2
2
1
K
ST +
1/
1
S
S
R
ST +
1
1
1
K
ST +
K
L
I
*
dc
V
. dc fb
V
*
sq
I
. sq fb
I
sq
I
dc
V
Fig. 6

Fig. 6 shows the block diagram of the entire system (controller and plant) of q-axis
only. The d-axis system will be similar to this and not reproduced here. In this diagram it
is assumed that all feed forward terms are accurately acting on the system.
K
V
:Voltage controller gain
K
C
:Current controller gain
K
1
:Gain in the voltage sensing path
K
2
:Gain in the current sensing path
T
V
:Voltage controller time constant
T
C
:Current controller time constant
T
1
:Voltage sensing path time constant
12
T
2
:Current sensing path time constant
T
d
:Converter delay (normally T
s
/2)
T
s
:Switching time period =1/f
sw
.
I
L
:Load current.
K : A constant. May be found out from input-output power balance as follows

Considering unity power factor case,
Total power =V
dc
.I
dc
=
( ) ( )
2 2
2
3 . 3. .
3 3 2 3 2
sq sq
rms phase rms phase sq sq
V I
V I V I

= =



( )
2
.
3
2 2
3 3
sq
dc sq sq
dc
sq LL Rms
dc dc
V
I I K I
V
V V
K
V V
= =

= =


.(32)

A. Design of current loop

The current loop is shown in Fig. 7. Using T
S
=T
C
it is possible to cancel out the
effect of plant time constant. With this, the close loop transfer function may be obtained
as given below. Here a damping factor of =0.707 has been considered to obtain the
expression for K
C
.

+_
(1 )
C C
C
K ST
ST
+
1
d
G
ST +
2
2
1
K
ST +
1/
1
S
S
R
ST +
*
sq
I
. sq fb
I
sq
I
Fig. 7

It should be noted that here the second order pole (1+ST
d
)(1+ST
2
) has been approximated
as a first order (1+S (T
d
+T
2
)) with =T
d
+T
2.
This is because the operating region is
13
close to zero frequency and both frequencies ((1/T
2
) and (1/T
d
)) are far away from that.
Hence for the purpose of controller design such approximation is valid.

( )
( )
( )
( )
( )
( )
2
*
2 2
2
*
2 2
2
*
2
2
*
2
2
( ) / (1 )
(1 )(1 ) /
( )
( )
/ (1 )
(1 ( )) /
( )
( )
/ (1 )
(1 ) /
( )
(1 )
( )
( )
sq
C s
s d C s
sq
sq
C s
s d C s
sq
sq
C s
s C s
sq
C
sq
s s
C sq
s s
I s K G R ST
ST ST ST K G R K
I s
I s
K G R ST
ST S T T K G R K
I s
I s
K G R ST
ST S K G R K
I s
K G
ST
I s
RT
S K GK I s
S
RT

+
=
+ + +
+

+ + +
+
=
+ +

+


=
+ +



2
2
2
1 1
2 ; ;
2
2
n
C
n
s s
s s
C
C S
K GK
R T
R T
K
GK
T T

= =
=
=
=


With this the current controller transfer function is given in (33).

( )
( )
2
*
2 2
2
( ) 1
1
............................................................................(33)
( ) 1 2 2
sq
sq
I s ST
K
I s S S
+
=
+ +


It should be noted that the presence of any pole in the feed back loop (1+ST
2
), appears
as zero in the close loop transfer function. In order to cancel out its effect, the reference
to the current controller may be modified as shown in Fig. 8. With this the overall
transfer function of the current loop is given by (34).

( )
2
*
2 2
( )
1/
( ) 1 2 2
sq
sq
I s
K
I s S S
=
+ +
....(34)

14

+_
(1 )
C C
C
K ST
ST
+
1
d
G
ST +
2
2
1
K
ST +
1/
1
S
S
R
ST +
*
sq
I
. sq fb
I
sq
I
2
1
1 ST +
Fig. 8


B. Design of voltage loop

The outer voltage control loop is shown in Fig. 9. Here the inner current loop transfer
function has been approximated as

( )
2
*
( )
1/
1 2
( )
sq
sq
I s
K
S
I s

=
+


The reasons behind this are as follows,
1. To realize the current loop as a first order system for the purpose of design.
2. The outer voltage loop is much slower compared to it.
3. Multi-order systems are difficult to design.


+_
2
1/
1 2
K
S +
+
1
1
1
K
ST
K
*
dc
V
. dc fb
V
+ (1 )
v v
v
K ST
ST
1
CS
dc
V
Fig. 9


15
The order of the system, even after approximation, is more than two. The zero of the
voltage controller may not be used to compensate the pole (1+2S) because in that case
there will not be any S term present, in the characteristic equation as shown in (35).

1
* 2
1 2 1
( ) (1 )
(1 ) ( )
dc V
V V dc
V s K K ST
ST CK T S K KK V s
+
=
+ +
...(35)

This will lead to instability. Hence to design the outer voltage loop a different method
needs to be followed. Here will follow the method of symmetric optimization.
Loop gain is given in (36)

1 2
1
(1 )/
( ) ( )
(1 2 )(1 )
V V
V
K KK ST K
G S H S
ST S ST CS
+
=
+ +
..(36)

The speed loop is much slower compared to current loop. Hence the following
approximation holds good.

1 1
(1 2 )(1 ) (1 (2 ) ) 1 S ST T S S + + + + = +

Where =T
1
+2. With this the loop gain is given in (37)

1
2
1
2
(1 ) (1 )
( ) ( )
(1 ) (1 )
V V e V
V V
V
e
K KK ST K ST
G S H S
K ST S CS ST S CS
K KK
K
K

+ +
= =

+ +

=
(37)

Here the poles of the system are (ST
V
), (SC) and (1+S). Of these we can control only
(ST
V
) as the others like (CS) is decided by the plant and (1+S) is decided by the current
loop. Now the task is to place the pole (ST
V
) in appropriate position to ensure sufficient
16
gain margin and phase margin. As the pole (CS) is associated with dc bus capacitor (large
valued) we can set the following inequalities.

1 1 1 1
; and
V
C T C
<< <<

Now we dont have idea about the relative positions of (1/T
V
) and (1/) as T
V
is not
yet decided. Let us consider both possibilities.

Case (a)
1 1
V
T
>

The corresponding gain and phase plots are given in Fig. 10. Hence in this case we
have phase margin equal to (-+180
0
), which is a negative quantity. Hence the above
assumption leads to instability.













Case (b)
1 1
V
T
<

dB
P
h
a
s
e
180
270

1
C
1

1
V
T
c

Fig. 10
17
The corresponding gain and phase plots are given in Fig. 11. Hence in this case we
have phase margin equal to (-+180
0
), which is a positive quantity. Hence the above
assumption leads to a stable design.











Next question is where to place the crossover frequency
C
in between (1/T
V
) and
(1/). The standard procedure is to place
C
in the geometrical mean of them. Let us
consider (T
V
=a
2
). Where a is any number 2,3,4 With this the expression for
C

becomes

1
C
a

=

The objective is to select the proper value of K
e
of equation (37) such a way that

2
2 2
2
2
1
substituting the expression for
1 ( )
( ) ( ) 1
1 ( )
;
;
C
e
e c V
c V c
e
V V
K
K T
G j H j
CT
C
K
a
CK
K and T a
K Ka

=
+
= =
+
=
= =

dB
P
h
a
s
e
180
270

1
C
1

1
V
T
c

Fig. 11
18
The expression for phase margin is given below

( )
1 1
1
tan tan
m
a
a

=


.

As an example, for a =2,
m
=36
0
. Hence selecting a suitable a, desired phase
margin may be achieved.


+_
2
1/
1 2
K
S +
K
*
dc
V
. dc fb
V
+ (1 )
V V
V
K ST
ST
1
CS
dc
V
1
1
1
K
ST +
( ) ( )
1
1
1 1
V
ST ST + +
Fig. 12


As mentioned earlier, the presence of pole (1+ST
1
) will also appear as zero in the
overall transfer function. Referring to (37) one additional zero (1+ST
V
) will also appear
in the close loop transfer function. Hence to cancel out their effect the voltage reference
may be modified as shown in Fig. 12.

C. Load current feed-forward

Load current feed-forward may be added in the controller to improve the dynamic
response of the system. In order to do this the load current is required to sense using a
current sensor. Equation (32) is reproduced in (38). This relates the steady state load
current I
dc
with I
sq
.

2
.
3
sq
dc sq sq
dc
V
I I K I
V
= = (38)
19

At steady state the output of the voltage controller should be zero and the load current I
dc

should set the reference current for the q-axis current controller as shown in Fig. 13. I
L(fb)

is the sensed load current.

+
+
+
-
+
-
-1
*
ia
v
*
dc
V
dc-fb
V
*
sq
i
sq-fb
i
''
iq
v
s s sd
L i
G

sq
v
G
+
-
-1
*
ib
v
s s sq
L i
G

''
id
v
+
-
+
-
*
sd
i
sd-fb
i
d-axis current
controller
q-axis current
controller
DC bus Voltage
controller
Feed forward term
e
j
d-q to a-b
transformation
Two-ph
to
Three-ph
a-b to three-phase
transformation
*
iq
v
*
id
v
cos sin
1
*
i
v
3
*
i
v
2
*
i
v
+
L
(fb)
I
1
K

Fig. 13












20

Three-phase shunt active filter


I. INTRODUCTION

As mentioned in the previous section, three-phase diode bridge rectifiers or six-pulse
thyristor converters are extensively used in many high-power low-cost applications
leading the degradation in the power quality due to the current distortion. In the attempt
to reduce their effects, various standards (IEEE-519 and IEC-555) and recommendations
have been introduced in order to limit the harmonics that an individual load can inject
into the utility. The input current distortion caused by bridge converter (Diode/Thyristor
bridge) may be reduced by connecting a PWM rectifier. Again, there are applications,
where a dc bus voltage less than the peak line-line ac voltage is required. This may not be
achievable in case of a PWM boost rectifier without using an additional conversion stage.
Thus in many applications it is proffered to use six-pulse thyristor/diode rectifier
compared to PWM rectifier. To meet the rigid harmonic standard an active power filter
may be used at the input to the rectifier. The filter will supply only the harmonic currents
to the rectifier while the fundamental component of current will be supplied from the
input source
Active filter is actually a voltage source inverter connected in parallel to the point of
common coupling (PCC) between utility and grid. Active filters are employed for
reactive current and harmonic current compensation. The voltage source inverter is
controlled in such a way, as to inject the reactive and harmonic current demanded by the
utility.
Fig. 1 shows the single line block diagram of a system containing a six-pulse rectifier
and an active power filter. It is assumed that a large inductor is connected at the dc bus of
the phase controlled rectifier to make the dc bus current constant. The nature of input
current drawn by the rectifier is also shown in Fig. 1. It has fundamental and harmonic
components. The active filter is required to supply locally the harmonic component of the
21
load current to the rectifier. The input source supplies the fundamental component of the
load current.













II. CONTROL OF ACTIVE FILTER

Assumptions:

1.The load is balanced in nature.
2.There is no control over the voltage at the point of common coupling.

Load currents are required to get the information of amount of harmonic current and
reactive current demanded by the non-linear load. In this present study, a phase-
controlled rectifier is taken as a non-linear load (Fig 1).

3-2 phase Transformation

AC
i s(t) iL (t)
i c(t)
A cti ve Fi l ter
Phase control l ed
Recti fi er
I l oad
Control l er
i l 1,i l 2
i c1,i c2
vs12,vs23
V dc
Gate pul ses
(G1-G6)
Fig. 1
22
















Fig. 2

In the above figure, is the angle between stationary a-axis and d-axis. The d-q axes
is rotating at a speed of (2 f ) with respect to stationary coordinate (a-b), where f is
the line frequency. If at t=0, q-axis is aligned with a-Axis, then at any time instant, t the
angle between q-Axis and a-Axis is t . d-Axis is lagging q-Axis by 90 degree. Hence,

( ) ( ) ( )
( ) ( ) ( )
2
i i
la l1
3
3
i i i
lb l2 l3
2
t t 1a
t t t
=
=


..................................................................................................................................
..................................... ( ) 1b ...........................................................................
a-Axi s
b-Axi s
d-Axi s
q-Axi s

t
23
( ) t 2
2

= .........................................................................................................................


2-Phase-DQ Transformation













ld
I and
lq
I are the dc components of the load current corresponding to the fundamental
component.

ld
i t ( ) and

lq
i t ( ) correspond to the harmonic components of i
L
.

Applying KCL at the point of common coupling (PCC),

( ) ( ) ( ) ( )
( ) ( ) ( )
1 1 1
2 2 2
s c l
s c l
i t i t i t 5a
i t i t i t
= +
= +
......................................................................................................
.................................................................... ( )
( ) ( ) ( ) ( )
3 3 3
s c l
5b
i t i t i t 5c = +
.................................
.....................................................................................................


1 2 3
s s s
i i i , , are the source currents for R,Y and B phases respectively.
( ) ( ) ( ) ( )
( ) ( ) ( )
ld la lb
lq lb la
i i
i i
i t t t 3a
i t t t
= +
=
.................................................................................................................................
.......................
.cos sin
.cos sin ( ) 3b ..........................................................................................................

( )

ld ld ld
lq lq lq
i t I i t 4a
i t I i t
= +
= +
( ) ( )..........................................................................................................
( ) ( ).......................................................... ( ) 4b ................................................
24
are the compensator currents for R,Y and B phases respectively.
1 2 3
l l l
i i i , , are the load currents for R,Y and B phases respectively.

In space phasor notation, KCL can be written as,

( ) ( ) ( ) ( ) ( ) ( ) ( )
sa sb ca cb la lb
i t ji t i t ji t i t ji t 6 + = + + +

..................................................
Multiplying both side of the above equation with
j
e

, we get

( ) ( ) ( ) ( ) ( ) ( )
j j j
sa sb ca cb la lb
i t ji t e i t ji t e i t ji t e

+ = + + +


(7) + = + + +
sd sq cd cq ld lq
[ i ( t ) ji ( t )] [ i ( t ) ji ( t )] [ i ( t ) ji ( t )].............................................

Equating real and imaginary part of the above equation we get,

(8.a) = +
= +
sd cd ld
sq cq lq
i ( t ) i ( t ) i ( t ).....................................................................................................
i ( t ) i ( t ) i ( t )...................................................... (8.b) ...............................................


Equation. (8.b) can be written as,


(9) + = + + +
sq sq cq cq lq lq
I i ( t ) ( I i ( t )) ( I i ( t )).......................................................................

If we equate the DC components from the both sides of the equation

(10) = +
sq cq lq
I I I .................................................................................................................

As the shunt active filter is not drawing active power from the grid, active power
demanded by the load is totally supplied by the source.

1 2 3
c c c
i i i , ,
25
Hence,
sq lq
I I = and
cq _ ref
I is decided by the DC bus voltage controller, to maintain
the DC bus at its nominal value. If we equate the ac components of the equation. (9)


(11) = +
sq cq lq
i ( t ) i ( t ) i ( t )......................................................................................................

The active filter should work such that, the harmonic current demanded by the non-linear
load is not drawn from the source but supplied by the active filter locally.

Hence,

sq
i ( t ) =0


cq lq
i ( t ) i ( t ) =

Therefore, q-axis current reference can be generated in the following way,

11.a ( )
=
=
DC _ ref DC lq lq
cq _ ref cq _ ref lq
cq _ ref PI(V V ) ( i ( t ) I )
i I i ( t ).................................................................................................
i ....................................... (11.b) ................................................


The dc component of the q-axis load current is generated by employing a low-pass
filter of cut-off frequency of 30 Hz. Equation (8.a) can be written as,


(12) + = + + +
sd sd cd cd ld ld
I i ( t ) ( I i ( t )) ( I i ( t ))...................................................................

If we equate the DC components from the both sides of the equation

(13) = +
sd cd ld
I I I ...................................................................................................................

As the active filter has to compensate for the demanded reactive power by the load
and maintain the desired power factor at source side,

26
(14) =
cd _ref sd _ ref ld
I I I ......................................................................................................

sd _ ref
I , is decided by the operating power factor at the grid side.

Equating the ac components of the equation. (12), we get


(15) = +
sd cd ld
i ( t ) i ( t ) i ( t )......................................................................................................

The active filter should work such that, the harmonic current demanded by the non-
linear load is not drawn from the source but supplied by the active filter locally. Hence,

sd
i ( t )=0


(16) =
cd ld
i ( t ) i ( t )................................................................................................................

Therefore, the d-axis current reference is generated by,

(17.a) =
cd _ ref sd _ref ld ld
i I I i ( t ).......................................................................................

(17.b) =
cd _ ref sd _ref ld
i I i ( t )...............................................................................................

From the knowledge of unit vector and d-q axis current references, current references
in stationary coordinate can be calculated.







(18.a) =
= +
ca _ ref cd _ ref cq _ ref
cb_ ref cq _ ref cd _ ref
i i cos i sin .............................................................................
i i cos i sin .......................................................

(18.b) ......................
27
Figure 3 explains the block diagram of current reference generation.
























Unit Vector Generation

In the previous section, it is well understood that, unit vector (
j
e

) is required for the
ab-dq transformation of load currents and the reverse transformation (dq-ab) of d-q axes
current references (refer fig. 3).
3-2-Phase
Trans.
2-Phase-
DQ
Trans.
DQ-
2-Phase
Trans
-
-
+
+ +
-
il1
il2
il3
ila
ilb
ild
ilq
isd_ref
cos sin cos

sin
Vdc*
+
-
Vdc
ica_ref
icb_ref
cut-off =30Hz
icd_ref
icq_ref
Fig. 3: Block Diagramof Current ReferenceGeneration
28
In order to generate unit vectors (cos ,sin ) synchronized with the grid voltage,
algorithms like Phase Locked Loop (PLL) are generally used. The presence of the
harmonics in the grid voltages results in the distortion of the unit vectors derived from
them. To avoid this kind of problem the following scheme has been adopted to generate
the unit vectors.











Fig. 4: Block Diagram of Unit vector Generation



Let us define the input voltages as follows,

1
0
2
0
3
2 19
2 120 19
2 240
s s
s s
s s
v V cos( t )......................................................................( .a )
v V cos( t )..........................................................( .b )
v V cos( t )........

=
=
= 19 ..................................................( .c )


Where V
s
is the rms value of the phase voltage. Transforming these voltages from three-
phase to two-phase stationary a-b (or -) reference frame we have,

3-phase
to
2 Phase
Transformation
Normalisation
Vs1
Vs2
cut off =50Hz
cut off =50Hz
cut off =50Hz
cut off =50Hz
Vsa
Vsb
cos
sin
Low pass filter
Low pass filter
x
y
29
3
2 20
2
3
2 20
2
sa s
sb s
v V cos( t )..................................................................( .a )
v V sin( t )...................................................................( .b )

=
=


Two low pass filters (in cascade), with cut-off at 50 Hz, are used to generate a delay of
90
0
and also to suppress any noise present in V
sa
and V
sb
(Fig. 3).
As,
2
t

= ,
The outputs of the filters are proportional to cos and sin respectively. These are then
normalized to get the required unit vectors cos and sin.


From figure 4, we can write
21
2 2
21
2 2
s
s
V
x cos( t ) ( .a )
V
y sin( t ) ( .b )

=
=


Therefore, after normalization we get,
2 2
2 2
22
22
x
cos ( .a )
x y
y
sin ( .b )
x y

=
+
=
+


Current controller
Quantities required to be sensed for controller
a) 2, load currents (il1, il2)
b) 2, compensator currents (ic1, ic2)
c) 2, line voltages (vs12, vs23)
d) DC bus voltage (Vdc)
The total system is described in the following figure.
30










Fig. 5: Block Diagram of total Control system

The current reference generator and unit vector generator is described in the previous
section.

Design of Current Controller

Let
1 2 3 f , f , f
v v v be the active filter output phase voltages, then the filter equations can be
written as








1
1 1 1
2
2 2 2
3
3 3 3
23
23
23
c
s s c s f
c
s s c s f
c
s s c s f
di ( t )
v ( t ) R i ( t ) L v ( t ) ( .a )
dt
di ( t )
v ( t ) R i ( t ) L v ( t ) ( .b )
dt
di ( t )
v ( t ) R i ( t ) L v ( t ) ( .c )
dt
= + +
= + +
= + +
Current ref.
generator
Current
controll er
DC bus
voltage
controll er
Pul se-
wi dth
modulator
A cti ve
Fil ter
3-2
phase
trans.
i ca*
i cb*
V dc*
V dc
i l1
i l2
isd*
ica
i cb
Uc1*
Uc2*
Uc3*
G1-G6
+
_
+
-
+
-
ic1
ic2
Uni t
V ector
Genera
tor
Us12
Us23
cos si n
31


Using three phase to two phase transformation, the active filter circuit can be modeled as



The effect of grid voltages,
sa sb
v ( t ),v ( t ) can be compensated using feed forward
technique as shown in the Fig. 6


The plant is represented by a first order lag along with the input voltage terms for both a-
axis and b-axis. The plant equations are as follows,

24
24
ca
s ca s sa fa
cb
s cb s sb fb
di ( t )
R i ( t ) L v ( t ) v ( t ) ( .a )
dt
di ( t )
R i ( t ) L v ( t ) v ( t ) ( .b )
dt
+ =
+ =


The a-axis plant and controller are given in Fig. 6









24
24
ca
sa s ca s fa
cb
sb s cb s fb
di ( t )
v ( t ) R i ( t ) L v ( t ) ( .a )
dt
di ( t )
v ( t ) R i ( t ) L v ( t ) ( .b )
dt
= + +
= + +
1
c c
c
K ( s.T )
.
G s.T
+
1
d
G
sT +
sa
v
G
sa
v
+
-
-
+
*
ca
i
+
-
ca
i
1
1
s s
R ( sT ) +
ca
i
32























Fig. 6
Proportional-Integral Controller parameters are given by,

1
c
c
c
s.T
K
s.T
+
1
d
G
s.T +
1
1
s
s
R
s.T +
1
K
*
ca
i
ca
i
+
-
2
2 2
2
n
n n
s s

+ +
*
ca
i ( t )
ca
i ( t )
1
2
n
d
T

=
33
s
c s
s
L
T T
R
= = ;




If we consider the converter as only gain,
Then the parameters of the PI- controller is given by

s
c s
s
L
T T
R
= = ;
1
s s
c
cl
R T
K
T K G
=


cl
T = Closed loop time constant
1
K =Current sensor gain
G = Converter gain
d
T = Time delay of the converter
= Damping factor for the closed loop system
n
= cut-off frequency of the closed loop transfer function

The resulting current controller is described in block diagram in Fig.7








2
1
4
s s
c
d
R T
K
K GT
=
+
+
-
-
ica_ref
icb_ref
ica
icb
Usa/G
Usb/G
2-3 Phase
Transform
ation
Uc1*
Uc2*
Uc3*
-1
-1
+
+
-
-
34





Fig. 7

















Three-Level Inverters






0
Vdc/2
Vdc/2
T11 T21
T13
T12
T23
T22
T31
T33
T32
P1 P2
P3
35

















The above figure shows the functional equivalent circuit of a three phase three level
inverter realized using ideal switches. Each pole of the three level inverter will have three
voltage levels with respect to mid-point of DC bus referred as o in the figure. Actually,
each phase of the inverter is a single pole triple throw switch.

For example, when pole P1 of phase-R is connected to throw T11
V
RO
=V
dc
/2;
When pole P1 of phase-R is connected to throw T12
V
RO
=0;
When pole P1 of phase-R is connected to throw T13
V
RO
=- V
dc
/2;
Similar way, V
YO
and V
BO
will have three voltage levels (V
dc
/2, 0, -V
dc
/2). The line
voltages will have five voltage levels; - V
dc,
- V
dc
/2, 0, V
dc
/2, V
dc
. (Fig 2)
36
This concept can be extended to M-level inverters. Each pole of M-level inverter will
have M voltage steps and line voltage will have (2M-1) voltage steps. The inverters with
voltage level three or more are referred as multilevel inverters in the literature.
RO
V
YO
V
BO
V
RY
V
dc
V
2
dc
V
2
dc
V
2
dc
V
2
dc
V

2
dc
V

2
dc
V

2
dc
V

2
dc
V
dc
V

3
2
3

4
3
5
3

+
2
2

2
3

+
2
3

5
3

+
5
3


37
Fig 2: Pole voltages (V
RO
,V
YO,
V
BO
) & Line Voltage (V
RY
) of a Three-level
Inverter

For medium voltage application, multilevel inverters are more suitable compared to the
conventional two-level inverters as
It is possible to synthesize the higher voltages using power devices of lower
rating.
o Multilevel inverters offer increased number of voltage levels which leads
to better voltage waveform and reduced total harmonic distortion (THD) at
the output.
o Multilevel inverters offer better performance at low switching frequency.
This results in reduced switching loss.

In figure 1, the switch P1-T11 has to block a voltage of -V
dc
(maximum) when OFF and
has to carry bi-directional current when ON. The switch P1-T13 has to block a voltage of
+V
dc
(maximum) when OFF and has to carry bi-directional current when ON .The switch
P1-T12 has to block a bipolar voltage of V
dc
/2 and has to carry a bi-directional current.


Diode Clamp Inverter

The three level diode clamp inverter is also called neutral point clamped (NPC) inverter.
This is one of the realizations of the functional equivalent circuit of a three level inverter
(Fig. 1). Fig. 3 shows the power circuit of a three phase three level NPC inverter. Node
o indicates the mid point of dc bus. Switches (
1 R
S ,
2

R
S ) of phase R, (
1 Y
S ,
2

Y
S ) of
phase Y and (
1 B
S ,
2

B
S ) of phase B are the main devices operating as modulating
switches for the PWM.
2 R
S ,
1

R
S ,
2 Y
S ,
1

Y
S ,
2 B
S ,
1

B
S are the auxiliary switches to
clamp the output voltage to the mid-point(node o) together with the diodes
1 2 1 2 1 R R Y Y B
D , D , D , D , D and
2 B
D .
38
The switch P1-T11 is realized by (
1 2 R R
S ,S ), P1-T12 is realized by (
2 1 1 2

R R R R
S ,S , D , D )
and P1-T13 is realized by (
1 2

R R
S ,S ). For phase Y and B the switch realization follows as
given below:

P2-T21---------------------------- (
1 2 Y Y
S ,S )
P2-T22---------------------------- (
2 1 1 2

Y Y Y Y
S ,S , D , D )
P2-T23---------------------------- (
1 2

Y Y
S ,S )

P3-T31---------------------------- (
1 2 B B
S ,S )
P3-T32---------------------------- (
2 1 1 2

B B B B
S ,S , D , D )
P3-T33---------------------------- (
1 2

B B
S ,S )

The switch status, definition of state and pole voltage of phase R of three level diode
clamp inverter are given in Table 1


1 R
S
2 R
S
1

R
S
2

R
S
1 R
D
2 R
D V
RO

ON ON OFF OFF OFF OFF +V
dc
/2
OFF ON ON OFF ON OFF 0
OFF ON ON OFF OFF ON 0
OFF OFF ON ON OFF OFF - V
dc
/2

Table 1: Diode clamp inverter: Switch status and definition of state for phase R






1 R
S
2 R
S
1 Y
S
2 Y
S
1 B
S
2 B
S
1 R
D
1 Y
D
1 B
D C
39




















Fig.3: Three level diode clamp inverter


Sine Triangle PWM(SPWM)

SPWM is the most widely used PWM technique for inverters of two and more levels. The
basic principle of the bipolar PWM used in two level inverters is as follows. The
reference signal (
r
v ) which is generally sinusoidal, is compared with the high frequency
triangular wave (
c
v ) of constant amplitude,
c
V . At any instant of time the PWM output
40
will be high (State +) for >
r c
v v and output will be low (State -) for <
r c
v v as
illustrated in fig. 4.
























41
Fig. 4: Pole voltages (V
RO
) and Line voltage (V
RY
) of a Two-level Inverter
operating at fundamental frequency of 50Hz .PWM carrier frequency is 1 KHz.



The modulation index is defined as
r
i
c
V
M
V
= ,
where
r
V is the peak of the reference and
c
V is the peak of the triangle. By varying
r
V
and keeping
c
V constant, that is by varying
i
M , the amplitude of the fundamental
component of the output will be varied. Similarly by varying the frequency of
r
v , the
frequency of the fundamental component of the output waveform can be varied.
The pulse number, P is defined as
sw
s
f
P
F
= ,
where
sw
f is the switching frequency and
s
F is the frequency of
r
v . For two level
inverters,
sw c
f f = , where
c
f is the frequency of
c
v . For three phase inverters, the same
carrier signal
c
v is used for all the three phases and three reference signals are phase
displaced by
2
3

radians are used for each phase. The above principle is easily extended
to three level and other multilevel inverters. Some of the approaches for the
implementation of SPWM for three level inverters are discussed below.

Multiple Carrier Method or Unipolar Modulation

In this method, two carrier signals (
1 2 t t
v ,v ) can be in phase opposition (PO-SPWM) or in
phase (IP-SPWM). In both approaches the switching logic is decided as follows.

42

Condition Switch status for R phase State
RO
V
1
*
R t
v v > and
2
*
R t
v v > 1 2
1 2
R R
R R
S ON,S ON
S OFF,S OFF
= =
= =


+
2
dc
V

1
*
R t
v v < and
2
*
R t
v v > 1 2
1 2
R R
R R
S OFF,S ON
S ON,S OFF
= =
= =


0

0
1
*
R t
v v < and
2
*
R t
v v < 1 2
1 2
R R
R R
S OFF,S OFF
S ON,S ON
= =
= =


-
2
dc
V

For
i
M =1, the fundamental component of the inverter output voltage will be maximum.
The maximum amplitude of the fundamental component is given by
1
2
dc
peak
V
V = and
the RMS value is given by
1
035
rms dc
V . V = .
So the maximum value of
1rms
V in linear modulation range is 78% of that of square wave
output. In this type of SPWM switching will take place between state + and state 0
during the positive half cycle of the fundamental and between state -and state 0 in the
negative half cycle of the fundamental. The switching frequency 2
sw c
f f = , where
c
f is
the frequency of
1 t
v and
2 t
v . Compared to two level inverter, for a given carrier
frequency (
c
f ), the switching frequency (
sw
f ), will be half.

In Fig. 5, the IP-SPWM is explained for one carrier time period ( 1
c c
T f = ). From the
figure the sequence of the inverter states applied for one half of the carrier period (sub-
cycle), are found to be,
00 000 00 0 ( ) ( ) ( ) ( ) + . In the next sub-cycle the sequence retraces the path
it came through and reaches the starting vector. The vectors applied for a total carrier
time period are as below:
1 2 1 2 1 z z
(V V V V V V V )
ur ur ur ur ur ur ur
. The sequence obeys the rule of Space-
Vector PWM for three-level inverter (as shown in Fig. 6).
43































+0 0
0 0 0
0
0
-
0
-
-
0
-
-
0
0
-
0 0 0 +0 0
*
R
v
*
Y
v
*
B
v
1 +
0
1
s
T
s
T
1 t
v
2 t
v
A A
B B
C C
A A
B B
C C
O O
D D D
E E
O
44








Fig. 5. In-Phase Sine Triangle PWM generation for 3-level Inverter






















1
000 V ( , ) +
ur
7
V ( ) +
ur
2
000 V ( , ) + +
ur
8
0 V ( ) +
ur
9
V ( ) + +
ur
O
A B
C D
E
000
z
V ( , , ) + + +
ur
1
T
2
T
3
T
4
T

ref
V
Fig 6: In-Phase Sine-Triangle PWM
45











In Fig. 7, the PO-SPWM is explained for one carrier time period ( 1
c c
T f = ). From the
figure the sequences of the inverter states applied for one half of the carrier period (sub-
cycle), are found to be,
0 00 000 ( ) ( ) ( ) ( ) + + + . In the next sub-cycle it retraces the path it came
through and reaches the starting vector. The vectors applied for a total carrier time period
is as below:
7 8 1 1 8 7 z
(V V V V V V V )
ur ur ur ur ur ur ur
. It does not obey the rule of Space-Vector
PWM for three-level inverter (as shown in Fig. 8). In this case, the applied vectors are not
the vertices of the triangle in which the tip of the reference vector falls.











*
R
v
1 +
1 t
v
A
A A
A
D D
D
1 +
1 t
v
46






























Fig. 7: Phase Opposition Sine Triangle PWM generation for 3-level Inverter
47


























Implementation of Sine-Triangle PWM

For implementation the IP-SPWM is chosen as this method conforms to the rules of
Space-vector PWM while the other method (PO-SPWM) disobeys the rules as explained
in the previous section. Instead of using two carrier signals (of amplitude 1pu), it is also
1
000 V ( , ) +
ur
7
V ( ) +
ur
2
000 V ( , ) + +
ur
8
0 V ( ) +
ur
9
V ( ) + +
ur
O
A B
C D
E
000
z
V ( , , ) + + +
ur
1
T
2
T
3
T
4
T

ref
V
Fig. 8: Phase-Opposition Sine-Triangle
PWM
48
possible to work with only one carrier with an amplitude of 0.5pu.This is achieved by
subtracting 0.5pu from the positive carrier and the positive reference voltages and
adding 0.5pu to the negative carrier and the negative reference voltages (as in Fig. 9).
This method is reported in Reference 1.



























+0 0
0 0 0
0
0
-
0
-
-
0
-
-
0
0
-
0 0 0 +0 0
**
B
v
**
Y
v
**
R
v
1 +
0
1
s
T
s
T
05 . +
05 .
t
v
A A A A
B B B B
C C C
C
O O
D
D D
E E
49











Fig. 9: Steinkes Method for SPWM Generation
Fig. 10 shows the basic structure of this method. The first main block is Sign
identification and shift block. In an initial step, sign of each phase reference voltage is
determined. The three sign signals are sent to the second main block Phase output signal
control. If for example, sign of
*
Y
v is positive, the phase output signal control sets the
switch pair (
2 2

Y Y
S ,S ) to the constant state (
2 2
= =
Y Y
S ON,S OFF ) and connects the
switch pair (
1 1

Y Y
S ,S ) to the output
Y
T of the pulse-width modulator.
If the sign is negative, the switch pair (
1 1

Y Y
S ,S ) is gated to constant state
(
1 1
= =
Y Y
S OFF,S ON ) and connects the switch pair (
2 2

Y Y
S ,S ) to the output
Y
T of the
pulse-width modulator.









Sign
Identification
&
shift
Normal PWM
Generation
Phase output
signal control
*
R
v
*
Y
v
*
B
v
**
R
v
**
Y
v
**
B
v
sign of
* *
R Y
v ,v
and
*
B
v
R
T
Y
T
B
T
1 1 R R
(S / S )
2 2 R R
(S / S )
1 1 Y Y
( S / S )
2 2 Y Y
(S / S )
1 1 B B
(S / S )
2 2 B B
(S / S )
50







Fig. 10: Basic Signal Processing Structure for Steinke,s Method


So, we can summarize the method (Steinke,s Method) for Sine-Triangle PWM for 3-level
Inverter as below:

If
*
x
v >0 then,
**
x
v =
*
x
v 0.5 ---------(1.a)

If
*
x
v <0 then,
**
x
v =
*
x
v +0.5 ---------(1.b)

Where, x =R, Y, B












51
















Fig 11: Pole voltages (V
RO
) and Line voltage (V
RY
) of a Three-level Inverter
operating at fundamental frequency of 50Hz .PWM carrier frequency is 1 KHz.
Modulation Index=0.9.DC bus voltage=600 Volts


Preprocessing of the Phase reference voltages

If working with three-phase reference voltages instead of a voltage space vector, it is not
possible to utilize the whole output range with the phase reference voltage system being
free from a zero sequence voltage system. The whole range may be utilized, if the zero
sequence voltage system is added to the three-phase reference voltages that makes the
absolute values of the maximum and minimum phase reference voltage (after Steinkes
transformation) equal to each other.

Unlike two-level inverter, the common-mode injection function,
52
2
max min
( v v ) / + , does not yield always a centered space vector PWM for three-level
inverter. The injection functions can be derived for a three-level sine-triangle modulator
to achieve centered space vector modulation (CSVPWM) which are tabulated below (Ref
2).


Condition

Common-Mode injection Function
0
mid
v < & 1
max min
( v v ) <
2
min
v

0
mid
v > & 1
max min
( v v ) <
2
max
v

0
mid
v < , 1
max min
( v v ) >
& 1
max mid
( v ) v >
1
2
max
( v )

0
mid
v > , 1
max min
( v v ) >
& 1
min mid
( v ) v + >
1
2
min
( v ) +

Others
2
max min
( v v ) +


Table-2: Common mode voltages for Three-Level Inverter CSVPWM

It is found in the above table that the common mode injection function for three level sine
triangle modulator is not unique, if we work with two carriers signals to generate SPWM
(ref. IP-SPWM).
But, instead of calculating common mode injection function with the original three-phase
reference voltages (
* * *
R Y B
v ,v ,v ), if they are determined using the transformed (Steinkes
Transformation) reference voltages (
** ** **
R Y B
v ,v ,v ) then the expression of the common-
mode voltage is found to be unique.
** ** **
max R Y B
v Max( v ,v ,v ) = -------------------------------------(2.a)

53
** ** **
min R Y B
v Min( v ,v ,v ) = --------------------------------------(2.b)

2
max min
CM
( v v )
v
+
= ----------------------------------------(2.c)
*** *** *** ** ** **
R Y B R Y B CM CM CM
( v ,v ,v ) ( v ,v ,v ) ( v ,v ,v ) = + ------(2.d)


The final Block-Diagram of the scheme for Sine-Triangle modulation for 3-level inverter
is as follows,















Fig. 12

Another alternative scheme has been reported in Ref. 3 for Sine-Triangle modulation for
Three-level Inverter. The scheme is described in the following sections.

Sign
Identification
&
shift
(Equations
1.a
& 1.b)
Normal
PWM
Generation
Phase output
signal
control
*
R
v
*
Y
v
*
B
v
**
R
v
**
Y
v
**
B
v
sign of
* *
R Y
v ,v and
*
B
v
R
T
Y
T
B
T
1 1 R R
( S / S )
2 2 R R
( S / S )
1 1 Y Y
( S / S )
2 2 Y Y
( S / S )
1 1 B B
( S / S )
2 2 B B
( S / S )
Commom-
mode
Voltage
Calculator
(Equations
2.a, 2.b, 2.c
& 2.d)
***
R
v
***
Y
v
***
B
v
54
Assuming that the reference for the three-level inverter is available in the form
REF
V
the nearest pivot vector can be identified. The nearest pivot vector can also be identified
using 3-phase sinusoidal references based on the conditions shown in Table-3. The pivot
vectors can be expressed as three phase quantities (
PNR PNY PNB
v ,v ,v ) as shown in the last
column of Table-3. Subtracting the nearest pivot vector from
* * *
R Y B
( v ,v ,v ) as shown in
equation (3) gives the tentative three-phase reference for the conceptual two-level
inverter.

** ** ** * * *
R Y B R Y B PNR PNY PNB
( v ,v ,v ) ( v ,v ,v ) ( v ,v ,v ) = ---------------------- (3)



Conditions
Nearest Pivot Vector (
PN
V
r
)
Pivot Vector as 3-phase
quantity
PNR PNY PNB
( v ,v ,v )
0
* * * *
R R Y B
*
R
v max( v , v , v )
v
=
>

1
V
r

2 1 1
3 3 3
( , , )
0
* * * *
B R Y B
*
B
v max( v , v , v )
v
=
<

2
V
r

1 1 2
3 3 3
( , , )
0
* * * *
Y R Y B
*
Y
v max( v , v , v )
v
=
>

3
V
r

1 2 1
3 3 3
( , , )
0
* * * *
R R Y B
*
R
v max( v , v , v )
v
=
<

4
V
r

2 1 1
3 3 3
( , , )
0
* * * *
B R Y B
*
B
v max( v , v , v )
v
=
>

5
V
r

1 1 2
3 3 3
( , , )
0
* * * *
Y R Y B
*
Y
v max( v , v , v )
v
=
<

6
V
r

1 2 1
3 3 3
( , , )
55

Table-3





Calculation of Dwell times and switching instants

The maximum and minimum values of
** ** **
R Y B
( v ,v ,v ) are identified as shown in
equations (4.a) & (4.b)

** ** ** **
MAX R Y B
v max( v ,v ,v ) = -----------------------------------(4.a)
** ** ** **
MIN R Y B
v min( v ,v ,v ) = ------------------------------------(4.b)

The middle value is designated as
**
MID
v . We have,
0
** ** **
MAX MID MIN
v v v + + = --------------------------------------(5)

Let an offset voltage
**
OFF
v be added as a zero-sequence component to (
** ** **
MAX MID MIN
v ,v ,v )
to ensure that the dwell time for the pivot vector is equally divided between the two pivot
states.
Then, the value of
**
OFF
v is found to be,
2 2
** ** **
** MAX MIN MID
OFF
( v v ) v
v
+
= = ---------------------------(6)

The offset voltage, added as a zero-sequence component to
** ** **
R Y B
( v ,v ,v ) , yields the
modified three-phase reference for the conceptual two-level inverter
*** *** ***
R Y B
( v ,v ,v ) as
56
shown in (7). The switching instants for the three phase are available from
*** *** ***
R Y B
( v ,v ,v ) .

*** *** *** ** ** ** ** ** **
R Y B R Y B OFF OFF OFF
( v ,v ,v ) ( v ,v ,v ) ( v ,v ,v ) = + ----------(7)

The two-level PWM from
*** *** ***
R Y B
( v ,v ,v ) can be translated into 3-level PWM waveform
using the final pivot vector as shown in Table-4.




Final
Pivot
Vector
2-level
PWM
1 R
S
2 R
S
1 Y
S
2 Y
S
1 B
S
2 B
S
HIGH ON OFF OFF OFF ON OFF
1
V
r

LOW OFF OFF OFF ON OFF ON
HIGH ON OFF ON OFF OFF OFF
2
V
r

LOW OFF OFF OFF OFF OFF ON
HIGH OFF OFF ON OFF OFF OFF
3
V
r

LOW OFF ON OFF OFF OFF ON
HIGH OFF OFF ON OFF OFF OFF
4
V
r

LOW OFF ON OFF OFF OFF OFF
HIGH OFF OFF OFF OFF ON OFF
5
V
r

LOW OFF ON OFF ON OFF OFF
HIGH ON OFF OFF OFF ON OFF
6
V
r

LOW OFF OFF OFF ON OFF OFF

1 1 R R
S S =
2 2 R R
S S =
1 1 Y Y
S S =
2 2 Y Y
S S =
1 1 B B
S S =
2 2 B B
S S =

Table-4

2 000 V ( ) + +
ur
3 0 0 0 V ( , ) +
ur
8 0 V ( ) +
ur
9 V ( ) + +
ur
10 0 V ( ) +
ur
11 V ( ) +
ur
12 0 V ( ) +
ur
57
















Fig. 13: Space-Phasor Diagram for 3-level Inverter
Common mode voltage and Midpoint voltage unbalance of Three-Level Inverter and its
Mitigation



A three-level inverter feeding a three-phase motor is shown in Fig.1 (a). The space
vectors associated with such inverter are shown in Fig. 1(b).

58
Motor
N
R
Y
O
+
-
+
-
S
R1
S
R2
S
Y 1
S
Y 2
S
B1
S
B2
S

R 1
S

R 2
S

Y 1
S

Y 2
S

B1
S

B2
B O
I
R
I
Y
I
B
I
MID
~
~
~


Fig. 1(a) Three-level inverter feeding a three-phase motor

V
1
V
2
V
3
V
4
V
5 V
6
V
7
V
8
V
9
V
10
V
11
V
12
V
13
V
14
V
15 V
16
V
17
V
18
V
z
V
REF
59

Fig. 1(b) Space vectors of three-level inverter
Common mode voltage:

Referring to Fig. 1 (a), the common mode voltage is the voltage between motor neutral
N and the mid-point of the dc bus O. The output pole voltages of the inverter may be
written as,






It is assumed that motor neutral is open. The instantaneous sum of the motor phase
voltages is zero. With this the expression for common mode voltage may be written as,
( )
NO AO BO CO
1
V = V +V +V
3
(1)
The instantaneous sum of the pole voltages however is not zero. Hence there is a finite
potential difference between motor neutral and mid-point of the dc bus. This has a
significant effect on the bearing failures of the motor, which is explained later. The
common-mode voltage of the three-level inverter depends on the applied inverter states,
which are shown in Table-1.

Mid-point current:

Referring to Fig. 1 (a) the mid-point current is the current flowing out of the mid-point
O of the dc bus. Depending on the inverter states the mid-point current is the sum of the
line currents, which are connected to the mid-point. The mid-point current of the three-
level inverter depends on the applied inverter states, which are shown in Table-1.

Fig. 1 (three-level inverter)
60
Table-1

Space-Vectors Inverter-States Common mode
voltage
Mid-point current

1
V
r

(+00) V
dc
/6 -i
R
1
V
r

(0--) -V
dc
/3 i
R

2
V
r

(++0) V
dc
/3 i
B
2
V
r

(00-) -V
dc
/6 -i
B

3
V
r

(0+0) V
dc
/6 -i
Y

3
V
r

(-0-) - V
dc
/3 i
Y
4
V
r

(0++) V
dc
/6 i
R

4
V
r

(-00) - V
dc
/6 -i
R

5
V
r

(00+) V
dc
/6 -i
B

5
V
r

(--0) -V
dc
/3 i
B

6
V
r

(+0+) V
dc
/6 i
Y

6
V
r

(0-0) - V
dc
/6 - i
Y

8
V
r

(+0-) 0 i
Y

10
V
r

(0+-) 0 i
R

12
V
r

(-+0) 0 i
B

14
V
r

(-0+) 0 i
Y

16
V
r

(0-+) 0 i
R

18
V
r

(+-0) 0 i
B

7
V
r

(+--) - V
dc
/6 0
9
V
r

(++-) V
dc
/6 0
61
11
V
r

(-+-) - V
dc
/6 0
13
V
r

(-++) V
dc
/6 0
15
V
r

(--+) - V
dc
/6 0
17
V
r

(+-+) V
dc
/6 0
z
V
r

(000) 0 0
z
V
r

(+++) V
dc
/4 0
z
V
r

(---) - V
dc
/4 0


Mitigation of common mode voltage and mid-point current:

Referring to the inverter states (Fig. 1(b)) the space vectors
1
V
r
-
6
V
r
are pivot vectors,
which correspond to the zero states of a two-level inverter. Each pivot vector consists of
two inverter states. The dwell time for each pivot vector can be divided into any fraction
between its two-inverter states. This does not affect the fundamental component of the
pole voltage of the inverter. This strategy can be used to mitigate the common-mode
voltage problem in case of three-phase motor (fed by a three-level inverter) and mid-
point current issues in case of a three-level inverter.
Mitigation of common mode voltage:

Referring to Fig. 2, let us consider a case when the reference vector V
REF
is encircled
by vectors V
1,
V
7
and V
8
. The switching sequence |(+00)-(+0-)-(+--)-(0--)||(0--)-(+--)-(+0-
)-(+00). The common-mode voltage associated with each of the applied inverter states are
given in Table-2. The dwell time for the pivot vector V
1
is T
1
. Let us consider the
inverter state (+00) is applied for duration (K.T
1
), while the inverter state (0--) is applied
for a duration of [(1-K)T
1
]. The common-mode voltage averaged over a switching sub-
cycle can be made zero by proper selection of K. The fraction K is calculated using
equations (2) and (3).

62

V
1
V
7
V
8
V
9
V
2
V
0
V
REF
(+0 -)
(+0 0)
(0 - -)
(+- -)
(T
1
) (T
7
)
(T
8
)


Fig. 2




Table-2
Common mode voltage (pu)
Vdc =1pu
(+0 0) (0 - -) (+0 -) (+- -)
K.T
1 (1-K).T
1
T
8
T
7
(1/6) (0) (-1/6) (-1/3)
Switching state
Dwelling time


(1/6).K.T
1
+0.T
8
+(-1/6).T
7
+(1-K)T
1
.(-1/3)

=0 (2)

6
1
T 2
K = +
3 3T
(3)
63

Mid point current:

Considering the same reference vector V
REF
as shown in Fig. 2 the mid-point current
associated with each of the applied inverter states are given in Table-3. Similar to the
common-mode voltage mitigation technique, the mid-point current averaged over a
switching sub-cycle can also be made zero by proper selection of K. The fraction K is
calculated using equations (4) and (5).

Table-3
(+0 0) (0 - -) (+0 -) (+- -)
K.T
1 (1-K).T
1
T
8
T
7
(-I
R
) (I
Y
) (0) (I
R
)
Switching state
Mid point current
Dwelling time


-I
R
.K.T
1
+I
Y
.T
8
+0.T
7
+(1-K)T
1
.I
R
=0 (4)

1
8 Y
R T
T I
K =0.5 +0.5
I







(5)









64








Effect of Common mode voltages

Recently in the literature it is found that there are number of cases of motor bearing
failures by bearing currents particularly when the motor is fed from a PWM inverter. It is
investigated that the presence of common mode voltage (between motor neutral and the
mid-point of the dc bus) and the capacitive coupling between stator winding and the rotor
surface are responsible for driving a current through motor bearings. This is reported in
this section.














Motor
N
C1
C2
+
+
_
_
O
A
B
C
+
_
Fig. 1
65

Referring to Fig. 1, the common mode voltage is the voltage between motor neutral N
and the mid-point of the dc bus O. The output pole voltages of dc-ac inverter may be
written as,






It is assumed that motor neutral is open. The instantaneous sum of the motor phase
voltages is zero. With this the expression for common mode voltage may be written as,
( )
1
3
NO AO BO CO
V V V V = + +
The instantaneous sum of the pole voltages however is not zero. Hence there is a finite
potential difference between motor neutral and mid-point of the dc bus. Let us see its
effect on the motor.

As per IEEE recommended grounding practices,
(1) The motor enclosure is grounded for personal and equipment safety.
(2) The mid point of the dc bus is normally grounded through some finite low
impedance to make the fault current flow to actuate the relays in case of motor
insulation failure. This is because the dc bus may be obtained through an isolation
transformer at the input side and a bridge rectifier.

Referring to Fig. 2, different capacitive couplings inside a motor that may cause bearing-
current may be realized as follows.
(1) Between stator winding conductors and rotor metal surface (through air gap and
winding insulation)
(2) Oil film, which acts as insulator
66
It should be noted that though the magnitude of the common mode voltage is less but due
to stepped nature the dv/dt is high. This high dv/dt causes a significant amount of
capacitive current to flow through these stray capacitances. The path for such currents is
shown in Fig. 2. The current enters in the rotor surface from stator winding and flows
thorough rotor shaft and finally returns to the mid-point of the dc bus through bearing oil
film and motor enclosure. It should be noted that the oil film is not an ideal capacitor.
When the rotor shaft rotates the oil film capacitance between the balls and bearing races
frequently discharges. The discharge current cause pitting on the race and also dries up
the oil film. Both of these cause increased bearing friction and finally bearing failure.


















Fig. 2
Ball
Oil flim
Shaft
Rotor
Stator winding
Stator winding