ECEN 326 LAB 1

Design of a Common-Emitter BJT Amplifier

1 Circuit Topology and Design Equations

General configuration of a single-supply common-emitter BJT amplifier is shown in Fig. 1.

Isupply

VCC (1−k)RB RC
CC
I1 VC Vout
CB IB RL
Vin Q1
CE
VE
Rin
kRB RE RG

Figure 1: Common-Emitter BJT Amplifier

For β-insensitive DC biasing, the base current (IB ) should be negligible compared to I1 :

IC VCC IC VCC βVCC

IB  I1 ⇒  ⇒ N = ⇒ RB = , N ≥ 10 (1)
β RB β RB N IC

Small-signal AC voltage gain (Av ) can be expressed as

 
 vout  R C k RL RC k R L
Av =  = ⇒ re + (RE k RG ) = (2)
vin  re + (RE k RG ) Av

Input resistance of the amplifier (Rin ) is usually included in the given specifications. It can be calculated as

Rin = kRB k (1 − k)RB k (β + 1)[re + (RE k RG )] ≈ k(1 − k)RB k β[re + (RE k RG )] (3)

Substituting RB from (1) and [re + (RE k RG )] from (2) into (3) results in
   
βVCC RC k R L β
Rin = k(1 − k) k β = (4)
N IC Av N IC Av
+
k(1 − k)VCC RC k R L

To maximize the available output swing, load-line analysis needs to be performed. Assume that the transistor’s DC
operating point is set to (IC , VCE ). The following equation can be obtained from the DC equivalent circuit of Fig. 1

VCC = IC RC + VCE + VE ⇒ VCE = VCC − IC RC − VE (5)

AC load line, which shows the relationship between the AC signals ic and vce , passes through the DC bias point
(IC , VCE ). The slope of the line depends on the AC resistance at the collector and emitter terminals. For the common-
emitter amplifier circuit in Fig. 1, the slope can be found as
∆ic 1
=− (6)
∆vce (RC k RL ) + (RE k RG )

1
 ic

DC bias point
IC

vce
0 VCE
VCE,sat 2VCE−VCE,sat For maximum
symmetrical swing

Figure 2: AC load line

Therefore, the load line equation can be obtained as

ic − IC 1
=− (7)
vce − VCE (RC k RL ) + (RE k RG )

To obtain the maximum symmetrical swing, the DC bias point should be at the middle of the available region. Since
the minimum value for vce is VCE,sat , the maximum value of vce corresponding to ic = 0 should be (2VCE −VCE,sat ),
as shown in Fig. 2. Evaluating the load-line equation at the point (ic , vce ) = (0, 2VCE − VCE,sat ),
0 − IC 1
=− (8)
2VCE − VCE,sat − VCE (RC k RL ) + (RE k RG )
which can be arranged as
IC [(RC k RL ) + (RE k RG )] = VCE − VCE,sat (9)
Substituting VCE from (5) into (9) results in

IC [(RC k RL ) + (RE k RG )] = VCC − IC RC − VE − VCE,sat (10)

which can be arranged as

VX
IC = (11)
RC + (RC k RL ) + (RE k RG )
where
VX = VCC − VE − VCE,sat (12)
From (2), Av  1 implies (RC k RL )  (RE k RG ). Therefore, (11) can be simplified as
VX
IC ≈ (13)
RC + (RC k RL )
0-to-peak voltage swing can be calculated as
VX
Vsw = IC (RC k RL ) = (14)
RC
2+
RL
Substituting IC in (13) into (4), Rin can be expressed as
β(RC k RL )
Rin = (15)
N VX 1
+ Av
k(1 − k)VCC RC
2+
RL

2
2 Design Procedure
1. VCC , VCE,sat and β should be given together with the design specifications, which usually include Rin , Av ,
0-to-peak output swing (Vsw ), and RL . In addition, the design should be insensitive to variations in β and VBE .
2. First, choose the value of VE . Increasing VE results in more stable bias current in the presence of VBE variations,
however it decreases the available voltage swing at the collector. If the resistor RE is replaced with a DC current
source, VE should be sufficiently large to allow proper operation of the source.
3. Calculate VX and k as follows
VE + 0.7
VX = VCC − VCE,sat − VE , k=
VCC
Also choose N such that N ≥ 10.
4. Determine the minimum value of RC using the specification for the desired input resistance (Rin,d ):

β(RC k RL )
≥ Rin,d
N VX 1
+ Av
k(1 − k)VCC RC
2+
RL
which can be arranged as
2 2
RC (βRL − Rin,d Av ) + RC (2βRL − 3Rin,d Av − QRin,d )RL − RL Rin,d (Q + 2Av ) ≥ 0

where
N VX
Q=
k(1 − k)VCC

5. Determine the maximum value of RC using the specification for the desired output voltage swing (Vsw,d ):

VX
≥ Vsw,d
RC
2+
RL
which can be arranged as  
VX
RC ≤ RL −2
Vsw,d

6. Choose RC , then calculate IC

VX
IC ≈
RC + (RC k RL )

7. Calculate RB and RE
βVCC VE
RB = , RE =
N IC IC
8. Find RG from
R C k RL
re + (RE k RG ) =
Av
which can be arranged as
1
RG =
1 1
 −
RC k RL RE
− re
Av

3
3 Pre-Lab
Using a Q2N2222 BJT, design a common-emitter amplifier with the following specifications:
VE ≥ 1 V Rin ≥ 5 kΩ 0-to-peak unclipped swing at Vout ≥ 1.6 V
VCC = 5 V |Av | = 40 Operating frequency: 5 kHz
RL = 10 kΩ Isupply ≤ 1.5 mA

1. Show all your calculations and final component values.

2. Verify your results using PSPICE. Submit all necessary simulation plots showing that the specifications are
satisfied. Also provide the circuit schematic with DC bias points annotated.

3. Using PSPICE, perform Fourier analysis and determine the input and the output signal amplitudes resulting in
5% total harmonic distortion (THD) at the output. Submit transient and Fourier plots, and the distortion data
from the output file.
4. Be prepared to discuss your design at the beginning of the lab period with your TA.

4 Lab Procedure
1. Construct the common-emitter amplifier you designed in the pre-lab.
2. Measure IC , VE , VC and VB . If any DC bias value is significantly different than the one obtained from Pspice
simulations, modify your circuit to get the desired DC bias before you move onto the next step.
3. Measure Isupply , Av , Rin , and Rout .
4. Measure the maximum unclipped output signal amplitude.
5. Apply the input signal level resulting in 5% THD at the output, and measure the input and output signal ampli-
tudes.
6. Prepare a data sheet showing your simulated and measured values.
7. Be prepared to discuss your experiment with your TA. Have your data sheet checked off by your TA before
leaving the lab.