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    CPU With Systems Bus

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    Tanafe
    The document discusses CPU registers and instruction pipelines. It covers: 1) CPU registers include general purpose registers for temporary storage, control/status registers like the program counter, and other specialized registers. The number of general purpose registers is typically between 8-32. 2) Instruction pipelines break down instruction execution into stages to overlap processing of multiple instructions. A basic pipeline may have fetch, decode, execute, and writeback stages. More complex pipelines can have 6 stages. 3) Pipelining improves performance but requires techniques like branch prediction to handle conditional jumps which can disrupt the pipeline flow. Common techniques include predicting branches as not taken, prefetching branch targets, and maintaining a loop buffer.

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    CPU With Systems Bus

    Uploaded by

    Tanafe
    5K views35 pages
    The document discusses CPU registers and instruction pipelines. It covers: 1) CPU registers include general purpose registers for temporary storage, control/status registers like the program counter, and other specialized registers. The number of general purpose registers is typically between 8-32. 2) Instruction pipelines break down instruction execution into stages to overlap processing of multiple instructions. A basic pipeline may have fetch, decode, execute, and writeback stages. More complex pipelines can have 6 stages. 3) Pipelining improves performance but requires techniques like branch prediction to handle conditional jumps which can disrupt the pipeline flow. Common techniques include predicting branches as not taken, prefetching branch targets, and maintaining a loop buffer.

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    Flowchart

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    The document discusses CPU registers and instruction pipelines. It covers: 1) CPU registers include general purpose registers for temporary storage, control/status registers like the program counter, and other specialized registers. The number of general purpose registers is typically between 8-32. 2) Instruction pipelines break down instruction execution into stages to overlap processing of multiple instructions. A basic pipeline may have fetch, decode, execute, and writeback stages. More complex pipelines can have 6 stages. 3) Pipelining improves performance but requires techniques like branch prediction to handle conditional jumps which can disrupt the pipeline flow. Common techniques include predicting branches as not taken, prefetching branch targets, and maintaining a loop buffer.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    5K views35 pages

    CPU With Systems Bus

    Uploaded by

    Tanafe
    The document discusses CPU registers and instruction pipelines. It covers: 1) CPU registers include general purpose registers for temporary storage, control/status registers like the program counter, and other specialized registers. The number of general purpose registers is typically between 8-32. 2) Instruction pipelines break down instruction execution into stages to overlap processing of multiple instructions. A basic pipeline may have fetch, decode, execute, and writeback stages. More complex pipelines can have 6 stages. 3) Pipelining improves performance but requires techniques like branch prediction to handle conditional jumps which can disrupt the pipeline flow. Common techniques include predicting branches as not taken, prefetching branch targets, and maintaining a loop buffer.

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    Download as PPT, PDF, TXT or read online from Scribd
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    At a glance
    Powered by AI
    The key takeaways are that the CPU uses registers for temporary storage and processing, and that instructions and data are fetched from memory through a multi-stage process.

    Registers are the CPU's temporary storage and working space. They come in different types like general purpose, program counter, status and control registers. They allow the CPU to process data and instructions efficiently.

    The CPU uses the program counter to fetch instruction addresses from memory. It then decodes and loads the instructions. For data, it uses address registers to fetch operands. Indirect addressing allows fetching data addresses from instructions stored in memory.

    CPU With Systems Bus

    CPU Internal Structure


    Registers
    • CPU must have some working space
    (temporary storage)
    • Called registers
    • Number and function vary between
    processor designs
    • One of the major design decisions
    • Top level of memory hierarchy
    How Many GP Registers?
    • Between 8 - 32
    • Fewer = more memory references
    • More does not reduce memory references
    and takes up processor real estate
    • See also RISC
    Control & Status Registers
    • Program Counter
    • Instruction Decoding Register
    • Memory Address Register
    • Memory Buffer Register

    • Revision: what do these all do?


    Program Status Word
    • A set of bits
    • Includes Condition Codes
    • Sign of last result
    • Zero
    • Carry
    • Equal
    • Overflow
    • Interrupt enable/disable
    • Supervisor
    Other Registers
    • May have registers pointing to:
    —Process control blocks (see O/S)
    —Interrupt Vectors (see O/S)

    • N.B. CPU design and operating system


    design are closely linked
    Example Register Organizations
    Instruction Cycle with Indirect
    Instruction Cycle State Diagram
    Data Flow (Instruction Fetch)
    • Depends on CPU design
    • In general:

    • Fetch
    —PC contains address of next instruction
    —Address moved to MAR
    —Address placed on address bus
    —Control unit requests memory read
    —Result placed on data bus, copied to MBR,
    then to IR
    —Meanwhile PC incremented by 1
    Data Flow (Data Fetch)
    • IR is examined
    • If indirect addressing, indirect cycle is
    performed
    —Right most N bits of MBR transferred to MAR
    —Control unit requests memory read
    —Result (address of operand) moved to MBR
    Data Flow (Fetch Diagram)
    Data Flow (Indirect Diagram)
    Data Flow (Execute)
    • May take many forms
    • Depends on instruction being executed
    • May include
    —Memory read/write
    —Input/Output
    —Register transfers
    —ALU operations
    Data Flow (Interrupt)
    • Simple
    • Predictable
    • Current PC saved to allow resumption
    after interrupt
    • Contents of PC copied to MBR
    • Special memory location (e.g. stack
    pointer) loaded to MAR
    • MBR written to memory
    • PC loaded with address of interrupt
    handling routine
    • Next instruction (first of interrupt handler)
    can be fetched
    Data Flow (Interrupt Diagram)
    Prefetch
    • Fetch accessing main memory
    • Execution usually does not access main
    memory
    • Can fetch next instruction during
    execution of current instruction
    • Called instruction prefetch
    Pipelining
    • Fetch instruction
    • Decode instruction
    • Calculate operands (i.e. EAs)
    • Fetch operands
    • Execute instructions
    • Write result

    • Overlap these operations


    Two Stage Instruction Pipeline
    Six Stage
    Instruction Pipeline
    Alternative Pipeline Depiction
    Speedup Factors
    with Instruction
    Pipelining
    Dealing with Branches
    • Multiple Streams
    • Prefetch Branch Target
    • Loop buffer
    • Branch prediction
    • Delayed branching
    Prefetch Branch Target
    • Target of branch is prefetched in addition
    to instructions following branch
    • Keep target until branch is executed
    • Used by IBM 360/91
    Loop Buffer
    • Very fast memory
    • Maintained by fetch stage of pipeline
    • Check buffer before fetching from memory
    • Very good for small loops or jumps
    • c.f. cache
    • Used by CRAY-1
    Loop Buffer Diagram
    Branch Prediction (1)
    • Predict never taken
    —Assume that jump will not happen
    —Always fetch next instruction
    —68020 & VAX 11/780
    —VAX will not prefetch after branch if a page
    fault would result (O/S v CPU design)
    • Predict always taken
    —Assume that jump will happen
    —Always fetch target instruction
    Branch Prediction Flowchart
    Branch Prediction State Diagram
    Dealing With
    Branches
    Intel 80486 Pipelining
    • Fetch
    — From cache or external memory
    — Put in one of two 16-byte prefetch buffers
    — Fill buffer with new data as soon as old data consumed
    — Average 5 instructions fetched per load
    — Independent of other stages to keep buffers full
    • Decode stage 1
    — Opcode & address-mode info
    — At most first 3 bytes of instruction
    — Can direct D2 stage to get rest of instruction
    • Decode stage 2
    — Expand opcode into control signals
    — Computation of complex address modes
    • Execute
    — ALU operations, cache access, register update
    • Writeback
    — Update registers & flags
    — Results sent to cache & bus interface write buffers
    80486 Instruction Pipeline Examples
    Pentium 4 Registers
    Control Registers

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