FPGA IMPLEMENTATION OF DIRECT SEQUENCE SPREAD SPECTRUM

AIM
The main aim of this project is to design Spread spectrum that enables a signal to be transmitted across a frequency band that is much wider than the minimum bandwidth required by the information signal. In this project we design and develop a transmitter and receiver for spread spectrum transmission. A transmitter generates a spread spectrum signal using a specified algorithm, which can be either random or preplanned. The transmitter operates in synchronization with a receiver, which has the same coding as the transmitter. A short burst of narrowband data is transmitted on a broad band. Then, the transmitter tunes to another frequency and transmits again. The transmitter comprises of The Shifter Unit that gets the 8 bit data, which is to be transmitted, separates that into Odd and Even samples and segregates it as four Di bits. The Di bits are now to be given to the respective Wave generator units. The Multiplexer unit serves as the output unit of the Modulator Section. It gives the eight bit samples as its output. This Units selection line continuously gets the input from the shifter unit (DI-bits) and the selection line selects the corresponding wave generator unit to the DAC to see the change of Phase shift. The demodulator consists of the Multiplier, Adder and comparator block the first sample in each signal message is first multiplied to the first reference signal and then added which in turn is given to comparator to find which message is in phase with reference signal.

The VHDL coding has been written with ModelSim software and the synthesis is done using Xilinx Project Navigator in the FPGA using the SPARTAN 3E Board.

CHAPTER 2 INTRODUCTION TO DIRECT SEQUENCE-SPREAD SPECTRUM USING QPSK SPREAD SPECTRUM

SPREAD SPECTRUM is the transmission in which the data of interest occupies a bandwidth in excess than necessary to send the data. The two types of spread spectrum are.

Direct Sequence Spread Spectrum Frequency Hopping Spread Spectrum

Secure communication is indispensable for many applications especially in defense so that intruders cant use it illegally. For the purpose, the message to be transmitted is digitized and mixed with a pseudo-Random sequence, which is many times the rate of the information signal. Many modulation techniques have been adopted to achieve this objective of secure communication but these commonly adopted techniques suffer from high signal interference, low data transfer rate, large bandwidth consumption and less privacy. Feasible solution to eliminate these drawbacks is to use Direct sequence-Spread spectrum Quadrature Phase Shift Keying method of modulation. In this method involves two modulation, first the data is been modulated by mixing it with the random sequence then it is modulated using a phase shift keying method. In frequency hopping us first modulate the data using a modulation technique and then it is transmitted by randomly hoping frequency. In both the cases the random sequence is called pseudo-noise or pseudorandom sequence. FREQUENCY AND BANDWIDTH USED Bandwidth is the maximum possible range of frequencies that can be used for transmission. It is usually the frequency range between the upper cut off frequencies and lower cut off frequencies

Frequency used in Direct Sequence Spread Spectrum: The frequency bandwidth used in the Direct sequence spread spectrum is similar to that of the frequency used in CDMA. Here the data rate is high as in HDR capable CDMA and the data rate is of 1.25 MHz 4.9xN Mbit/s and uplink (reverse link) data rates up to 1.8xN Mbit/s where N is the frequency used which ranges between 1.15 MHz to 1.35 MHz. Since its the general character of the spread spectrum to consume more bandwidth than that is actually required the bandwidth range is from 1700-1900.

Direct sequence-Spread spectrum:

In Direct sequence-Spread spectrum the data signal is taken and it is modulated with a pseudonoise sequence. The spread spectrum technique reduces interference because an interfering signal from a narrowband system will only affect the spread spectrum signal if both are transmitting at the same frequency at the same time. Thus, the aggregate interference will be very low, resulting in little or no bit errors. A Direct sequence-Spread spectrum code determines the frequencies that the radio will transmit and the order. To properly receive the signal, the receiver must be set to the same code and listen to the incoming signal at the right time and correct frequency. FCC regulations require manufacturers to use 75 or more pseudo sequence for transmission channel with a maximum Dwell time (the time spent at a particular frequency during any single hop) of 400 ms. If the radio encounters interference on one frequency, then the radio will retransmit the signal on a subsequent hop on another frequency. Because of the nature of its modulation technique, frequency hopping can achieve data rates of up to 2 Mbps

Direct sequence-Spread spectrum Using QPSK Modem:

The modulation and demodulation of the Direct sequence-Spread spectrum system is done using QPSK. In the QPSK Modulator module, the input binary bit streams are split into in-phase and Quadrature-phase data bits. These bits are then converted to bipolar form, which helps in, effectively imparting a 0 or 180 -phase shifts to the orthogonal carriers. The resultant signals are combined and transmitted as output signal. The Demodulator unit that accepts the modulator output as input has a reference signal by which the original message is got back.

ADVANTAGES OF DIRECT SEQUENCE SPREAD SPECTRUM

Lower cost Highly secure data transmission Jamming free Most tolerant to signal interference Lowest power consumption Lowest potential data rates from individual physical layers Highest aggregate capacity using multiple physical layers Faster rate of data transfer

CHAPTER 3 DESIGN OF DIRECT SEQUENCE SPREAD SPECTRUM TRANSMITTER

DIRECT SEQUENCE SPREAD SPECTRUM TRANSMITTER The direct sequence spread spectrum transmitter has a global clock and reset. The input given is of 15-bits which is then encrypted using the pseudo noise sequence of 15-bits.So the encrypted data is of 32-bits.The encrypted data is then transmitted using the QPSK modem. The transmitted data is of 8-bits length

Fig 5 Schematic diagram of Direct sequence-Spread spectrum QPSK

QPSK MODEM
In this method, the Modulated Wave shifts between four phases each 90 apart for the Di bits 00, 01 10 or 11 creating sine ,cosine ,inverse-sine and inverse-cosine respectively .It comprises of a modulator and a demodulator .

Connectors:

Block diagram direct sequence-Spread spectrum QPSK Transmitter BLOCKS OF DIRECT SEQUENCE SPREAD SPECTRUM TRANSMITTER Encryption Unit QPSK Modulator

Splitter Unit Address generation unit for shifter unit Control unit Multiplier unit Digital To Analog Interfacing Unit QPSK Demodulator

CHAPTER 4 DESIGN OF DIRECT SEQUENCE SPREAD SPECTRUM RECEIVER

DIRECT SEQUENCE SPREAD SPECTRUM RECEIVER The receiver receives the transmitted signal which is of 8-bits is then converted to digital signal for further processing send then is then encrypted with pseudo-noise sequence to get the transmitted data

Blocks Involved
Modulated output is received at the receiver end, where demodulation of the signal occurs. The blocks involved at the Demodulator section are ADC Interfacing block Multiplier block Comparator block Counter block X-OR block

CLK RST ANALOG TO DIGITAL

OUT MULTIPLIER O1 O2 O3 O4

COMPARATOR

CIN CLK RST COUNTER

cout (31:0) DATAOUT Status XOR

CHAPTER-5 INTRODUCTION TO VHDL

4.1 INTRODUCTION VHDL is language for describing digital electronic systems. It arose out of the United States governments very high speed integrated circuits (VHSIC) program, in the course of this program. It became clear that there was a need for a standard language for describing the structure and function of integrated circuits(ICs). Hence the VHSIC hardware description language (VHDL) was developed. It was subsequently developed further under the auspices of the Institute of Electrical and Electronics Engineers (IEEE) and adopted in the form of the IEEE standard 1076. Like all IEEE standards, the VHDL standard is subject to review every five years. The 1987 standard was analyzed by the IEEE working group responsible for VHDL, and in 1992 a revised version of the standard was proposed. VHDL is designed to fill a number of needs in the design process. First, it allows description of the structure of a system which includes decomposition into subsystems and interconnects of those subsystems. Second it allows the specification of the function of a system to be stimulated before being manufactured, so that designers can quickly compare alternatives test for correctness without the delay and expense if hardware prototyping. Third it allows the detailed structure of a design to be synthesized from a more abstract specification, allowing designers to concentrate on more strategic design and reducing time to market. Modeling for simulation and synthesis is a vital part of a range of levels of abstraction, from gate levels up to algorithmic and architectural levels. It will continue to play an important role in the design future silicon-based systems.

Very high speed integrated circuit hardware description language (VHDL) can be used to model digital systems and introduce some of the basic concepts underlying the language. Hence with a description of the basic lexical and syntactic elements of the language, to form a basis for the detailed descriptions of language. Features of VHDL Strongly typed language. Case insensitive. Supports flexible design methodologies Top-Down and Bottom-Up design methods

4.2 MODELLING STYLES 4.2.1 TYPES OF MODELLING Data flow Modelling Behavioral Modelling Structural Modelling

4.2.2 OVERVIEW OF MODELLING STYLES In a behavioral model, a component is described by its input and output response. A Data flow model describes the circuit in terms of its function and flow of data through the circuit. Structural model describes a circuit in terms of interconnection of component

4.3 DATA FLOW MODELLING 4.3.1 DATA FLOW MODEL A dataflow model specifies the functionality of the entity without explicitly specifying its structure. This functionality shows the Flow of information through the entity, which is expressed primarily using concurrent signal assignment statements. 4.3.2 CONCURRENT SIGNAL ASSIGNMENT STATEMENT One of the primary mechanisms for modeling the dataflow behavior of an entity is using the concurrent signal assignment statement. 4.3.2.1 TYPES OF CONCURRENT SIGNAL ASSIGNMENT The two types of signal assignment statements are Conditional signal assignment statement Selected signal assignment statement.

Conditional Signal Assignment statement Conditional signal assignment statement selects different values for the target

Whenever an event occurs on a signal used in either any of the waveform expression or any of the conditions , the conditional signal assignment statement is executed by evaluating the conditions one at a time. Selected Signal Assignment statement The selected signal assignment statement selects different values for a target signal based on the value of a select expression (it is like a case statement).

Whenever an event occurs on a signal in the select expression or on any signal used in any of the waveform expressions, the statement is executed. So based on the value of the select expression that matches the choice value specified, the value of the corresponding waveform are scheduled to be assigned to the target signal. Choices are not evaluated in sequence. All possible values must be covered and those values not covered may be covered by others choice. Syntax With expression select Target-signal <= [waveform-elements when choices, [Waveform-elements when choices, .. Waveform-elements when choices; 4.4 STRUCTURAL MODELLING In a structural model, an entity is modeled as a set of components connected by signals, that is, as a net list. The component instantiation statement is the primary mechanism used for describing such a model of an entity. Structural model describes the circuit as interconnection of components.

4.4.1

COMPONENT DECLARATION

A component instantiated in a structural description must first be declared using a component declaration. A component declaration declares the name and the interface of a component. 4.4.2 COMPONENT INSTANTIATION A component instantiation statement defines a subcomponent of the entity in which it appears. It associates the signals in the entity with the ports of that subcomponents 4.5 BEHAVIOURAL MODELLING In behavioural modeling the statements are executed in sequential flow. In this modeling style the behavior of the entity is expressed using sequentially executed, procedural code which is similar in syntax to that of a highly programming language like C. The process statement is the primary mechanism used to model the behavior of an entity 0. 4.5.1 DEFINITION AND USAGE OF A PROCESS In architecture for an entity all statements are concurrent. We go for Process statement in order to run the code sequentially. Process statement is itself a concurrent statement. A Process statement has a declaration section and a statement part. In the declaration section, type, variables, constants, subprograms, and so on can be declared. The statement part contains only sequential statements. Sequential statements consist of CASE statements IF-THEN-ELSE statements, LOOP statements and so on. Architecture can contain as many number of processes, but the statements inside the process will be executed in sequential manner and and all processes will be executed in a concurrent manner. Sensitivity List The process statement can have an explicit sensitivity list. This list defines the signals that cause the statements inside the process statement to execute whenever one or more elements of the list change value. The sensitivity list is a list of the signals that cause the process to execute. The

process has to have an explicit sensitivity list or it can have a WAIT statement.

Syntax for PROCESS statement Process (sensitivity list) is --Variable declarations Begin --statements to be executed sequentially End process;

4.5.2 SEQUENTIAL STATEMENTS IN VHDL IF-THEN CASE LOOP statements EXIT

4.5.2.1 IF-THEN STATEMENT An IF statement selects a sequence of statement for execution based on the value of a condition. The condition can be an expression that evaluates to a Boolean value. The IF statement is executed by checking each condition sequentially until the first true condition is found; then, a set of sequential statements associated with this condition is executed. The IF statement can have zero or more ELSIF clauses and an optional ELSE clause. Syntax for IF-THEN statement IF (Boolean expression) THEN --sequential statement ELSIF (Boolean expression) THEN

--sequential st atements ELSE 4.5.2.2 CASE STATEMENT The case statement is used whenever a single expression value can be used to select between a numbers of actions. Syntax for CASE statement CASE expression is WHEN choices WHEN choices WHEN choices WHEN choices

=> Sequential statements; => Sequential statements; => Sequential statements; => Sequential statements; => Sequential statements; WHEN OTHERS => Sequential statements; END CASE;

--Branch 1 --Branch 2 --.. --.. --Branch N-1

--Last Branch

The CASE statement selects one of the branches for execution based on the value of the expression. The expression value must be of the discrete type or of a one dimensional array. Choices may be expressed as single values, as range of values, by using vertical bar (|), or by using the others clause. All possible values of the expression must be covered in the case statement exactly once. The others clause can be used as a choice to cover the catch-all values.

4.5.2.3 LOOP STATEMENTS Loop statement is used whenever an operation needs to be repeated. LOOP statements are used when powerful iteration capability is needed to implement a model.

Syntax for LOOP statement Loop_lable: iteration scheme LOOP ---sequence of statements END LOOP Loop_lable There are three types of iteration schemes, FOR LOOP FOR loop is a kind of basic LOOP statement, which includes a specification of how many times the body of the loop is to be executed. Syntax for FOR loop loop_lable: FOR identifier IN discrete range LOOP --sequential statements END LOOP loop_lable; FOR WHILE LOOP

WHILE LOOP WHILE loop is one type of LOOP statement which test a condition before each iteration. If the condition is true iteration proceeds. If it is false loop is terminated. Syntax for WHILE loop Loop_lable: WHILE Boolean expression LOOP

---sequential statements END LOOP loop_lable;

4.5.2.4 Loop and Exit Statements This form of loop is one where no iteration scheme is specified. In this form of loop, all statements in the loop body are repeatedly executed until some other action causes the loop to exit. This action can be caused by EXIT statement NEXT statement or a RETURN statement. EXIT statement is a sequential statement that can be used only inside a loop. It causes execution to jump out of the inner most loops or the loop whose label is specified. If no loop label is specified the inner most loop is exited. If the when clause is used, the specific loop is excited only if the condition is true. NEXT statement is also a sequential statement that can be used only inside a loop. The next statement result in skipping the remaining statements in the current iteration of the specified loop; execution resumes with the first statement in the next iteration of this loop, if one exists. ` In comparison with the EXIT statement which causes the loop to be terminated the NEXT statement causes the current loop iteration of the specified.

CHAPTER - 6
HARDWARE AND SOFTWARE

Very-Large-Scale Integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors based circuits into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed.

The first semiconductor chips held one transistor each. Subsequent advances added more and more transistors and as a consequence more individual functions of systems were integrated over time. The microprocessor is a VLSI device. The first generation of computers relied on vacuum tubes. Then came discrete semiconductor devices, followed by integrated circuits. The first SmallScale Integration (SSI) Ics had small numbers of devices on a single chip-diodes, transistors, resistors and capacitors (no inductors though), making it possible to fabricate one or more logic gates on a single device. The fourth generation consisted of Large-scale Integration (LSI),

i.e. systems with at least a thousand logic gates. The natural successor to LSI was VLSI (many tens of thousands of gates on a single ship). Current technology has moved far past this mark and todays microprocessors have many millions of gates and hundreds of millions of individual transistors.

As of mid-2006, billion transistor processors are just on the horizon, with the first being Intels Montecito Itanium Server. This is expected to become more common place as semiconductor fabrication moves from the current generation of 90 nanometer (90nm) processes to the next 65nm and 45nm generations

At one time, there was effort to name and calibrate various levels of large scale integration above VLSI. Terms like Ultra-large scale Integration (ULSI) were used. But the huge number of gates and transistors available on common devices has rendered such fine distinctions moot. Terms suggesting more than VLSI levels of integration are no larger in widespread use. Even VLSI is now somewhat quaint, given the common assumption that all microprocessors are VLSI or better.

FPGA

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturinghence "fieldprogrammable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the

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configuration, as they were for ASICs, but this is increasingly rare). FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the functionality after shipping, partial re-configuration of the portion of the design and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.

FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together"somewhat like a one-chip programmable breadboard. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.

The area of field programmable gate array (FPGA) design is evolving at a rapid pace. The increase in the complexity of the FPGA's architecture means that it can now be used in far more applications than before. The newer FPGAs are steering away from the plain vanilla type "logic only" architecture to one with embedded dedicated blocks for specialized applications. With so many choices available, the designer not only has to familiarize himself with the various architectures and their strengths, but he also needs a way to quickly estimate the performance of his design when targeted to the different technologies. This paper briefly outlines the latest

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offerings from the key FPGA vendors and in its latter half discusses the importance of using the right synthesis tool in order to target the same design to these various technologies. Definitions of Relevant Terminology are Field-programmable Device (FPD) a general term that refers to any type of integrated circuit used for implementing digital hardware, where the chip can be configured by the end user to realize different designs. Programming of such a device often involves placing the chip into a special programming unit, but some chips can also be configured in-system. Another name for FPDs is programmable logic devices (PLDs); although PLDs encompass the same types of chips as FPDs, we prefer the term FPD because historically the word PLD has referred to relatively simple types of devices. PLA a Programmable Logic Array (PLA) is a relatively small FPD that contains two levels of logic, an AND-plane and an OR-plane, where both levels are programmable (note: although PLA structures are sometimes embedded into full-custom chips, we refer here only to those PLAs that are provided as separate integrated circuits and are user-programmable).

PAL a Programmable Array Logic (PAL) is a relatively small FPD that has a programmable AND-plane followed by a fixed OR-plane. SPLD refers to any type of Simple PLD, usually either a PLA or PAL. CPLD a more Complex PLD that consists of an arrangement of multiple SPLD-like blocks on a single chip.

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Alternative names (that will not be used in this paper) sometimes adopted for this style of chip are Enhanced PLD (EPLD), Super PAL, Mega PAL, and others. FPGA a Field-Programmable Gate Array is an FPD featuring a general structure that allows very high logic capacity. Whereas CPLDs feature logic resources with a wide number of inputs (AND planes), FPGAs offer more narrow logic resources. FPGAs also offer a higher ratio of flip-flops to logic resources than do CPLDs.

FPGA Landscape

In the semiconductor industry, the programmable logic segment is the best indicator of the progress of technology. No other segment has such varied offerings as field programmable gate arrays. It is no wonder that FPGAs were among the first semiconductor products to move to the 0.13 m technology, and again recently to 90nm technology. This rapidly changing technology means that more complex functionality is being designed into a FPGA.

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Fig. 5.1 Structure of An FPGA The players in the current programmable logic market are Altera, Atmel, Actel, Cypress, Lattice, Quicklogic and Xilinx. Some of the larger and more popular device families are: Stratix from Altera; Accelerator from Actel; ispXPGA from Lattice and Virtex from Xilinx. Between these FPGA devices, many major electronics applications such as communications, video, image and digital signal processing, storage area networks and aerospace are covered. While the architecture of each FPGA is unique, the basic combination of the functional block remains the same: LUTs + registers + carry-chain + wide MUX. It is important to be aware of the required resources for a design and to cross-reference this with what is available. Sometimes, however, it is also the supported configuration that is important for a 35 35

design's requirement. For example, the capability of a dedicated RAM to function in a particular mode might not be supported by all vendors.

FPGA synthesis: the vendor-independent approach

The present-day FPGAs offer the necessary features for successfully completing most complex designs. Table 1 highlights the amount of key resources available in the largest device offered by each FPGA vendor. Clock management forms a very important part of any digital design and this functionality is facilitated by on-chip phase locked loop (PLLs or DLLs) circuitry. Dedicated memory blocks offer data storage and can be configured as basic single-port RAMs, ROMs (read only memory), FIFOs (first in first out), or CAMs (content addressable memory). Data processing or the logic fabric of these FPGAs varies widely in size with the biggest Xilinx Virtex-II Pro offering up to 100K LUT4s. The ability to interface the FPGA with backplanes, high-speed buses, and memories is possible by the availability of various single-ended and differential I/O standards support.

Many of the major electronics applications such as communications, video, image and digital signal processing; storage area networks and aerospace are covered between the above-mentioned FPGA devices. Although all of these FPGAs can perform the key functions required by these applications, each of them is individually better suited for certain target segments. For example, although Virtex-II and the Stratix both offer dedicated multiplier blocks, the existence of the adders in the dedicated DSP block may enable the Stratix device to target DSP applications 36 36

more effectively due to its ability to create efficient MAC (multiply-accumulate) blocks4.

In a similar manner, for programmable systems applications requiring embedded processors, the Virtex-II Pro with its 32-bit RISC processor (PowerPC 405) would be an ideal choice.

Table 5.1 Features Offered In FPGA Xilinx virtex II Altera Features Clock management Embedded memory blocks Pro DCM Up to 12 Block RAM Up to 10 Mbit stratix PLL Up to 12 Tri Matrix Memory Actel Axcelerator PLL Up to 8 Embedded RAM Lattice Pxpga Sys CLOCK PLL up to 8 Sys MEM Blocks Up to 414K is

Up to10 Mbit Up to 338K

Data processing

CLB and 18-bitx 18-bit Multipliers

LEs

and Logic modules PFU based (C-cell cell) Sys IO &R-

embedded multipliers

Programmable Select IO I/O s Special features Embedded power PC405 Cores

Advanced IO Advanced Support DSP blocks IO Support Per pin

Sys Hs 1 for speed

FIFOs for bus high Application 37 37

serial interface

MODELSIM
MODELSIM SE 6.2c This section describes the basic procedure for simulating ModelSim. BASIC STEPS FOR SIMULATION Step 1 Collect Files and Map Libraries Files needed to run ModelSim on your design: design files (VHDL and/or Verilog ), including stimulus for the design libraries, both working and resource modelsim.ini file (automatically created by the library mapping command)

Providing Stimulus to the Design You can provide stimulus to your design in several ways: Language-based test bench Tcl-based ModelSim interactive command, force VCD files / commands See Creating a VCD File and Using Extended VCD as Stimulus Third-party test bench generation tools.

Work and Resource Libraries You can use design libraries in two ways: As a local working library that contains the compiled version of your design As a resource library

Mapping the Logical Work to the Physical Work Directory VHDL uses logical library names that can be mapped to ModelSim library directories. If libraries are not mapped properly, and you invoke your simulation, necessary components will not be loaded and

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simulation will fail. Similarly, compilation can also depend on proper library mapping. By default, ModelSim can find libraries in your current directory (assuming they have the right name), but for it to find libraries located elsewhere, you need to map a logical library name to the pathname of the library. You can use the GUI (Library Mappings with the GUI, a command (Library Mapping from the Command Line), or a project (Getting Started with Projects to assign a logical name to a design library.

Step 2 Compile the Design To compile a design, run one of the following ModelSim commands, depending on the language used to create the design:

Compiling Verilog (VLOG) The vlog command compiles Verilog modules in your design. You can compile Verilog files in any order, since they are not order dependent. See Verilog Compilation for details. Compiling VHDL (VCOM) The vcom command compiles VHDL design units. You must compile VHDL files in the order necessitate to any design requirements. Projects may assist you in determining the compile order.

Step 3 Load the Design for Simulation Running the Vsim Command on the Top Level of the Design After you have compiled your design, it is ready for simulation. You can then run the vsim command using the names of any top-level modules (many designs contain only one top-level module).

Using Standard Delay Format Files You can incorporate actual delay values to the simulation by applying standard delay format (SDF) back-annotation files to the design. For more information on how SDF is used in the design, see Specifying SDF Files for Simulation.

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Step 4 Simulate the Design Once you have successfully loaded the design, simulation time is set to zero, and you must enter a run command to begin simulation. For more information, see Verilog and SystemVerilog Simulation, and VHDL Simulation.

Step 5 Debug the Design The ModelSim GUI provides numerous commands, operations, and windows useful in debugging your design. In addition, you can also use the command line to run the following basic simulation commands for debugging: describe drivers examine force log

show

This are the steps were used in the ModelSim.

6.2 XILINX ISE 9.1 i

Xilinx is disclosing this document and intellectual property (hereinafter the design) to you for use in the development of designs to operate on, or interface with xilinx FPGAs. except as stated herein, none of the design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of xilinx. Any unauthorized use of the design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the design; nor does xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the design. Xilinx reserves the

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right to make changes, at any time, to the design as deemed desirable in the sole discretion of xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the design. The design is provided as is with all faults and the entire risk as to its function and implementation is with you. You acknowledge and agree that you have not relied on any oral or written information or advice, whether given by xilinx, or its agents or employees. Xilinx makes no other warranties, whether express, implied, or statutory, regarding the design, including any warranties of merchantability, fitness for a particular purpose, title, and non infringement of third-party rights. In no event will xilinx be liable for any consequential, indirect, exemplary, special, or incidental damages, including any lost data and lost profits, arising from or relating to your use of the design, even if you have been advised of the possibility of such damages. The total cumulative liability of xilinx in connection with your use of the design, whether in contract or tort or otherwise, will in no event exceed the amount of fees paid by you to xilinx hereunder for use of the design. You acknowledge that the fees, if any, reflect the allocation of risk set forth in this agreement and that xilinx would not make available the design to you without these limitations of liability. The design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring failsafe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (high-risk applications).

IMPLEMENTING THE DESIGN Select the counter source file in the Sources window. Open the Design Summary by double-clicking the View Design Summary process in the Processes tab. Double-click the Implement Design process in the Processes tab. Notice that after Implementation is complete, the Implementation processes have agreen check mark next to them indicating that they completed successfully without Errors or Warnings. Locate the Performance Summary table near the bottom of the Design Summary. Click the All Constraints Met link in the Timing Constraints field to view the Timing Constraints report. Verify that the design meets the specified timing requirements. Close the Design Summary.

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