HT24LC02

CMOS 2K 2-Wire Serial EEPROM

Features
· Operating voltage: 2.2V~5.5V · Partial page write allowed
· Low power consumption · 8-byte Page write modes
- Operation: 5mA max. · Write operation with built-in timer
- Standby: 5mA max. · Hardware controlled write protection
· Internal organization: 256´8 · 40-year data retention
· 2-wire serial interface · 106 erase/write cycles per word
· Write cycle time: 5ms max. · Commerical temperature range (0°C to +70°C)
· Automatic erase-before-write operation · 8-pin DIP/SOP/TSSOP package

General Description
The HT24LC02 is a 2K-bit serial read/write non-volatile low power and low voltage operation are essential. Up
memory device using the CMOS floating gate process. to eight HT24LC02 devices may be connected to the
Its 2048 bits of memory are organized into 256 words same 2-wire bus. The HT24LC02 is guaranteed for 1M
and each word is 8 bits. The device is optimized for use erase/write cycles and 40-year data retention.
in many industrial and commercial applications where

Block Diagram Pin Assignment

A 0 1 8 V C C
S C L I/O H V P u m p A 1 2 7 W P
C o n tro l
S D A A 2 3 6 S C L
L o g ic
V S S 4 5 S D A
X
D E E P R O M H T 2 4 L C 0 2
M e m o ry E A rra y 8 D IP -A /S O P -A /T S S O P -A
W P C o n tro l C
L o g ic
P a g e B u f
Y D E C

A d d re s s
A 0 ~ A 2 S e n s e A M P
C o u n te r
R /W C o n tro l
V C C
V S S

Pin Description
Pin Name I/O Description
A0~A2 I Address inputs
SDA I/O Serial data inputs/output
SCL I Serial clock data input
WP I Write protect
VSS ¾ Negative power supply, ground

VCC ¾ Positive power supply

Rev. 1.10 1 November 5, 2002

 HT24LC02

Absolute Maximum Ratings

Operating Temperature (Commercial)..........................................................................................................0°C to 70°C
Storage Temperature.............................................................................................................................-50°C to 125 °C
Applied VCC Voltage with Respect to VSS ................................................................................................-0.3V to 6.0V
Applied Voltage on any Pin with Respect to VSS ..............................................................................-0.3V to VCC+0.3V

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.

D.C. Characteristics Ta=0°C to 70°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VCC Conditions
VCC Operating Voltage ¾ ¾ 2.2 ¾ 5.5 V
ICC1 Operating Current 5V Read at 100kHz ¾ ¾ 2 mA
ICC2 Operating Current 5V Write at 100kHz ¾ ¾ 5 mA
VIL Input Low Voltage ¾ ¾ -1 ¾ 0.3VCC V
VIH Input High Voltage ¾ ¾ 0.7VCC ¾ VCC+0.5 V
VOL Output Low Voltage 2.4V IOL=2.1mA ¾ ¾ 0.4 V
ILI Input Leakage Current 5V VIN=0 or VCC ¾ ¾ 1 mA
ILO Output Leakage Current 5V VOUT=0 or VCC ¾ ¾ 1 mA
ISTB1 Standby Current 5V VIN=0 or VCC ¾ ¾ 5 mA
ISTB2 Standby Current 2.4V VIN=0 or VCC ¾ ¾ 4 mA
CIN Input Capacitance (See Note) ¾ f=1MHz 25°C ¾ ¾ 6 pF
COUT Output Capacitance (See Note) ¾ f=1MHz 25°C ¾ ¾ 8 pF

Note: These parameters are periodically sampled but not 100% tested

Rev. 1.10 2 November 5, 2002

 HT24LC02

A.C. Characteristics Ta=0°C to 70°C

Standard Mode* VCC=5V±10%

Symbol Parameter Remark Unit
Min. Max. Min. Max.
fSK Clock Frequency ¾ ¾ 100 ¾ 400 kHz
tHIGH Clock High Time ¾ 4000 ¾ 600 ¾ ns
tLOW Clock Low Time ¾ 4700 ¾ 1200 ¾ ns
tr SDA and SCL Rise Time Note ¾ 1000 ¾ 300 ns
tf SDA and SCL Fall Time Note ¾ 300 ¾ 300 ns
After this period the
tHD:STA START Condition Hold Time first clock pulse is 4000 ¾ 600 ¾ ns
generated
Only relevant for
tSU:STA START Condition Setup Time repeated START 4000 ¾ 600 ¾ ns
condition
tHD:DAT Data Input Hold Time ¾ 0 ¾ 0 ¾ ns
tSU:DAT Data Input Setup Time ¾ 200 ¾ 100 ¾ ns
tSU:STO STOP Condition Setup Time ¾ 4000 ¾ 600 ¾ ns
tAA Output Valid from Clock ¾ ¾ 3500 ¾ 900 ns
Time in which the bus
must be free before a
tBUF Bus Free Time 4700 ¾ 1200 ¾ ns
new transmission can
start
Input Filter Time Constant Noise suppression
tSP ¾ 100 ¾ 50 ns
(SDA and SCL Pins) time
tWR Write Cycle Time ¾ ¾ 5 ¾ 5 ms

Note: These parameters are periodically sampled but not 100% tested
* The standard mode means VCC=2.2V to 5.5V
For relative timing, refer to timing diagrams

Rev. 1.10 3 November 5, 2002

 HT24LC02

Functional Description

· Serial clock (SCL) · Acknowledge

The SCL input is used for positive edge clock data into All addresses and data words are serially transmitted
each EEPROM device and negative edge clock data to and from the EEPROM in 8-bit words. The
out of each device. EEPROM sends a zero to acknowledge that it has re-
ceived each word. This happens during the ninth clock
· Serial data (SDA)
cycle.
The SDA pin is bidirectional for serial data transfer.
The pin is open-drain driven and may be wired-OR
D a ta a llo w e d
with any number of other open-drain or open collector to c h a n g e
devices. S D A
· A0, A1, A2
The A2, A1 and A0 pins are device address inputs that S C L
are hard wired for the HT24LC02. As many as eight S ta rt A d d re s s o r S to p
2K devices may be addressed on a single bus system c o n d itio n a c k n o w le d g e c o n d itio n
v a lid
(the device addressing is discussed in detail under the
Device Addressing section).
Device addressing
· Write protect (WP)
The 2K EEPROM devices all require an 8-bit device ad-
The HT24LC02 has a write protect pin that provides
dress word following a start condition to enable the chip
hardware data protection. The write protect pin allows
for a read or write operation. The device address word
normal read/write operations when connected to the
consist of a mandatory one, zero sequence for the first
VSS. When the write protect pin is connected to Vcc,
four most significant bits (refer to the diagram showing
the write protection feature is enabled and operates
the Device Address). This is common to all the
as shown in the following table.
EEPROM device.
WP Pin
Protect Array The next three bits are the A2, A1 and A0 device ad-
Status
dress bits for the 2K EEPROM. These three bits must
At VCC Full Array (2K) compare to their corresponding hard-wired input pins.
At VSS Normal Read/Write Operations The 8th bit of device address is the read/write operation
select bit. A read operation is initiated if this bit is high
Memory organization and a write operation is initiated if this bit is low.
· HT24LC02, 2K Serial EEPROM If the comparison of the device address succeed the
Internally organized with 256 8-bit words, the 2K re- EEPROM will output a zero at ACK bit. If not, the chip will
quires an 8-bit data word address for random word ad- return to a standby state.
dressing.
1 0 1 0 A 2 A 1 A 0 R /W
Device operations
D e v ic e A d d r e s s
· Clock and data transition
Data transfer may be initiated only when the bus is not
Write operations
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in · Byte write
data line while the clock line is high will be interpreted A write operation requires an 8-bit data word address
as a START or STOP condition. following the device address word and acknowledg-
ment. Upon receipt of this address, the EEPROM will
· Start condition
again respond with a zero and then clock in the first
A high-to-low transition of SDA with SCL high is a start
8-bit data word. After receiving the 8-bit data word, the
condition which must precede any other command
EEPROM will output a zero and the addressing de-
(refer to Start and Stop Definition Timing diagram).
vice, such as a microcontroller, must terminate the
· Stop condition write sequence with a stop condition. At this time the
A low-to-high transition of SDA with SCL high is a stop EEPROM enters an internally-timed write cycle to the
condition. After a read sequence, the stop command non-volatile memory. All inputs are disabled during
will place the EEPROM in a standby power mode (re- this write cycle and EEPROM will not respond until the
fer to Start and Stop Definition Timing Diagram). write is completed (refer to Byte write timing).

Rev. 1.10 4 November 5, 2002

 HT24LC02

· Page write
S e n d W r ite C o m m a n d
The 2K EEPROM is capable of an 8-byte page write.
A page write is initiated the same as byte write, but the
S e n d S to p C o n d itio n
microcontroller does not send a stop condition after to In itia te W r ite C y c le
the first data word is clocked in. Instead, after the
EEPROM acknowledges the receipt of the first data
S e n d S ta rt
word, the microcontroller can transmit up to seven
more data words. The EEPROM will respond with a
z e ro a f t e r e a c h d a t a w or d r e c ei ve d . T h e S e n d C o tr o ll B y te
w ith R /W = 0
microcontroller must terminate the page write se-
quence with a stop condition.
The data word address lower three (2K) bits are inter-
(A C K = 0 )? N o
nally incremented following the receipt of each data
word. The higher data word address bits are not incre-
mented, retaining the memory page row location (re- Y e s
fer to Page write timing). N e x t O p e r a tio n

· Acknowledge polling
Acknowledge polling flow
Since the device will not acknowledge during a write
· Read operations
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus Read operations are initiated the same way as write
throughput). Once the stop condition for a write com- operations with the exception that the read/write se-
mand has been issued from the master, the device ini- lect bit in the device address word is set to one. There
tiates the internally timed write cycle. ACK polling can are three read operations: current address read, ran-
be initiated immediately. This involves the master dom address read and sequential read.
sending a start condition followed by the control byte · Current address read
for a write command (R/W=0). If the device is still busy The internal data word address counter maintains the
with the write cycle, then no ACK will be returned. If last address accessed during the last read or write op-
the cycle is completed, then the device will return the eration, incremented by one. This address stays valid
ACK and the master can then proceed with the next between operations as long as the chip power is main-
read or write command. tained. The address roll over during read from the last
byte of the last memory page to the first byte of the first
· Write protect
page. The address roll over during write from the last
The HT24LC02 can be used as a serial ROM when byte of the current page to the first byte of the same
the WP pin is connected to VCC. Programming will be page. Once the device address with the read/write se-
in h ib i t ed and t he ent i r e m em or y w i l l b e lect bit set to one is clocked in and acknowledged by
write-protected. the EEPROM, the current address data word is seri-
B y te w r ite tim in g

D e v ic e a d d r e s s W o rd a d d re s s D A T A

S D A S A 2 A 1 A 0 P
S ta rt R /W A C K A C K
A C K
S to p

P a g e w r ite tim in g

D e v ic e a d d r e s s W o rd a d d re s s D A T A n D A T A n + 1 D A T A n + x

S D A S P

S ta rt A C K A C K A C K A C K
S to p

C u r r e n t r e a d tim in g

D e v ic e a d d r e s s D A T A
S to p
S D A S A 2 A 1 A 0 P

S ta rt A C K N o A C K

Rev. 1.10 5 November 5, 2002

 HT24LC02

ally clocked out. The microcontroller does not respond · Sequential read
with an input zero but generates a following stop con- Sequential reads are initiated by either a current ad-
dition (refer to Current read timing). dress read or a random address read. After the
· Random read microcontroller receives a data word, it responds with an
A random read requires a dummy byte write sequence acknowledgment. As long as the EEPROM receives an
to load in the data word address which is then clocked acknowledgment, it will continue to increment the data
in and acknowledged by the EEPROM. The word address and serially clock out sequential data
microcontroller must then generate another start con- words. When the memory address limit is reached, the
dition. The microcontroller now initiates a current ad- data word address will roll over and the sequential read
dress read by sending a device address with the continues. The sequential read operation is terminated
read/write select bit high. The EEPROM acknowl- when the microcontroller does not respond with a zero
edges the device address and serially clocks out the but generates a following stop condition.
data word. The microcontroller does not respond with
a zero but does generates a following stop condition
(refer to Random read timing).

R a n d o m r e a d tim in g

D e v ic e a d d r e s s W o rd a d d re s s D e v ic e a d d r e s s D A T A
S to p
S D A S A 2 A 1 A 0 S P
A C K A C K A C K N o A C K
S ta rt S ta rt

S e q u e n tia l r e a d tim in g

D e v ic e a d d r e s s D A T A n D A T A n + 1 D A T A n + x

S D A S P
S ta rt A C K A C K A C K
S to p

Timing Diagrams

tf tr tH IG H

tL O W
S C L
tS U :S T A tH D :S T A tS U :D A T tS U :S T O
tH D :D A T

S D A tS P
tB U F
tA A
S D A
V a lid V a lid
O U T

S C L

S D A 8 th b it A C K
W o rd n tW R

S to p S ta rt
C o n d itio n C o n d itio n

Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start
condition of sequential command.

Rev. 1.10 6 November 5, 2002

 HT24LC02

Package Information
8-pin DIP (300mil) outline dimensions

8 5
B
1 4

D
= I
E G

Dimensions in mil
Symbol
Min. Nom. Max.
A 355 ¾ 375
B 240 ¾ 260
C 125 ¾ 135
D 125 ¾ 145
E 16 ¾ 20
F 50 ¾ 70
G ¾ 100 ¾
H 295 ¾ 315
I 335 ¾ 375
a 0° ¾ 15°

Rev. 1.10 7 November 5, 2002

 HT24LC02

8-pin SOP (150mil) outline dimensions

8 5
A B
1 4

C '
G
D H

E F =

Dimensions in mil
Symbol
Min. Nom. Max.
A 228 ¾ 244
B 149 ¾ 157
C 14 ¾ 20
C¢ 189 ¾ 197
D 53 ¾ 69
E ¾ 50 ¾
F 4 ¾ 10
G 22 ¾ 28
H 4 ¾ 12
a 0° ¾ 10°

Rev. 1.10 8 November 5, 2002

 HT24LC02

8-pin TSSOP outline dimensions

8 5

E 1

1 4

E
D
L
A A 2
C G
e B A 1 L 1
R 0 .1 0 y
(4 C O R N E R S )

Dimensions in mm
Symbol
Min. Nom. Max.
A 1.05 ¾ 1.20
A1 0.05 ¾ 0.15
A2 0.95 ¾ 1.05
B ¾ 0.25 ¾
C 0.11 ¾ 0.15
D 2.90 ¾ 3.10
E 6.20 ¾ 6.60
E1 4.30 ¾ 4.50
e ¾ 0.65 ¾
L 0.50 ¾ 0.70
L1 0.90 ¾ 1.10
y ¾ ¾ 0.10
q 0° ¾ 8°

Rev. 1.10 9 November 5, 2002

 HT24LC02

Product Tape and Reel Specifications

Reel dimensions

D
T 2

A B C

T 1

SOP 8N
Symbol Description Dimensions in mm
A Reel Outer Diameter 330±1.0
B Reel Inner Diameter 62±1.5
13.0+0.5
C Spindle Hole Diameter
-0.2
D Key Slit Width 2.0±0.15
12.8+0.3
T1 Space Between Flange
-0.2
T2 Reel Thickness 18.2±0.2

TSSOP 8L
Symbol Description Dimensions in mm
A Reel Outer Diameter 330±1.0
B Reel Inner Diameter 62±1.5
13.0+0.5
C Spindle Hole Diameter
-0.2
D Key Slit Width 2.0±0.5
12.8+0.3
T1 Space Between Flange
-0.2
T2 Reel Thickness 18.2±0.2

Rev. 1.10 10 November 5, 2002

 HT24LC02

Carrier tape dimensions

P 0 P 1
D t

F
W
B 0
C

D 1 P
K 0

A 0

SOP 8N
Symbol Description Dimensions in mm
12.0+0.3
W Carrier Tape Width
-0.1
P Cavity Pitch 8.0±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 5.5±0.1
D Perforation Diameter 1.55±0.1
D1 Cavity Hole Diameter 1.5+0.25
P0 Perforation Pitch 4.0±0.1
P1 Cavity to Perforation (Length Direction) 2.0±0.1
A0 Cavity Length 6.4±0.1
B0 Cavity Width 5.20±0.1
K0 Cavity Depth 2.1±0.1
t Carrier Tape Thickness 0.3±0.05
C Cover Tape Width 9.3

TSSOP 8L
Symbol Description Dimensions in mm
12.0+0.3
W Carrier Tape Width
-0.1
P Cavity Pitch 8.0±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 5.5±0.5
D Perforation Diameter 1.5+0.1
D1 Cavity Hole Diameter 1.5+0.1
P0 Perforation Pitch 4.0±0.1
P1 Cavity to Perforation (Length Direction) 2.0±0.1
A0 Cavity Length 7.0±0.1
B0 Cavity Width 3.6±0.1
K0 Cavity Depth 1.6±0.1
t Carrier Tape Thickness 0.3±0.013
C Cover Tape Width 9.3

Rev. 1.10 11 November 5, 2002

 HT24LC02

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Copyright Ó 2002 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most
up-to-date information, please visit our web site at http://www.holtek.com.tw.

Rev. 1.10 12 November 5, 2002