Tda 1564

INTEGRATED CIRCUITS
DATA SHEET
TDA1564 High efficiency 2 25 W/4 stereo car radio power amplifier

Preliminary specication Supersedes data of 2003 Sep 17 2004 Jan 27
Philips Semiconductors
Preliminary specication
High efciency 2 25 W/4 stereo car radio power amplier

FEATURES Low dissipation due to switching from Single-Ended (SE) to Bridge-Tied Load (BTL) mode Differential inputs with high Common Mode Rejection Ratio (CMRR) Mute/standby/operating (mode select pin) Load dump protection circuit Short-circuit safe to ground, to supply voltage and across load Loudspeaker protection circuit Offset detection for each channel Device switches to single-ended operation at excessive junction temperatures Thermal protection at high junction temperature (170C) Clip detection at THD = 2.5 % Diagnostic information (clip/protection/prewarning/offset). QUICK REFERENCE DATA SYMBOL VP PARAMETER supply voltage CONDITIONS DC biased non-operating load dump IORM Iq(tot) Istb Zi Po repetitive peak output current total quiescent current standby current input impedance output power RL = 4 ; EIAJ RL = 4 ; THD = 10 % RL = 4 ; THD = 2.5 % Gv CMRR SVRR VO cs Gv voltage gain common mode rejection ratio supply voltage ripple rejection DC output offset voltage channel separation channel unbalance Rs = 0 ; Po = 15 W Po = 1 W f = 1 kHz; Rs = 0 f = 1 kHz; Rs = 0 RL = MIN. 6.0 90 23 18 25 45 40 TYP. 14.4 95 1 120 38 25 20 26 80 65 70 GENERAL DESCRIPTION
TDA1564
The TDA1564 is a monolithic power amplifier in a 17-lead single-in-line (SIL) plastic power package. It contains two identical 25 W amplifiers. The dissipation is minimized by switching from SE to BTL mode, only when a higher output voltage swing is needed. The device is primarily developed for car radio applications.
MAX. 18 30 45 4 150 50 150 27 100 1
UNIT V V V A mA A k W W W dB dB dB mV dB dB
ORDERING INFORMATION TYPE NUMBER TDA1564TH TDA1564J 2004 Jan 27 PACKAGE NAME HSOP20 DBS17P DESCRIPTION plastic, heatsink small outline package; 20 leads; low stand-off height plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm) 2 VERSION SOT418-3 SOT243-1

BLOCK DIAGRAM
TDA1564
VP1 20
VP2 11
TDA1564TH
+
SLAVE CONTROL 7
OUT2
MUTE IN2 IN2 + 13
VI
IV
OUT2 +
+
VI
14
+
60 k 60 k 25 k Vref
+
VP 16
CIN
19
CSE
60 k IN1 IN1+ 18
60 k VI
+ +
VI
+
IV 3 OUT1
17 MUTE

SLAVE CONTROL
n.c. n.c.
1 10
OUT1+
STANDBY LOGIC 2
CLIP/PROTECTION TEMP PREWARNING 15
OFFSET DETECTION 12 9 5 6
mdb811
MODE
DIAG
OC1
OC2 GND1 GND2
Fig.1 Block diagram (TDA1564TH).
2004 Jan 27
TDA1564
VP1 5
VP2 13
TDA1564J
+
SLAVE CONTROL 10
OUT2
MUTE IN2 IN2 + 16
VI
IV
11
OUT2 +
+
VI
17
+
60 k 60 k 25 k Vref
+
VP 4
CIN
CSE
60 k IN1 IN1+ 2
60 k VI
+ +
VI
+
IV 7 OUT1
1 MUTE

SLAVE CONTROL
OUT1+
STANDBY LOGIC 6
CLIP/PROTECTION TEMP PREWARNING 15
OFFSET DETECTION 14 12 9
mgw244
MODE
DIAG
OC1
OC2
GND
Fig.2 Block diagram (TDA1564J).
2004 Jan 27

PINNING PIN SYMBOL TDA1564TH n.c. MODE OUT1 OUT1+ GND1 GND GND2 OUT2 OUT2+ OC2 n.c. VP2 OC1 IN2 IN2+ DIAG CSE IN1+ IN1 CIN VP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TDA1564J 6 7 8 9 10 11 12 13 14 16 17 15 4 1 2 3 5 not connected mute/standby/operating inverting output 1 non-inverting output 1 ground 1 ground ground 2 inverting output 2 non-inverting output 2 offset capacitor 2 not connected supply voltage 2 offset capacitor 1 inverting input 2 non-inverting input 2 diagnostic DESCRIPTION
TDA1564
electrolytic capacitor for single-ended (SE) mode non-inverting input 1 inverting input 1 common input supply voltage 1
2004 Jan 27
TDA1564
handbook, halfpage
IN1+ IN1 CIN CSE VP1
1 2 3 4 5 6 7 8 9
VP1 20 CIN 19 IN1 18 IN1+ 17 CSE 16 DIAG 15 IN2+ 14 IN2 13 OC1 12 VP2 11
001aaa307
1 2 3 4
n.c. MODE OUT1 OUT1+ GND1 GND2 OUT2 OUT2+ OC2
MODE OUT1 OUT1+ GND
TDA1564TH
5 6 7 8 9
TDA1564J
OUT2 10 OUT2 + 11 OC2 12 VP2 13 OC1 14 DIAG 15 IN2 16 IN2 + 17

MGW245
10 n.c.
Fig.3 Pin configuration (TDA1564TH).
Fig.4 Pin configuration (TDA1564J).
FUNCTIONAL DESCRIPTION The TDA1564 contains two identical amplifiers with differential inputs. At low output power [up to output amplitudes of 3 V (RMS) at VP = 14.4 V], the device operates as a normal SE amplifier. When a larger output voltage swing is needed, the circuit switches internally to BTL operation. With a sine wave input signal, the dissipation of a conventional BTL amplifier (up to 2 W output power) is more than twice the dissipation of the TDA1564 (see Fig.12). In normal use, when the amplifier is driven with music-like signals, the high (BTL) output power is only needed for a small percentage of time. Assuming that a music signal has a normal (Gaussian) amplitude distribution, the dissipation of a conventional BTL amplifier with the same output power is approximately 70 % higher (see Figs 13 and 14. 2004 Jan 27 6
The heatsink has to be designed for use with music signals. With such a heatsink, the thermal protection will disable the BTL mode when the junction temperature exceeds 150 C. In this case, the output power is limited to 5 W per amplifier. The gain of each amplifier is internally fixed at 26 dB. The device can be switched to the following modes via the MODE pin: Standby with low standby current (< 50 A) Mute condition, DC adjusted On, operation. The device is fully protected against a short-circuit of the output pins to ground and to the supply voltage. It is also protected against a short-circuit of the loudspeaker and against high junction temperatures. In the event of a permanent short-circuit condition to ground or the supply voltage, the output stage will be switched off, causing low dissipation. With a permanent short-circuit of the

loudspeaker, the output stage will be repeatedly switched on and off. The duty cycle in the on condition is low enough to prevent excessive dissipation. The device also has two independent DC offset detection circuits that can detect DC output voltages across the speakers. With a DC offset greater than 2 V, a warning is given on the diagnostic pin. There will be no internal shutdown with DC offsets. When the supply voltage drops below 6 V (e.g. engine start), the circuit mutes immediately, avoiding clicks from the electronic circuit preceding the power amplifier. The voltage of the SE electrolytic capacitor (pin 4) is kept at 0.5VP by means of a voltage buffer (see Fig.2). The value of this capacitor has an important influence on the output power in SE mode, especially at low signal frequencies. A high value is recommended to minimize dissipation at low frequencies. The diagnostic output is an open-collector output and requires a pull-up resistor. It gives the following outputs: Clip detection at THD = 2.5 % Short-circuit protection:
TDA1564
When a short-circuit occurs (for at least 10 ms) at the outputs to ground or the supply voltage, the output stages are switched off to prevent excessive dissipation; the outputs are switched on again approximately 500 ms after the short-circuit is removed, during this short-circuit condition the protection pin is LOW When a short-circuit occurs across the load (for at least 10 ms), the output stages are switched off for approximately 500 ms; after this time, a check is made to see whether the short-circuit is still present The power dissipation in any short-circuit condition is very low. During start-up/shutdown, when the product is internally muted Temperature prewarning: A prewarning (junction temperature > 145 C) indicates that the temperature protection will become active. The prewarning can be used to reduce the input signal and thus reduce the power dissipation. Offset detection: One of the channels has a DC output voltage greater than 2 V.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VP PARAMETER supply voltage CONDITIONS operating non-operating load dump; tr > 2.5 ms VP(sc) Vrp IORM Ptot Tstg Tvj Tamb short-circuit safe voltage reverse polarity voltage repetitive peak output current total power dissipation storage temperature virtual junction temperature ambient temperature 55 40 MIN. MAX. 18 30 45 18 6 4 60 +150 150 +85 V V V V V A W C C C UNIT
THERMAL CHARACTERISTICS SYMBOL Rth(j-c) Rth(j-a) Note 1. The value of Rth(c-h) depends on the application (see Fig.5). 2004 Jan 27 7 PARAMETER thermal resistance from junction to case thermal resistance from junction to ambient CONDITIONS note 1 in free air VALUE 1.3 40 UNIT K/W K/W

Heatsink design There are two parameters that determine the size of the heatsink. The first is the rating for the virtual junction temperature and the second is the ambient temperature at which the amplifier must still deliver its full power in the BTL mode. With a conventional BTL amplifier, the maximum power dissipation with a music-like signal (at each amplifier) will be approximately two times 6.5 W. At a virtual junction temperature of 150 C and a maximum ambient temperature of 65 C, Rth(vj-c) = 1.3 K/W and Rth(c-h) = 0.2 K/W, the thermal resistance of the heatsink 150 65 should be: --------------------- 1.3 0.2 = 5 K/W 2 6.5 Compared to a conventional BTL amplifier, the TDA1564 has a higher efficiency. The thermal resistance of the heatsink should be: 145 65 1.3 0.2 = 9 K/W 1.7 -------------------- 2 6.5 -
0.1 K/W
handbook, halfpage
TDA1564
virtual junction OUT 1 OUT 2 OUT 2
OUT 1
3.6 K/W
3.6 K/W 3.6 K/W
3.6 K/W
0.6 K/W
0.6 K/W
MGC424
case
Fig.5 Thermal equivalent resistance network.
2004 Jan 27

DC CHARACTERISTICS VP = 14.4 V; Tamb = 25 C; measured in Fig.9; unless otherwise specied. SYMBOL Supplies VP Iq(tot) Istb VCSE VO supply voltage total quiescent current standby current average electrolytic capacitor voltage at pin 4 DC output offset voltage on state mute state Mode select switch; see Fig.6 VMODE voltage at mode select pin standby condition mute condition on condition IMODE(sw) Diagnostic VDIAG IDIAG VO(DC) Protection Tpre Tdis(BTL) Notes 1. The circuit is DC biased at VP = 6 to 18 V and AC operating at VP = 8 to 18 V. 2. If the junction temperature exceeds 150 C, the output power is limited to 5 W per channel. prewarning temperature BTL disable temperature note 2 145 150 output voltage at the diagnostic output pin current through the diagnostic pin DC output voltage detection levels IDIAG = 2 mA; during any fault condition or clip detect during any fault condition or clip detect 2 1.4 2 switch current through pin 6 VMODE = 5 V 0 2 4 5 25 1 3 VP 40 note 1; Fig.17 RL = ; Fig.16 6.0 14.4 95 1 7.1 PARAMETER CONDITIONS MIN. TYP.
TDA1564
MAX.
UNIT
18.0 150 50 100 100
V mA A V mV mV
V V V A V mA V
0.5 2.5
C C
2004 Jan 27
TDA1564
MODE handbook, halfpage (V)
18
Operating
4 3 Mute 2 1 Standby 0
MGR176
Fig.6 Switching levels of the mode select pin.
2004 Jan 27
10
TDA1564
AC CHARACTERISTICS VP = 14.4 V; RL = 4 ; CCSE = 1000 F; f = 1 kHz; Tamb = 25 C; measured in Fig.9; unless otherwise specied. SYMBOL Po PARAMETER output power CONDITIONS THD = 0.5 %; Fig.18 THD = 10 %; Fig.18 EIAJ VP = 13.2 V; THD = 0.5 % VP = 13.2 V; THD = 10 % THD P Bp fro(l) fro(h) Gv SVRR total harmonic distortion power dissipation power bandwidth low frequency roll-off high frequency roll-off closed-loop voltage gain supply voltage ripple rejection THD = 1 %; Po = 1 dB with respect to 15 W 1 dB; note 2 1 dB Po = 1 W; Fig.21 Rs = 0 ; Vripple = 2 V (p-p); Fig.22 on/mute standby; f = 100 Hz to 10 kHz CMRR Zi Zi VSE-BTL Vout Vn(o) common mode rejection ratio input impedance mismatch in input impedance SE to BTL switch voltage level output voltage mute (RMS value) noise output voltage note 3 Vi = 1 V (RMS) on; Rs = 0 ; note 4 on; Rs = 10 k; note 4 mute; note 5 cs Gv Notes 1. The distortion is measured with a bandwidth of 10 Hz to 30 kHz. 2. Frequency response externally fixed (input capacitors determine the low frequency roll-off). 3. The SE to BTL switch voltage level depends on the value of VP. 4. Noise output voltage measured with a bandwidth of 20 Hz to 20 kHz. 5. Noise output voltage is independent of Rs. channel separation channel unbalance Rs = 0 ; Po = 15 W; Fig.23 Rs = 0 45 45 70 90 40 65 90 120 1 3 100 100 105 100 70 150 150 150 150 1 dB dB dB k % V V V V V dB dB Po = 1 W; note 1; Fig.19 MIN. 15 23 130 25 TYP. 19 25 38 16 20 0.1 20 to 15000 25 26 MAX. UNIT 27 W W W W W % W Hz Hz kHz dB
see Figs 12 and 13
2004 Jan 27
11
TDA1564
handbook, halfpage Io handbook, halfpage V

MGR177
10 s
max
t
0 max short-circuit removed short-circuit to ground
DIAG CLIP
0
0 t 500 ms 500 ms 500 ms
maximum current
short-circuit to supply pins

MGW246
Fig.7 Clip detection waveforms.

(1)
Fig.8 Protection waveforms.
2004 Jan 27
12

TEST AND APPLICATION INFORMATION
TDA1564
handbook, full pagewidth
VP1 5
VP2 13
220 nF
2200 F
VP
TDA1564J
0.5Rs 220 nF 4 IN2 16 10 OUT2 100 nF 3.9 100 nF
+
3.9
0.5Rs 220 nF IN2+ 17 60 k CIN 3 10 F 60 k 60 k 60 k 25 k Vref
11 OUT2+
4 CSE 1000 F
0.5Rs 220 nF
IN1 2
7 OUT1 3.9 100 nF 100 nF 3.9
4 0.5Rs 220 nF IN1+ 1
8 OUT1+
STANDBY LOGIC 6 MODE Vms
CLIP AND DIAGNOSTIC 12 OC2 22 F 14 OC1 22 F 15 DIAG Rpu Vlogic

MGW247
signal ground 9 GND power ground
Connect Boucherot filter to pin 8 or pin 10 with the shortest possible connection.
Fig.9 Application diagram (TDA1564J).
2004 Jan 27
13
TDA1564
TDA1564J
RL 2000
In1
TDA1565J
In2
sgnd Mute On Off Out1 Out2
sgnd diag GND
VP
MGW248
Dimensions in mm.
Fig.10 PCB layout (component side) for the application of Fig.9.
2004 Jan 27
14
TDA1564
High efficiency
3.9 In2
100 nF 100 nF 3.9
Cool
220 nF 17
Power
220 nF 1 220 nF
In1
GND
2.7 k Out2
Continuous offset detection

4.7 k 24 k Out1
100 nF 3.9 100 nF VP
MGW249
Dimensions in mm.
Fig.11 PCB layout (soldering side) for the application of Fig.9.
2004 Jan 27
15
TDA1564
handbook, halfpage
25
MGW250
P (W) 20
(1)
handbook, halfpage
25
MGW251
P (W) 20
(1)
(2)
15
15
(2)
10
10
0 0 4 8 12 16 Po (W) Input signal 1 kHz, sinusoidal; VP = 14.4 V. (1) For a conventional BTL amplifier. (2) For TDA1564. 20
0 0 2 4 6 8 Po (W) 10
(1) For a conventional BTL amplifier. (2) For TDA1564.
Fig.12 Power dissipation as a function of output power; sine wave driven.
Fig.13 Power dissipation as a function of output power; pink noise through IEC-60268 filter.
430
2.2 F
330
2.2 F
470 nF
input
3.3 k
91 nF
3.3 k
68 nF
10 k
output
MGC428
Fig.14 IEC-60268 filter.
2004 Jan 27
16
TDA1564
VP1 5
VP2 13
220 nF
2200 F
VP
TDA1564J
IN2 16 220 nF 4 10 OUT2 100 nF 3.9 100 nF
+
3.9
IN2+ 17 220 nF 60 k 60 k 25 k Vref
11 OUT2+
CIN 3 10 F IEC-60268 FILTER IN1 2 pink noise 220 nF 60 k
4 CSE 1000 F
60 k
7 OUT1 3.9 100 nF 100 nF 3.9
4 IN1+ 1 220 nF
8 OUT1+
INTERFACE signal ground MS 6 MODE Vms OFFSET 12 OC2 22 F 14 OC1 22 F DIAG 15 DIAG Rpu Vlogic
MGW252
9 GND
power ground
Fig.15 Test and application diagram for dissipation measurements with a music-like signal (pink noise).
2004 Jan 27
17
TDA1564
MGW253
handbook, halfpage
150
handbook, halfpage
200
MGW254
IP (mA) 100
IP (mA) 150
3 100
50
50
0 0 5 10 15 20 VP (V) 25
0 0 1 2 3 4 5 VMODE (V)
VMODE = 5 V; RI = .
VP = 14.4 V (1) Standby. (2) Mute. (3) Operating.
Fig.16 Quiescent current as a function of supply voltage.
Fig.17 Supply current as a function of VMODE.
handbook, halfpage
40
MGW255
102 handbook, halfpage THD + N (%) 10
MGW256
Po (W) 30
(1)
(2)
(3)
20
(1)
10
10 1
(2) (3)
0 8 10 12 14 16 VP (V) (1) TDH + N = 10 %. (2) TDH + N = 2.5 %. (3) TDH + N = 0.5 %. 18
10 2 10 2
10 1
10
Po (W)
102
(1) f = 10 kHz. (2) f = 1 kHz. (3) f = 100 kHz.
Fig.18 Output power as a function of supply voltage.
Fig.19 THD + noise as a function of output power.
2004 Jan 27
18
TDA1564
handbook, halfpage
10
MGW257
handbook, halfpage
28
MGW258
THD + N (%)
(1)
Gv (dB) 26
24
(2)
10 1 22
10 2 10
102
103
104 f (Hz)
105
20 10
102
103
104
105 f (Hz)
106
(1) Po = 10 W. (2) Po = 1 W.
Fig.20 THD + noise as a function of frequency.
Fig.21 Voltage gain as a function of frequency.
handbook, halfpage
20
MGW259
handbook, halfpage
(1)
SVRR (dB) 40
cs (dB)
20
MGW260
40
(1) (2)
60
60
80
(2)
80
100
100
120 10
102
103
104 f (Hz)
105
120 10
102
103
104 f (Hz)
105
(1) On/Mute. (2) Standby.
(1) Po2 = 10 W. (2) Po2 = 1 W.
Fig.22 SVRR as a function of frequency.
Fig.23 Channel separation as a function of frequency.
2004 Jan 27
19
TDA1564
VP Vload
MBH691
VP VP Vmaster 1/2 VP
0 VP Vslave 1/2 VP
t (ms)
See Fig.9 Vload = V7 V8 or V11 V10. Vmaster = V7 or V11. Vslave = V8 or V10.
Fig.24 Output waveforms.
2004 Jan 27
20

APPLICATION NOTES Advantages of high efciency 1. Power conversion improvement (power supply): Usually, the fact that the reduction of dissipation is directly related to supply current reduction, is neglected. One advantage is less voltage drop in the whole supply chain. Another advantage is less stress for the coil in the supply line. Even the adapter or supply circuit remains cooler than before due to the reduced heat dissipation in the whole chain because more supply current will be converted into output power. 2. Power dissipation reduction: This is the best known advantage of high efficiency amplifiers. 3. Heatsink size reduction: The heatsink size of a conventional amplifier may be reduced with approximately 50 % at Vp = 14.4 V when the TDA1564 will be used. In that case, the maximum heatsink temperature will remain the same. 4. Heatsink temperature reduction: The power dissipation and the thermal resistance of the heatsink determine the heatsink temperature rise. When the same heatsink size is used from a conventional amplifier, the maximum heatsink temperature decreases and also the maximum junction temperature, which extends the life of this semiconductor device. The maximum dissipation with music-like input signals decreases by 40 %. It is clear that the use of the TDA1564 saves a significant amount of energy. The maximum supply current decreases by approximately 32 %, that reduces the dissipation in the amplifier as well as in the whole supply chain. The TDA1564 allows a heatsink size reduction of approximately 50 % or the heatsink temperature decreases by 40 % when the heatsink size hasnt been changed.
Heatsink size reduction of 50%
handbook, halfpage
TDA1564
VP = 14.4 V
Supply current reduction of 32%
Power dissipation reduction of 40% at Po = 1.6 W
Same junction temperature
choice
Same heatsink size
Heatsink temperature reduction of 40%

MGS824
Fig.25 Heatsink design.
Advantage of the concept used by TDA1564 The TDA1564 is highly efficient under all conditions, because it uses a single-ended capacitor to create a non-dissipating half supply voltage. Other concepts rely on the fact that both input signals are the same in amplitude and phase. With the concept of a SE capacitor it means that it doesnt matter what kind of signal processing is done on the input signals. For example, amplitude difference, phase shift or delays between both input signals, or other DSP processing, have no impact on the efficiency.
2004 Jan 27
21

INTERNAL PIN CONFIGURATIONS PIN NAME TDA1564TH TDA1564J IN1+, IN1, IN2, IN2+ and CIN
17, 18, 13, 14 J 1, 2, 16, 17 VP1, VP2
TDA1564
EQUIVALENT CIRCUIT
17, 18, 13, 14 1, 2, 16, 17 and 19 and 3
VP1, VP2
19 3
MGR182
16
CSE
VP2
16 TH 4 J
MGW261
MODE
TH 2 J 6
MGW262
2004 Jan 27
22

PIN NAME TDA1564TH 3, 8 TDA1564J 7, 11 OUT1, OUT2+
VP1, VP2
TDA1564
EQUIVALENT CIRCUIT
3, 8 7, 11 16 TH 4 J
TH J
MGR185
4, 7
8, 10
OUT1+, OUT2
VP1, VP2
4, 7 8, 10 16 TH 4 J
TH J
MGR186
9, 12
12, 14
OC1, OC2
VP2 TH 9, 12 J 12, 14
MGW263
15
15
DIAG
VP2
15
MGW264
2004 Jan 27
23

PACKAGE OUTLINES
HSOP20: plastic, heatsink small outline package; 20 leads; low stand-off height
TDA1564
SOT418-3
E x
A X
c y E2 HE v M A
D1 D2 1 pin 1 index Q A2 E1 A4 Lp detail X 20 Z e bp 11 w M (A3) A 10
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A A2 max. 3.5 3.5 3.2 A3 0.35 A4(1) bp c D(2) D1 D2 1.1 0.9 E(2) 11.1 10.9 E1 6.2 5.8 E2 2.9 2.5 e 1.27 HE 14.5 13.9 Lp 1.1 0.8 Q 1.7 1.5 v w x y Z 2.5 2.0 8 0
+0.08 0.53 0.32 16.0 13.0 0.04 0.40 0.23 15.8 12.6
0.25 0.25 0.03 0.07
Notes 1. Limits per individual lead. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT418-3 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 02-02-12 03-07-23
2004 Jan 27
24
TDA1564
DBS17P: plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm)
SOT243-1
non-concave D x Dh
Eh
view B: mounting base side A2
B j E A
L3
Q c v M
1 Z e e1 w M
17 m e2
bp
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 17.0 15.5 A2 4.6 4.4 bp 0.75 0.60 c 0.48 0.38 D (1) 24.0 23.6 d 20.0 19.6 Dh 10 E (1) 12.2 11.8 e e1 e2 5.08 Eh 6 j 3.4 3.1 L 12.4 11.0 L3 2.4 1.6 m 4.3 Q 2.1 1.8 v 0.8 w 0.4 x 0.03 Z (1) 2.00 1.45
2.54 1.27
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT243-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-17 03-03-12
2004 Jan 27
25

SOLDERING Introduction This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Through-hole mount packages SOLDERING BY DIPPING OR BY SOLDER WAVE Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. MANUAL SOLDERING Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. Surface mount packages REFLOW SOLDERING Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and 2004 Jan 27 26
TDA1564
cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: below 225 C (SnPb process) or below 245 C (Pb-free process) for all the BGA, HTSSON..T and SSOP-T packages for packages with a thickness 2.5 mm for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. WAVE SOLDERING Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. For packages with leads on two sides and a pitch (e): larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be
TDA1564
applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. MANUAL SOLDERING Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. Suitability of IC packages for wave, reow and dipping soldering methods MOUNTING Through-hole mount CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL Through-holesurface mount Surface mount PMFP(4) BGA, HTSSON..T(5), LBGA, LFBGA, SQFP, SSOP-T(5), TFBGA, USON, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(7), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L(11), PMFP(10), WQCCN32L(11) Notes 1. For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. 3. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 4. Hot bar soldering or manual soldering is suitable for PMFP packages. 5. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 6. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 7. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. PACKAGE(1) suitable suitable(3) not suitable not suitable not suitable(6) SOLDERING METHOD WAVE REFLOW(2) DIPPING not suitable suitable suitable suitable
suitable not not recommended(7)(8) recommended(9)
suitable suitable suitable not suitable
not suitable
2004 Jan 27
27
TDA1564
8. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 9. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 10. Hot bar or manual soldering is suitable for PMFP packages. 11. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request.
2004 Jan 27
28

DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
TDA1564
This data sheet contains data from the objective specication for product development. Philips Semiconductors reserves the right to change the specication in any manner without notice. This data sheet contains data from the preliminary specication. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specication without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specication. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notication (CPCN).
II
Preliminary data Qualication
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status Production), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2004 Jan 27
29
Philips Semiconductors a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales ofces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R32/04/pp30
Date of release: 2004
Jan 27
Document order number:
9397 750 12613

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INTEGRATED CIRCUITS

TDA1564 High efficiency 2 25 W/4 stereo car radio power amplifier

High efciency 2 25 W/4 stereo car radio power amplier

MAX. 18 30 45 4 150 50 150 27 100 1

High efciency 2 25 W/4 stereo car radio power amplier

MUTE IN2 IN2 + 13

CLIP/PROTECTION TEMP PREWARNING 15

OC2 GND1 GND2

Fig.1 Block diagram (TDA1564TH).

High efciency 2 25 W/4 stereo car radio power amplier

MUTE IN2 IN2 + 16

CLIP/PROTECTION TEMP PREWARNING 15

Fig.2 Block diagram (TDA1564J).

High efciency 2 25 W/4 stereo car radio power amplier

High efciency 2 25 W/4 stereo car radio power amplier

IN1+ IN1 CIN CSE VP1

n.c. MODE OUT1 OUT1+ GND1 GND2 OUT2 OUT2+ OC2

MODE OUT1 OUT1+ GND

OUT2 10 OUT2 + 11 OC2 12 VP2 13 OC1 14 DIAG 15 IN2 16 IN2 + 17

Fig.3 Pin configuration (TDA1564TH).

Fig.4 Pin configuration (TDA1564J).

High efciency 2 25 W/4 stereo car radio power amplier

High efciency 2 25 W/4 stereo car radio power amplier

virtual junction OUT 1 OUT 2 OUT 2

3.6 K/W 3.6 K/W

Fig.5 Thermal equivalent resistance network.

High efciency 2 25 W/4 stereo car radio power amplier

18.0 150 50 100 100

High efciency 2 25 W/4 stereo car radio power amplier

MODE handbook, halfpage (V)

Fig.6 Switching levels of the mode select pin.

High efciency 2 25 W/4 stereo car radio power amplier

see Figs 12 and 13

High efciency 2 25 W/4 stereo car radio power amplier

handbook, halfpage Io handbook, halfpage V

short-circuit to supply pins

Fig.7 Clip detection waveforms.

Fig.8 Protection waveforms.

High efciency 2 25 W/4 stereo car radio power amplier

handbook, full pagewidth

0.5Rs 220 nF IN2+ 17 60 k CIN 3 10 F 60 k 60 k 60 k 25 k Vref

7 OUT1 3.9 100 nF 100 nF 3.9

4 0.5Rs 220 nF IN1+ 1

STANDBY LOGIC 6 MODE Vms

CLIP AND DIAGNOSTIC 12 OC2 22 F 14 OC1 22 F 15 DIAG Rpu Vlogic

signal ground 9 GND power ground

Fig.9 Application diagram (TDA1564J).

High efciency 2 25 W/4 stereo car radio power amplier

handbook, full pagewidth

sgnd Mute On Off Out1 Out2

sgnd diag GND

Fig.10 PCB layout (component side) for the application of Fig.9.

High efciency 2 25 W/4 stereo car radio power amplier

handbook, full pagewidth

100 nF 100 nF 3.9

Continuous offset detection

100 nF 3.9 100 nF VP

Fig.11 PCB layout (soldering side) for the application of Fig.9.

High efciency 2 25 W/4 stereo car radio power amplier

(1) For a conventional BTL amplifier. (2) For TDA1564.