SFSU - ENGR 301 ELECTRONICS LAB

LAB #2: OPERATIONAL AMPLIFIER CHARACTERISTICS

Updated March 15, 2004

Objective:
To measure the most common parameters of a 741 op amp: The input bias and offset currents IB and IOS, the input offset voltage VOS, the power-supply and common-mode rejection ratios PSRR and CMRR, the output saturation limits VOH and VOL, the output short-circuit current ISC, the open-loop dc gain AOL0, the gain-bandwidth product GBP, the small-signal rise time tR, and the slew rate SR. To assess the faithfulness of the 741 macro-model available in the PSpice library.

1 741C op amp, 1 10-k potentiometer, 1 100-k potentiometer, 2 0.1-F capacitors, and resistors: 2 100 , 1 2 k, 3 10.0 k, 2 100 k, and 2 1.0 M (all 5%, W). A dual 15-V regulated variable power supply, a 5-V fixed dc source, a waveform generator (sinewave and square-wave), a high-sensitivity (10 -V or better) digital multi-meter, and a dual-trace oscilloscope.

Components:

Instrumentation:

PART I THEORETICAL BACKGROUND

Ideally, an op amp has (a) infinite open-loop gain regardless of frequency, it draws (b) zero currents at its input pins, and it can provide (c) any voltage or current at its output pin. In a practical op amp, the open loop gain is not only finite, but it rolls off with frequency. Moreover, the input pins draw tiny currents IP and IN, where labels P and N denote, respectively, the noninverting and the inverting input pins. Also, if we tie the input pins together so that vN = vP, the output vO will not be zero due to mismatches in the internal circuits processing vP and vN ; if we wish to drive it to zero, a tiny corrective voltage must be applied between the input pins, called the input offset voltage VOS. Finally, a practical op amp can only swing vO within a limited range, VOL vO VOH , where VOL and VOH are the lower and upper output saturation limits. Similarly, it can supply an output current iO of no more than a specified value called the output short-circuit current ISC. The most popular op amp is the A741, developed by Fairchild in the late nineteen-sixties and since then available from virtually any analog IC manufacturer. You can download the 741 data sheets from the website of any analog IC manufacturer, or you can perform your own search using, for instance, http://www.google.com and searching for 741 operational amplifier or variants thereof. The quantities IP, IN, and VOS are referred to as dc imperfections. The mean of IP and IN is called the input bias current IB, and their difference the input offset current IOS, IB = IP + IN 2

I OS = I P I N

(1)

The data sheets of the 741C version give the following typical (maximum) room-temperature values: IB = 80 nA (500 nA), IOS = 20 nA (200 nA), VOS = 2.0 mV (6.0 mV). Note that IOS and VOS may be positive or negative, depending on the direction of mismatch between the internal circuits processing each input. The input offset voltage VOS varies, with temperature (for a general-purpose op amp, the thermal
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drift is typically VOS / T 5 V/C), as well as with the power supply and the common-mode input voltage. Denoting the supply voltages as VS, we define the power-supply rejection ratio (PSRR) as VOS 1 = PSRR VS (2)

For instance, if it is found that VOS changes by 50 V for every 1-V change in VS, then we have 1/PSRR = 50 106 /1 , or PSRR = 2 104. This is also expressed in decibels as PSRRdB = 20 log10 (2 104) = 86 dB. Similar considerations hold for the common-mode rejection ratio (CMRR), defined as VOS 1 = CMRR vCM where vCM is the common-mode input voltage to the op amp, in turn defined as vCM = vP + v N 2 (4) (3)

Since we know that when operated in the negative-feedback mode the op amp yields vN vP, we can approximate vCM vP. The 741C data sheets give the following typical as well as worst-case values: PSRR = 15 V/V (50 V/V), and CMRR = 95 dB (80 dB). Ideally, wed want PSRR = CMRR = . With VS = 15 V, the 741C data sheets report ISC 25 mA. Moreover, with a typical output load of 2 k, they give VOH +13 V and VOL -13 V. At low frequencies the open-loop gain AOL, though not infinite, is still fairly large. This gain is aptly called the DC gain and is denoted as AOL0. For the 741C op amp, AOL0 = 200,000 V/V typical (50,000 V/V minimum). An op amp provides a high gain only up to some frequency called the open-loop gain bandwidth fb, after which gain rolls with frequency until a frequency ft is reached, at which gain becomes unity, or 0 dB. Above ft gain is less than unity; hence, ft is called the transition frequency. The 741C op amp typically has fb 5 Hz and ft 1 MHz. For most op amps, including the 741 type, gain rolls off at a constant rate of 20 dB/dec, indicating that we can express the open-loop gain AOL(jf) mathematically as AOL ( jf ) = AOL 0 1 + jf / fb (5)

For the 741C op amp, AOL(jf) = (2 105 V/V)/[1 + jf/(5 Hz)]. The gain-bandwidth product is defined as GBP = AOL f. For an op amp with a gain rolloff of 20 db/dec, this product is constant for f >> fb, GBP = AOL0 fb = ft (6)

The frequency response of an op amp is readily visualized via PSpice using suitable op amp models called macro-models. The PSpice circuit of Fig. 1 is used to display both the open-loop gain of the basic op amp and the closed-loop gain of the non-inverting amplifier configuration, which is obtained by applying negative feedback around the basic op amp via R1 and R2. An important parameter arising in negative feedback applications is the feedback factor , representing the portion of vO being fed back to the inverting input as vN, or = vn/vO. Using the voltage divider formula,
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VCC 15Vdc 7 Vi 1Vac 0Vdc uA741 2 3

+ U1

V+

OS2

5 6 1 Vo

OUT OS1 V-

0
15Vdc VEE

R1 100

Vn

R2 100k

Fig. 1 PSpice circuit to plot the open and closed loop gains.

R1 1 = R1 + R2 1 + R2 / R1

(7)

Figure 2 indicates a closed-loop gain of the type ACL ( jf ) = ACL 0 1 + jf / f B (8)

where ACL0 and fB are the closed-loop dc gain and the closed-loop bandwidth, respectively. We have ACL 0 = and f B = ft = ft 1 + R2 / R1 (9b) 1 R =1+ 2 R1 (9a)

Fig. 2 Gain plots for the circuit of Fig. 1.

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VCC V1 = 0V V2 = 5mV TD = 10ns TR = 10ns TF = 10ns PW = 10us PER = 20us

15Vdc

vI uA741 2 N

+ U1 -

V+

OS2

5 6 1 O

OUT OS1 V-

15Vdc

VEE

Fig. 3 PSpice circuit to plot the small-signal transient response.

R2

R1 10k

100k

In our example, ACL0 103 V/V = 60 dB, and fB 1 kHz. We also note that for f >> fB the GBP is again constant and it is the same as in the open-loop case, namely, GBP = ft = 1 MHz. You can simulate this circuit on your own by downloading its appropriate files from the Web. To this end, go to http://online.sfsu.edu/~sfranco/CoursesAndLabs/Labs/301Labs.html, and once there, click on PSpice Examples and follow the instructions contained in the Readme file. If we feed our amplifier with an input step of sufficiently small amplitude, the response is an exponential transient governed by the time constant = 1 2 f t (10)

The amount of time it takes for this transient to swing from 10% to 90% of its final value is called the rise time tR. It is readily seen that tR = ln 9 = 0.35/ft. The transient response too can be visualized via PSpice, and Fig. 3 shows a circuit to do it for the case = 1/11. We now have tR = 0.35/(106/11) = 3.85 s, a result that you can readily verify by studying the output waveform of Fig. 4. On the other hand, had

Fig. 4 Small-signal transient response of the circuit of Fig. 3.

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VCC V1 = 0V V2 = 1V TD = 100ns TR = 100ns TF = 100ns PW = 50us PER = 100us

15Vdc

vI uA741 2 N

+ U1 -

V+

OS2

5 6 O 1

OUT OS1 V-

15Vdc

VEE

R1 10k

R2 100k

Fig. 5 PSpice circuit to plot the large-signal transient response.

the same op amp been configured as a voltage follower ( = 1), then we would have had tR = 350 ns. If the amplitude of the input step is gradually increased, a point is reached at which the output becomes slew-rate limited, and the initial portion of the transient becomes a linear ramp ramp. The slope of this ramp is called the slew rate (SR). The 741C data sheets give SR 0.5 V/s. We use the circuit of Fig. 5 to visualize a slew-rate limited response, and the result is shown in Fig. 6. The borderline between small-signal and large-signal transient response occurs when the maximum slope of the exponential transient becomes equal to the slew rate. As we know, the slope is maximum at the onset of the transient, and its value is Vom/, where Vom denotes the amplitude of the output transient. Imposing Vom/ = SR, we find the borderline output amplitude to be Vom = SR = SR/(2ft). In our example, Vom = 0.5 106/(2 106/11) = 0.875V. This corresponds to an input step amplitude Vim = Vom/11 80 mV. It is interesting to observe that in both responses, the op amp yields vP vN 0 only once the transient has died out. During the transient, particularly at its onset, vN is quite different from vP. Can you exercise your engineering judgement to justify this? For a sine-wave input, it is of interest to know the borderline frequency above which the output

Fig. 6 Large-signal transient response of the circuit of Fig. 5.

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will distort due to slew-rate limiting. Expressing the output as vo(t) = Vomsin(2ft), we note that the maximum slope occurs at the zero crossings of vo(t), where slope is 2fVom. Letting 2fVom SR gives f SR 2 Vom (11)

In the case in which Vom is as large at it can be, before output clipping occurs, the upper limit provided by Eq. (11) is called the full-power bandwidth (FPB). For a 741C operating with Vom = 10 V, we get FPB 8 kHz.

PART II EXPERIMENTAL PART

The 741 data sheets give typical data, that is, data that were obtained by averaging over a large number of samples. The 741 macro-model is based on typical data. In this lab we shall characterize a particular 741 sample, and compare against the data sheets to assess how close our sample is to typical, as well as how realistic the PSpice simulations are. Like all integrated circuits, op amps are delicate devices that must be used with care to avoid permanently damaging them. Refer to the Appendix for useful tips on how to construct op amp circuits. In particular, always use two 0.1-F capacitors to bypass the 15-V power supplies, and always turn off power before making any changes in a circuit. Failure to do so may destroy your device, indicating that the measurements performed up to that point will have to be repeated on a different sample. Henceforth, steps shall be identified as follows: C for calculations, M for measurements, and S for SPICE simulation. Moreover, each measured value should be expressed in the form X X (e.g. VOS = 1.52 mV 0.01 mV), where X represents the estimated uncertainty of your measurement, something you have to figure out based on measurement concepts and techniques learned in Engr 206 and Engr 300.

Finding VOS, IP, IN, and PSRR:

Mark one of the 741 samples available in your kit (the other is a spare), and proceed as instructed. M1: With power off, assemble the circuit of Fig. 7(a), using the instructions of the Appendix as guidelines for good circuit-assembly habits. Apply power, and measure the output with your digital

(a)

(b)
Fig. 7 Test circuits to measure VOS, IP, IN, and PSRR.

(c)

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multi-meter configured as a DC voltmeter with the highest sensitivity available (10 V or better). Given that the op amp is working as a voltage follower, the output reading is simply the input offset voltage VOS. How does it compare with the value given in the data sheets? Comment. Warning: Because of thermal drift, the least significant digits of your multi-meter are likely to fluctuate, so it is up to you to decide how to interpret your readings, and to justify your decision. MC2: Turn power off, and insert the 1-M resistor shown in Fig. 7(b). This is intended to cause the current IP drawn by the non-inverting input to develop the voltage VP = RIP, so that V1 = VOS RIP, by the superposition principle. Apply power, measure V1, and calculate IP = (VOS V1)/R, with VOS as found in Step M1. For accurate results, you may wish to measure R with the ohmmeter. MC3: Turn power off, and connect the 1-M resistor as in Fig. 7(c). By similar reasoning, the current IN drawn by the inverting input will yield V2 = VOS + RIN. Apply power, measure V2, and calculate IN = (V2 VOS)/R, with VOS again as found in Step M1. C4: Using Eq. (1), calculate IB and IOS. Hence, compare with their data-sheet values, and comment. MC5: Turn power off, configure the circuit again as in Fig. 7(a), and lower the supply voltages from 15 V to 10 V, thus effecting a power-supply change VS = 5 V. Apply power, measure the new value of VOS, and find the difference VOS between the current reading and that of Step M1, which you may wish to repeat, just to make sure that the offset hasnt drifted meanwhile. Finally, use Eq. (2) to find 1/PSRR |VOS/VS|, in V/V. Compare with the value given in the data sheets, and comment.

The Difference Amplifier:

To understand the implications of various op amp imperfections, we examine a very popular circuit, namely, the difference amplifier of Fig. 8a. As we know, if its resistances are in equal ratios R4 R2 = R3 R1 then the circuit gives (12)

(a ) Fig. 8 The difference amplifier .

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(b )

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vO =

R2 (v2 v1 ) R1

(13)

With the component values shown, vO = 100(v2 v1). Equation (13) indicates that vO depends exclusively on the difference between the inputs, even if they happen to be different from zero. In particular, if the inputs are grounded (v1 = v2 = 0) as in Fig. 8b, the circuit ought to give 0 V also at the output. In practice, it yields an output error EO generally different from zero. C6: Show that the circuit of Fig. 8b gives EO = 1 [VOS ( R1 // R2 ) I OS ] (14)

where 1/ is aptly called the noise gain. Hence, use the experimental data gathered so far to predict the value of EO. M7: Pick a pair of 10-k and a pair of 1-M resistors from your kit and measure all four of them with the digital ohmmeter. Then, with power off, assemble the circuit of Fig. 8(b), using the smaller of the two 10-k resistors as R1 (and, of course, the larger one as R3), and using the larger of the two 1-M resistors as R2 (and, of course, the smaller one as R4). This arrangement results in the greatest degree of imbalance in the resistance ratios. Apply power, measure EO, compare with the predicted value of Step C6, and account for possible differences.

Offset Error Nulling:

M8: The 741 op comes with provision for nulling the input offset error appearing inside brackets in Eq. (14). Nulling is accomplished by connecting an external 10-k potentiometer as specified in the data sheets. The purpose of this pot is to deliberately imbalance the internal circuitry of the op amp so as to allow the user to drive EO to zero. With power off, connect the pot between pins 1 and 5 as shown in Fig. 9. Reapply power, and vary the wiper until EO comes as close as possible to 0 V, giving the appearance of an offset-less op amp! Once the pot has been adjusted, it should not be touched again, unless necessary because of thermal drift or other changes in the circuit.

Finding the CMRR:

If the left terminals of R1 and R3 are lifted off ground and driven with a common voltage vCM as depicted

Fig. 9 Difference amplifier with provision for offset nulling.

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Fig. 10 Circuit setup to optimize the CMRR of a difference amplifier.

in Fig. 10, we expect that a true difference amplifier will give vO = 0 regardless of vCM. In practice, vO is likely to be different from zero because actual resistors will fail to satisfy Eq. (12) exactly, and also because of op amp nonidealities. The ratio vO/vCM is called the common-mode gain, Acm = vO vCM (15)

and our goal is to minimize it to approach the ideal condition Acm 0. (As we shall see shortly, this is achieved via the 100-k pot, as shown.) If we define vDM = v2 v1 in Fig. 8a, then the gain Adm = vO vDM (16)

is by contrast called the differential-mode gain. (The circuit of Fig. 8a has Adm = R2/R1 = 100 V/V.) A very important figure of merit of a difference amplifier is its common mode rejection ratio, defined as CMRRdB = 20log Adm Acm (17)

Ideally, wed want Acm 0, and thus CMRR . In practice, Acm will be small but not zero, and clearly the smaller Acm, the closer the amplifier will be to ideal. MC9: With power off, add to your difference amplifier the 100-k pot as indicated in Fig. 10. Initially, turn the wiper all the way up so as to short out the pot resistance and leave the resistance ratios as in Fig. 9. Next, apply power, and using Ch. 1 of the oscilloscope to monitor vCM, adjust the waveform generator so that vCM is a 100-Hz sine wave alternating between 5 V and +5 V. Observing vO with Ch. 2 of the oscilloscope, measure the gain Acm = vO/vCM, and insert it into Eq. (17), along with Adm 100 V/V, to find the value of CMRRdB for your difference amplifier.

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Fig. 11 Test circuit to find the CMRR of the basic op amp.

MC10: Now vary the wiper of the 100-k pot in Fig. 10 until vO is minimized. This, in turn, will maximize the CMRR of your circuit. What is its new value, in dB? Remark: If the resistance range provided by the pot is insufficient, insert a series resistance (50 k) between pot and ground. MC11: Now let us take advantage of the calibrated circuit of Fig. 10 to find the CMRR of the basic op amp via Eq. (3). With power off, insert the additional 10-k resistor shown in Fig. 11 (the reason is given below). Then, apply power, and measure VOS first with the switch to ground, then with the switch to +5 V (obtain 5 V from the third output available from your bench power supply). Next, calculate the difference VOS between the two readings. Note that flipping the switch from 0 V to 5 V causes the common-mode input to the basic op amp to change by vCM = 5R4/(R3 + R4) 5 V, so apply Eq. (3) to estimate CMRR |vCM/VOS| |(5 V)/VOS|. Give its value in dB, compare with the data sheets, and comment. Remark: Never connect a cable directly to the inverting input of an op amp! The cables stray capacitance be it the cable of a voltmeter or the probe of an oscilloscope tends to destabilize the op amp, possibly causing it to oscillate. Always interpose an isolating resistor, such as the 10-k resistor shown. MC12: With power off, assemble the circuit of Fig. 12 (you can create the 15-k resistor as 10 k in series with the 10-k pot with the wiper set in the middle). Then, apply power, and measure VD and VO with the switch first flipped to +15 V (positive supply), then flipped to 15 V (negative supply). (When measuring VD, be sure to configure the voltmeter for its maximum sensitivity!) Next, calculate the differences VD and VO, and finally obtain AOL0 = VO /VD. Compare with the data sheets, comment. Remark: Note again the use of the 10-k isolating resistor! MC13: In the circuit of Fig. 12, connect the current meter directly between the output node and ground, and measure current first with the switch to +15 V, then with the switch to 15 V. The two readings represent, respectively, the maximum current that the op amp is capable of sinking from and sourcing to
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Finding AOL0 and ISC:

Fig. 12 Test circuit to find AOL0 and ISC.

an output load. Are your readings approximately similar? How do they compare with the value of ISC given in the data sheets? We now investigate the frequency response using the circuit of Fig. 13. Here, the op amp is configured to amplify the input vi with the gain ACL0 = 1/ = 1 + R2/R1 1000 V/V. (Before assembling the circuit, you may want to measure R1 and R2 to find the actual value of .) To prevent vo from saturating, we must keep vi suitably small, so we obtain it from the waveform generator vs via a voltage divider such that vi= vsR4/(R3 + R4 ) vs/1000. Moreover, since we have a new set of resistance values, the error term within brackets in Eq. (14) will also change, mandating that you again offset null your amplifier as in Step M8. MC14: With power off, assemble the circuit of Fig. 13. Apply power, and null the offset as in Step M8. Next, while monitoring vs with Ch. 1 of the oscilloscope, adjust the waveform generator so that vs is a sine wave with an amplitude of 2.5 V (5-V peak-to-peak), 0-V DC, and frequency f 10 Hz. Then, while monitoring vo with Ch. 2 of the oscilloscope, gradually increase f while keeping the amplitude of vs constant, until the amplitude of vo drops to 0.707 (70.7%, or 3 dB) of its low-frequency value. Record this frequency, which is the closed-loop bandwidth fB of your circuit. Finally, use Eq. (9b) to estimate ft. How does it compare with the data sheets? Comment.

Finding fb and ft:

Fig. 13 Test circuit to investigate the frequency response.

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M15: In the circuit of Fig. 13 measure the amplitude Vom of vo also at f = 10fB and at f = 100fB, and find the corresponding values of the closed-loop gain ACL = Vom/Vim, where Vim is the amplitude of vi. Finally verify the constancy of the GBP, namely, GBP = ACL f = constant. C16: Using the value of AOL0 obtained in step MC12, estimate fb. Hence, sketch the magnitude Bode plots of both the open-loop and closed-loop responses of your particular amplifier sample. How do they compare with the typical plots of Fig. 2? Comment. M17: With power off, change R4 to 10 k in the circuit of Fig. 13, and connect a 2-k load between the op amp output pin (pin #6) and ground. Moreover, adjust the waveform generator so that vs is a 1-kHz sine wave with minimum amplitude and zero DC offset. Next, apply power, and while monitoring vo with the oscilloscope, gradually increase the amplitude of vs until vo clips. Measure on the oscilloscope the upper and lower saturation limits VOH and VOL. Are they symmetric? Different? Justify. How do they compare with the data-sheet values? To find this parameter, we use the inverting amplifier of Fig. 14, for which ACL0 = R2/R1 = 1V/V, = 1/(1 + R2/R1) = , and fB = ()ft. MC18: With power off, assemble the circuit of Fig.14. Then, while monitoring vS with Ch. 1 of the oscilloscope, adjust the waveform generator so that vS is a square wave alternating between 0 V and +50 mV with initial frequency f 250 kHz. (If you have difficulty adjusting the waveform generator for this small an amplitude, you can interpose a suitable voltage divider between vS and R1). Next, apply power, observe vO with Ch. 2 of the oscilloscope, and find the rise time tR, that is, the amount of time it takes for the output to swing from 10% to 90% of its final value (for best visualization, you may need to vary f up or down from the suggested value.) How does the measured value compare with the expected value tR = 0.35/ft? Comment. S19: Run a PSPice simulation of the circuit of Step MC18 using the 741 macro-model available in PSpices library. Plot the output waveform, and use the cursor to find tR. Hence, compare with your measured value and account for possible differences based also on your conclusions of Step. MC18.

Finding tR:

Finding SR and FPB:

To find these parameters we still use the circuit of Fig. 14, but with a much greater input amplitude. MC20: In the circuit of Fig. 14, adjust the waveform generator so that vS is a square wave now alternating between 0 V and +5 V with initial frequency f 25 kHz. Hence, determine the slopes of the

Fig. 14 Test circuit to find tR, SR, and the FPB.

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two ramps, in V/s. How do they compare with the data-sheet SR value for the 741C? Note: For best visualization of the slopes, you may need to vary the frequency from the suggested initial value of 25 kHz. MC21: Adjust the waveform generator so that vS is now a 1-kHz sine wave alternating between 10 V and +10 V. Then, gradually increase its frequency while observing with the oscilloscope the slope of vO near its zero crossings, where it is steepest. As you increase frequency, slope also increases, until a point is reached beyond which it wont increase any more due to slew-rate limiting, no matter how much you increase frequency. Record the frequency at which the slope just begins to saturate, and compare it with the frequency predicted by Eq. (11). Justify any differences. Note: For best visualization of slope on the screen, you will find it necessary to keep increasing also the horizontal sensitivity of your oscilloscope as you increase frequency and thus slope. For best results, keep adjusting sensitivity so that slope is always in the vicinity of 45 on the screen. MC22: Reduce vS to half its magnitude of Step MC21, and find the new frequency at which the slope of vO just begins to saturate near its zero crossings. Again, compare with Eq. (11), and comment.

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