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    3 The TTL NAND Gate

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    anupamj4u
    The TTL NAND gate uses a multiple emitter transistor structure to implement the NAND logic function. It analyzes the circuit for different input conditions to determine the output state and transistor conduction. For one input low, T1 conducts forward while others are off, giving a high output. For both inputs high, T1 conducts reverse while T2 and T3 conduct forward, giving a low output. It calculates the current drawn and power consumption for each output state.

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    3 The TTL NAND Gate

    Uploaded by

    anupamj4u
    852 views7 pages
    The TTL NAND gate uses a multiple emitter transistor structure to implement the NAND logic function. It analyzes the circuit for different input conditions to determine the output state and transistor conduction. For one input low, T1 conducts forward while others are off, giving a high output. For both inputs high, T1 conducts reverse while T2 and T3 conduct forward, giving a low output. It calculates the current drawn and power consumption for each output state.

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    The TTL NAND gate uses a multiple emitter transistor structure to implement the NAND logic function. It analyzes the circuit for different input conditions to determine the output state and transistor conduction. For one input low, T1 conducts forward while others are off, giving a high output. For both inputs high, T1 conducts reverse while T2 and T3 conduct forward, giving a low output. It calculates the current drawn and power consumption for each output state.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    852 views7 pages

    3 The TTL NAND Gate

    Uploaded by

    anupamj4u
    The TTL NAND gate uses a multiple emitter transistor structure to implement the NAND logic function. It analyzes the circuit for different input conditions to determine the output state and transistor conduction. For one input low, T1 conducts forward while others are off, giving a high output. For both inputs high, T1 conducts reverse while T2 and T3 conduct forward, giving a low output. It calculates the current drawn and power consumption for each output state.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 7

    3 The TTL NAND Gate

    3.1 TTL NAND Gate Circuit Structure

    The circuit structure is identical to the previous TTL inverter circuit except for the multiple emitter input transistor. This is used to implement a diode switching structure in active transistor form using parallel junction diffusions for several emitters.

    Fig. 3.1 Multiple Input Emitter Structure of TTL If any input is low, the corresponding base-emitter junction becomes forward-biased and the transistor conducts. The other characteristics of the circuit and its transfer characteristic are identical to those of the inverter circuit.

    3.2

    Logical Operation

    A table of conduction states can be drawn up showing the state of each transistor in the circuit for all possible input conditions as before to verify the logic function performed. The direction of conduction of T1 can be in the forward or reverse mode so this should also be noted in the table. It can be seen from the table that the output goes LO only when both inputs are HI which verifies the NAND function.

    IN1 LO LO HI HI

    IN2 LO HI LO HI

    T1 ONfor ONfor ONfor ONrev

    T2 OFF OFF OFF ON

    T3 OFF OFF OFF ON

    T4 ON ON ON OFF

    D ON ON ON OFF

    OUPUT HI HI HI LO

    VCC

    R3 R1 1. 6 k RB 4k 130

    N5 N3
    T4

    N1

    N6 N2

    Input 1 Input 2

    T1

    T2
    N4
    R2

    N7 T3

    Output (no load)

    1k

    Fig. 3.2

    Circuit Diagram of a Standard 2-input TTL NAND Gate

    3.3. Circuit Analysis


    It is of interest to examine the conditions for the different logic states of the NAND Gate circuit, particularly with regard to estimating the power consumption in each state. This can be done by first establishing the voltages at each of the nodes N1 N7 in the circuit and then finding the total current drawn from the power supply.

    (a) At Least One Input LO Output HI To aid in the analysis, the NAND Gate circuit can be redrawn with the transistors which are non-conducting or OFF removed from the circuit as shown in Fig. 3.3. Then the potentials, relative to ground, can be determined for each of the nodes in turn. Under this condition, T1 is ON in forward mode, T2 is OFF, T3 is OFF, while T4 is ON at the point of cutin and therefore T2 and T3 have been removed from the circuit.

    VCC IB I1
    R1 RB 4k 1.6k

    I3
    R3 130

    N5 N3 T4 N6

    N1 Input 1 Input 2 0.1 V N2

    T1
    N4
    R2 1k

    N7

    Output (no load)

    Fig. 3.3

    NAND Gate Circuit Redrawn with at least One Input LO

    (i) T1 ON in forward mode and is operating in saturation as there is only a leakage current from T2 available as collector current, i.e. T1 operates with a large base current and negligible collector current where IC MAX = 0. The input logic LO voltage is taken as 0.1V. Then:

    Node N1 : VN1 = Vi + VBE1 SAT = 0.1 + 0.8 = 0.9V


    (ii) With T1 operating in saturation, its collector-emitter voltage is VCE SAT = 0.1V so that:

    Node N2 : VN2 = Vi + VCE1 SAT = 0.1 + 0.1 = 0.2V


    (iii) With T4 operating at the point of cut-in its base current and hence its collector current can be taken as zero. This means that there is no voltage drop across either resistor R1 or R3 and so the potential at both sides of these resistors is equal to the supply voltage VCC giving:

    Node N3, Node N5 : VN3 = VN5 = VCC = 5V


    (iv) Node N4 is pulled low by the resistor R2 which has no current flowing through it so that:

    Node N4 :
    (v)

    VN4 = 0V

    Finally, with T4 operating at the point of cut-in:

    Node N6 : VN6 = VN3 VBE4 CUT-IN = 5 0.6 = 4.4V


    and with the diode at cut-in also:

    Node N7 : VN7 = VN6 VD CUT -IN = 4.4 0.4 = 4.0V

    The current drawn from the supply can then be obtained as:

    IB =

    VCC VN1 5 0.9V = = 1.025mA RB 4k

    with I1 and I3 = 0 since negligible current flows into the base or collector of T4 while at the point of cut-in. The power consumption of the gate with the output in the logic Hi state can then be obtained as:

    POH = VCC x IB = 5V x 1.025mA = 5.125mW

    (b) Both Inputs HI Output LO Under this condition T1 is ON in the reverse mode, T2 is ON, T3 is ON and T4 is OFF. Fig. 3.4 shows the NAND gate circuit redrawn with T4 removed. Potentials must be determined in a different order this time.

    VCC

    I1 IB
    R1 1.6k RB 4k

    I3

    R3 130 N5

    N3 N1 N6 N2 T2 N4
    R2 1k

    Input 1 Input 2

    5V 5V

    T1

    N7 T3

    Output (no load)

    Fig. 3.4

    NAND Gate Circuit Redrawn with Both Inputs HI

    (i) With T3 ON and operating in saturation:

    Node N4 : VN4 = VBE3 SAT = 0.8V


    (ii) With T2 also ON and in saturation:

    Node N2 :

    VN2 = VN4 + VBE2 SAT = 0.8 + 0.8 = 1.6V

    (iii) Since T1 is ON in the reverse mode, the base-collector voltage in this mode can be taken as the same as the base-emitter voltage of a transistor operating in the forward active mode so that:

    Node N1 :

    VN1 = VN2 + VBC1 ON REV = 1.6 + 0.7 = 2.3V

    (iv) With T2 operating in saturation, its collector emitter voltage will be VCE SAT = 0.1V so that:

    Node N3 :

    VN3 = VN4 + VCE2 sat = 0.8 + 0.1 = 0.9V

    (v) With T4 OFF no current will flow through resistor R3 and consequently Node N5 will be pulled up to the supply rail voltage:

    Node N5 :

    VN5 = VCC = 5V

    (vi) With T3 ON and in saturation, its collector-base voltage will be at a saturation value so that the output voltage at Node N7 is simply:

    Node N7 :

    VN7 = VCE3 SAT = 0.1V

    (vii) With T4 and the diode non-conducting, the potential at Node N6 is somewhat ill-defined and depends on the resistances of the nonconducting junctions of these devices but will lie somewhere between that of Nodes N3 and N7, i.e. between 0.1 and 0.9V. However, this voltage is not significant.

    The current drawn from the supply this time is given by the sum of IB and I1 with I3 = 0: Then:

    IB =
    and

    VCC VN1 5 2.3V = = 0.675mA RB 4k

    I1 =

    VCC VN3 5 0.9V = = 2.56mA R1 1.6k

    The power consumption when the output is LO is then given as:

    POL = VCC x (IB + I1 ) = 5 x ( 0.675 + 2.56) = 16.175mW


    If the NAND gate is assumed to spend half of its time in each logic state then the average power consumption can be expressed as:

    PAVE =

    POH + POL 5.125 + 16.175 = = 10.56mW 2 2

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