74ACT323 8-Bit Universal Shift/Storage Register With Synchronous Reset and Common I/O Pins

Revised October 1998
74ACT323
8-Bit Universal Shift/Storage Register with
Synchronous Reset and Common I/O Pins
General Description
Features
The ACT323 is an 8-bit universal shift/storage register with

3-STATE outputs. Parallel load inputs and flip-flop outputs
are multiplexed to minimize pin count. Separate serial
inputs and outputs are provided for Q0 and Q7 to allow
easy cascading. Four operation modes are possible: hold
(store), shift left, shift right and parallel load.
s ICC and IOZ reduced by 50%

s Common parallel I/O for reduced pin count
s Additional serial inputs and outputs for expansion
s Four operating modes: shift left, shift right, load and
store
s 3-STATE outputs for bus-oriented applications
s Outputs source/sink 24 mA
s TTL-compatible inputs
Ordering Code:
Order Number
Package Number
74ACT323PC
N20A
Package Description
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment
for DIP
Pin Descriptions
Pin Name
Description
CP
Clock Pulse Input
DS0
Serial Data Input for Right Shift
DS7
Serial Data Input for Left Shift
S0, S1
Mode Select Inputs
SR
Synchronous Reset Input
OE1, OE2
3-STATE Output Enable Inputs
I/O0I/O7
Multiplexed Parallel Data Inputs or
Q0, Q7
Serial Outputs
3-STATE Parallel Data Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation
DS009787.prf
www.fairchildsemi.com
74ACT323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins
June 1988
74ACT323
Functional Description
other state changes are also initiated by the LOW-to-HIGH
CP transition. Inputs can change when the clock is in either
state provided only that the recommended setup and hold
times, relative to the rising edge of CP, are observed.
The ACT323 contains eight edge-triggered D-type flip-flops

and the interstage logic necessary to perform synchronous
reset, shift left, shift right, parallel load and hold operations.
The type of operation is determined by S0 and S1 as shown
in the Mode Select Table. All flip-flop outputs are brought
out through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q0 and Q7
are also brought out on other pins for expansion in serial
shifting of longer words.
A HIGH signal on either OE1 or OE2 disables the 3-STATE

buffers and puts the I/O pins in the high impedance state.
In this condition the shift, load, hold and reset operations
can still occur. The 3-STATE buffers are also disabled by
HIGH signals on both S0 and S1 in preparation for a parallel load operation.
A LOW signal on SR overrides the Select inputs and allows

the flip-flops to be reset by the next rising edge of CP. All
Mode Select Table

Inputs
SR
S1
Response
S0
CP

X
Synchronous Reset; Q0Q7 = LOW

Parallel Load; I/OnQn
Shift Right; DS0Q0, Q0Q1, etc.
Shift Left; DS7Q7, Q7Q6, etc.
Hold
H = HIGH Voltage Level

L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
74ACT323
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACT323
Absolute Maximum Ratings(Note 1)
Junction Temperature (TJ)

PDIP
0.5V to +7.0V
Supply Voltage (VCC)

DC Input Diode Current (IIK)
VI = 0.5V
Recommended Operating
Conditions
20 mA
VI = VCC + 0.5V
+20 mA
DC Input Voltage (VI)
0.5V to VCC + 0.5V
Supply Voltage (VCC)
VO = 0.5V
VO = VCC + 0.5V
+20 mA
0V to VCC
Output Voltage (VO)
20 mA
0V to VCC
40C to +85C
Operating Temperature (TA)
0.5V to V CC + 0.5V
Minimum Input Edge Rate (V/t)

VIN from 0.8V to 2.0V
DC Output Source or
50 mA
Sink Current (IO)
VCC @ 4.5V, 5.5V
50 mA
Per Output Pin (ICC or IGND)
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC VCC or Ground Current

Storage Temperature (TSTG)
4.5V to 5.5V
Input Voltage (VI)
DC Output Diode Current (IOK)
DC Output Voltage (VO)
140C
65C to +150C
DC Electrical Characteristics
Symbol
Parameter
TA = +25C
VCC
(V)
VIH
Typ
TA = 40C to +85C
Minimum High Level
4.5
1.5
2.0
2.0
Input Voltage
VIL
5.5
1.5
2.0
2.0
Maximum Low Level
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
Minimum High Level
4.5
4.49
4.4
4.4
5.5
5.49
5.4
Conditions
3.76
VOUT = 0.1V
or VCC 0.1V
VOUT = 0.1V
5.4
3.86
0.8
Output Voltage
VOH
Units
Guaranteed Limits
or VCC 0.1V
V
IOUT = 50 A
IOH = 24 mA
IOUT = 50 A
IOL = 24 mA
VIN = VIL or VIH

4.5
5.5
4.86
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
4.5
0.36
0.44
IOH = 24 mA (Note 2)
4.76
Maximum Low Level

Output Voltage
VOL
VIN = VIL or VIH

IOL = 24 mA (Note 2)
5.5
IIN
Maximum Input
0.36
0.44
5.5
0.1
1.0
VI = VCC, GND
5.5
0.3
3.0
VI/O = VCC or GND
1.5
mA
VI = VCC 2.1V
VOLD = 1.65V Max
Leakage Current
IOZT
Maximum I/O
VIN = VIH, VIL
Leakage Current
ICCT
Maximum ICC/Input
5.5
0.6
IOLD
Minimum Dynamic
5.5
75
mA
IOHD
Output Current (Note 3)
5.5
75
mA
VOHD = 3.85V Min
ICC
Maximum Quiescent
5.5
40.0
VIN = VCC or GND
4.0
Supply Current
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
VCC
Symbol
TA = 25C
(V)
Parameter
CL = 50 pF
(Note 4)
Min
TA = 40C to +85C
CL = 50 pF
Typ
Max
Min
Units
Max
fmax
Maximum Input Frequency
5.0
120
125
tPLH
Propagation Delay
5.0
5.0
9.0
12.5
4.0
110
14.0
MHz
ns
5.0
5.0
9.0
13.5
4.5
15.0
ns
5.0
5.0
8.5
12.5
4.5
14.5
ns
5.0
6.0
10.0
14.5
5.0
16.0
ns
CP to Q0 or Q7
tPHL
Propagation Delay
CP to Q0 or Q7
tPLH
Propagation Delay
CP to I/On
tPHL
Propagation Delay
CP to I/On
tPZH
Output Enable Time
5.0
3.5
7.5
11.0
3.0
12.5
ns
tPZL
Output Enable Time
5.0
3.5
7.5
11.5
3.0
13.0
ns
tPHZ
Output Disable Time
5.0
4.0
8.5
12.5
3.0
13.5
ns
tPLZ
Output Disable Time
5.0
3.0
8.0
11.5
2.5
12.5
ns
Note 4: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
TA = 25C
Parameter
TA = 40C to +85C
VCC
CL = 50 pF
CL = 50 pF
(V)
Symbol
VCC = +5.0V
VCC = +5.0V
Units
(Note 5)
tS
Typ
5.0
2.0
5.0
5.0
ns
5.0
1.5
1.5
ns
5.0
1.0
4.0
4.5
ns
5.0
1.0
1.0
ns
5.0
1.0
2.5
2.5
ns
5.0
1.0
1.0
ns
5.0
Setup Time, HIGH or LOW
Guaranteed Minimum
2.0
4.0
4.5
ns
S0 or S1 to CP
tH
Hold Time, HIGH or LOW

S0 or S1 to CP
tS

I/On, DS0, DS7 to CP
tH

I/On, DS0, DS 7 to CP
tS

SR to CP
tH

SR to CP
tW
CP Pulse Width
HIGH or LOW
Note 5: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Typ
Units
CIN
Symbol
Input Capacitance
Parameter
4.5
pF
VCC = OPEN
CPD
Power Dissipation Capacitance
170
pF
VCC = 5.0V
Conditions
74ACT323
AC Electrical Characteristics
74ACT323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N20A
LIFE SUPPORT POLICY

FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
This datasheet has been download from:

www.datasheetcatalog.com
Datasheets for electronics components.

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Revised October 1998

The ACT323 is an 8-bit universal shift/storage register with

s ICC and IOZ reduced by 50%

Clock Pulse Input

Serial Data Input for Right Shift

Serial Data Input for Left Shift

Mode Select Inputs

Synchronous Reset Input

3-STATE Output Enable Inputs

Multiplexed Parallel Data Inputs or

3-STATE Parallel Data Outputs

FACT is a trademark of Fairchild Semiconductor Corporation.

1999 Fairchild Semiconductor Corporation

The ACT323 contains eight edge-triggered D-type flip-flops

A HIGH signal on either OE1 or OE2 disables the 3-STATE

A LOW signal on SR overrides the Select inputs and allows

Mode Select Table

Synchronous Reset; Q0Q7 = LOW

H = HIGH Voltage Level

Absolute Maximum Ratings(Note 1)

Junction Temperature (TJ)

Supply Voltage (VCC)

DC Input Voltage (VI)

0.5V to VCC + 0.5V

Supply Voltage (VCC)

Output Voltage (VO)

Operating Temperature (TA)

Minimum Input Edge Rate (V/t)

Sink Current (IO)

VCC @ 4.5V, 5.5V

Per Output Pin (ICC or IGND)

DC VCC or Ground Current

Input Voltage (VI)

DC Output Diode Current (IOK)

DC Output Voltage (VO)

Minimum High Level

Maximum Low Level

Minimum High Level

VIN = VIL or VIH

Maximum Low Level

VIN = VIL or VIH

VI/O = VCC or GND

VIN = VIH, VIL

Output Current (Note 3)

VOHD = 3.85V Min

VIN = VCC or GND

Maximum Input Frequency

Output Enable Time

Output Enable Time

Output Disable Time

Output Disable Time

Note 4: Voltage Range 5.0 is 5.0V 0.5V

Setup Time, HIGH or LOW

Hold Time, HIGH or LOW

Setup Time, HIGH or LOW

Hold Time, HIGH or LOW

Setup Time, HIGH or LOW

Hold Time, HIGH or LOW