The MOS Capacitor: N Polysilicon Gate Gate Oxide 3.9 0

The MOS Capacitor
M
O
S
n+ polysilicon gate
gate oxide
ox = 3.9 o
0
p-type
s = 11.7 o
Oxide = SiO2 ... a near-perfect insulator. We assume zero charge in the oxide for
this course --> electric field is constant and potential is linear in the oxide.
n+ polysilicon has a potential which is the maximum possible in silicon:
n+ = 550 mV
p-type substrate has potential which is p = - 60 mV log (Na / 1010)
Strategy: same as pn junction electrostatics

rst thermal equilibrium, then
with an applied bias voltage
EE 105 Spring 1997

Lecture 9
Qualitative Charge Distribution

in Thermal Equilibrium
Where to start: potential in n+ polysilicon is known; potential in p-type

substrate is known, too ... need + charge on gate, - charge in substrate -->
since the silicon is p-type, this means that a depletion region forms under the
gate

,,

,,,,,,
,,,,,,
metal
interconnect to gate
n+ polysilicon gate
Vox,o +
_
VBo
_
gate charge, QGo
+++++++++++++++++++
gate oxide
depletion region with
Xdo bulk charge QBo

p-type substrate
x
,,,,,,,,,,
,,,,,,,,,,
metal interconnect to bulk
EE 105 Spring 1997

Lecture 9
Thermal Equilibrium MOS Electrostatics
Sketch charge density, electric eld, and potential in equilibrium
o(x)
charge
density
0
-tox
Eo(x)
electric
field
-tox
o(x)
n+
potential
-tox
EE 105 Spring 1997

Lecture 9
MOS Capacitor under Applied Bias
Oxide doesnt permit any steady-state current between the n+ poly gate and the
substrate. Therefore, if we wait long enough for transient currents to die out, the
electron and hole currents are zero -Jn = 0
and
Jp = 0
Even though the structure isnt in equilibrium, the absence of current implies
that we can relate potential to carrier concentration in the silicon substrate (since
thats all we assumed in deriving the 60 mV rule.)

,,
,,,,,
,,,,,
metal
interconnect to gate
+
_ mn+
gate oxide
ox = 3.9 o
n+ polysilicon gate
+
_
VGB
+V
_ ox
0 +
_VB
,,,,,,,,,
,,,,,,,,,
p-type
s = 11.7 o
+ pm
_
metal interconnect to bulk
Flatband condition: cancel built-in drop by applying the atband voltage

V GB = ( n+ p ) = V FB = 970 mV for Na = 1017 cm-3
EE 105 Spring 1997

Lecture 9
MOS Electrostatics in Flatband
When VGB = VFB, the gate is shifted from its thermal equilibrium potential (n+)
to a new value of VFB + n+ = -(n+ - p) + n+ = p, which is the same potential
as the p-type bulk. Therefore, there is no potential drop across the MOS structure
in flatband
(x)
charge
density
-tox
E(x)
electric
eld
-tox
x
(x)
250mV
potential
-tox
-250mV
VGB + n+
-500mV
-750mV
-1.0V
If we continue to make the gate-bulk voltage more negative, the gate will take on
a negative charge QG < 0. The substrate has a positive charge, which comes from
holes that are attracted by the negative gate charge
EE 105 Spring 1997

Lecture 9
MOS Capacitor in Accumulation
Charge density, electric eld, and potential in accumulation:

VGB < VFB, where VFB = - 0.97 V for this example.
(x)
- QG (accumulated holes)
charge
density
-tox
0
QG
E(x)
-tox
electric
field
x
+
QG
Eox =
ox
(x)
-tox
potential
0
x
-250mV
VGB + n+
VGB - VFB
-500mV
-750mV
-1.0V
-1.25V
EE 105 Spring 1997

Lecture 9
MOS Capacitor in Depletion
Now we make VGB > VFB. Note that thermal equilibrium falls into this range of
applied bias.
(x)
QG
charge
density
Xd
0
-tox
-qNa
E (x)
electric
eld
0
-tox
Xd
(x)
1V
VGB + n+
potential
VGB
500 mV
-tox
s = 185 mV
Xd
x
-500 mV
Surface potential at oxide/silicon interface is now positive --> n-type

(slightly, ns = 1013 cm-3).
EE 105 Spring 1997

Lecture 9
The Threshold Voltage VTn
Keep increasing VGB --> surface potential keeps increasing. At some point, the
surface is n-type (i.e., we say that it is inverted) and the electron charge makes a
signicant contribution to the charge density.
How do we model this phenomenon? We approximate that onset of inversion as
the point where the electron concentration ns at the surface is the same as the
hole concentration Na in the bulk. (In other words, the surface is as n-type as
the bulk is p-type.)
The gate-bulk potential at the onset of inversion is called the threshold voltage,
VTn. To nd the threshold voltage, we need to consider the electrostatics in
depletion (no electrons at the surface at the onset of inversion) -- with the surface
potential equal to the opposite of the bulk potential:
s, max = p
(x)
1.5 V
VTn + n+
1V
s,max = - p = 420 mV
Vox
500 mV
VTn - VFB
Xd,max
-tox
0
-500 mV
VB,max
- p
EE 105 Spring 1997

Lecture 9
Threshold Voltage Expression
We can solve for the threshold voltage:

V T V FB = V ox + V B, max
The drop across the depletion region is

V B, max = s, max p = p p = 2 p
The drop across the oxide for VGB = VTn is

Q B, max
Q B, max
V ox = E ox t ox = ---------------------- t ox = ---------------------C ox
ox
The bulk charge in inversion is found from the depletion width Xd,max
2 p
Q B, max = qN a X d, max = qN a --------------------------------------- = 2q s N a ( 2 p )
( ( 1 2 )qN a ) s
where the relationship between the depletion width Xd,max and the drop across
the depletion region s,max - (p) = -p - p = -2p can be found from Poissons
Equation.
EE 105 Spring 1997

Lecture 9
Threshold Voltage (p-type Substrate)
The threshold voltage is the sum of the atband voltage (which cancels the builtin potential drop from gate to bulk), the drop across the oxide at the onset of
inversion, and the maximum potential drop across the depletion region
1
V Tn = V FB 2 p + --------- 2q s N ( 2 p )
a
C
ox
EE 105 Spring 1997

Lecture 9

The MOS Capacitor: N Polysilicon Gate Gate Oxide 3.9 0

Uploaded by

Copyright:

Available Formats

The MOS Capacitor: N Polysilicon Gate Gate Oxide 3.9 0

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

The MOS Capacitor: N Polysilicon Gate Gate Oxide 3.9 0

Uploaded by

Copyright:

Available Formats

The MOS Capacitor

Strategy: same as pn junction electrostatics

EE 105 Spring 1997

Qualitative Charge Distribution

Where to start: potential in n+ polysilicon is known; potential in p-type

gate charge, QGo

depletion region with

Xdo bulk charge QBo

EE 105 Spring 1997

Thermal Equilibrium MOS Electrostatics

Sketch charge density, electric eld, and potential in equilibrium

EE 105 Spring 1997

MOS Capacitor under Applied Bias

metal interconnect to bulk

Flatband condition: cancel built-in drop by applying the atband voltage

EE 105 Spring 1997

MOS Electrostatics in Flatband

EE 105 Spring 1997

MOS Capacitor in Accumulation

Charge density, electric eld, and potential in accumulation:

EE 105 Spring 1997

MOS Capacitor in Depletion

Surface potential at oxide/silicon interface is now positive --> n-type

EE 105 Spring 1997

The Threshold Voltage VTn

EE 105 Spring 1997

Threshold Voltage Expression

We can solve for the threshold voltage:

The drop across the depletion region is

The drop across the oxide for VGB = VTn is

EE 105 Spring 1997

Threshold Voltage (p-type Substrate)

EE 105 Spring 1997

You might also like