ARUSlecture7 fm5-1 PDF
ARUSlecture7 fm5-1 PDF
ARUSlecture7 fm5-1 PDF
Oxide doesnt permit any steady-state current between the n+ poly gate and the
substrate. Therefore, if we wait long enough for transient currents to die out, the
electron and hole currents are zero -Jn = 0
and
Jp = 0
Even though the structure isnt in equilibrium, the absence of current implies
that we can relate potential to carrier concentration in the silicon substrate (since
thats all we assumed in deriving the 60 mV rule.)
,,
,,,,,
,,,,,
metal
interconnect to gate
+
_ mn+
gate oxide
ox = 3.9 o
n+ polysilicon gate
+
_
VGB
+V
_ ox
0 +
_VB
,,,,,,,,,
,,,,,,,,,
p-type
s = 11.7 o
+ pm
_
When VGB = VFB, the gate is shifted from its thermal equilibrium potential (n+)
to a new value of VFB + n+ = -(n+ - p) + n+ = p, which is the same potential
as the p-type bulk. Therefore, there is no potential drop across the MOS structure
in flatband
(x)
charge
density
-tox
E(x)
electric
field
-tox
x
(x)
250mV
potential
-tox
-250mV
VGB + n+
-500mV
-750mV
-1.0V
If we continue to make the gate-bulk voltage more negative, the gate will take on
a negative charge QG < 0. The substrate has a positive charge, which comes from
holes that are attracted by the negative gate charge
(x)
- QG (accumulated holes)
charge
density
-tox
0
QG
E(x)
-tox
electric
field
x
+
QG
Eox =
ox
(x)
-tox
potential
0
x
-250mV
VGB + n+
VGB - VFB
-500mV
-750mV
-1.0V
-1.25V
Now we make VGB > VFB. Note that thermal equilibrium falls into this range of
applied bias.
(x)
QG
charge
density
Xd
0
-tox
-qNa
E (x)
electric
field
0
-tox
Xd
(x)
1V
VGB + n+
potential
VGB
500 mV
-tox
s = 185 mV
Xd
x
-500 mV
Keep increasing VGB --> surface potential keeps increasing. At some point, the
surface is n-type (i.e., we say that it is inverted) and the electron charge makes a
significant contribution to the charge density.
How do we model this phenomenon? We approximate that onset of inversion as
the point where the electron concentration ns at the surface is the same as the
hole concentration Na in the bulk. (In other words, the surface is as n-type as
the bulk is p-type.)
The gate-bulk potential at the onset of inversion is called the threshold voltage,
VTn. To find the threshold voltage, we need to consider the electrostatics in
depletion (no electrons at the surface at the onset of inversion) -- with the surface
potential equal to the opposite of the bulk potential:
s, max = p
(x)
1.5 V
VTn + n+
1V
s,max = - p = 420 mV
Vox
500 mV
VTn - VFB
Xd,max
-tox
0
-500 mV
VB,max
- p
The bulk charge in inversion is found from the depletion width Xd,max
2 p
Q B, max = qN a X d, max = qN a --------------------------------------- = 2q s N a ( 2 p )
( ( 1 2 )qN a ) s
where the relationship between the depletion width Xd,max and the drop across
the depletion region s,max - (p) = -p - p = -2p can be found from Poissons
Equation.
The threshold voltage is the sum of the flatband voltage (which cancels the builtin potential drop from gate to bulk), the drop across the oxide at the onset of
inversion, and the maximum potential drop across the depletion region
1
V Tn = V FB 2 p + --------- 2q s N ( 2 p )
a
C
ox
(x)
1.5 V
1.0 V
Vox
500 mV
- tox
VGB - VFB
s,max = 420 mV
Xd,max
2 p
- 500 mV
Depletion:
Inversion:
QG
on
rsi
e
inv
letio
dep
1
ati
ul
VFB = 0.97 V
QB,max
QB(VGB)
0
on
QN(VGB)
VGB (V)
VTn = 0.6 V
cu
ac
MOS Capacitance
qG
rs
ve
in
letio
dep
QB,max
qB(vGB)
1
on
ati
ul
vGB (V)
VGB (V)
VTn = 0.6 V
VFB = 0.97 V
um
qN(vGB)
cc
(a)
C/Cox
accumulation
inversion
1.0
0.8
ple
de
0.6
n
tio
0.4
VFB = 0.97 V
2
0.2
VTn = 0.6 V
1
1
0
(b)
ox
C ox = -------t ox
s
C b = -----Xd
Note that Xd is
a function of VGB
C = C ox C b
Step 1: identify the flatband voltage from the gate and bulk potentials in
equilibrium
Why? positive charge on gate ( since VGB - VFB > 0 V) must be mirrored by a
negative charge in the substrate.
n-type substrate: negatively charged electrons are accumulated under the gate
p-type substrate: negatively charged ionized acceptors are left, after holes are
repelled away from positive charge on gate
Step 3: construct C(VGB) plot, using the knowledge that the substrate is depleted
on the other side of VFB from accumulation in Step 2 and that inversion occurs
after depletion. Calculation of VT and Cmin is necessary to quantify the plot
Example:
gate: p+ polysilicon (where p+ = - 550 mV); gate oxide thickness = 200 ,
substrate: n type silicon, n = 480 mV (Nd = 1018 cm-3)
VFB = - (-550 mV - 480 mV) = + 1.03 V
VGB - VFB > 0 V --> accumulated; substrate is depleted for VGB < 1.03 V
Check: VGB = 0 --> negative charge on gate; positive in bulk (since gate is at
- 0.55 V and substrate is at + 0.48 V in thermal equilibrium) --> positive donors in
depletion region under gate ... and possibly holes due to inversion
6
2 10
2.9 10
t ox X d, max
Maximum capacitance is Cox = 1.72 fF/cm2.
C/Cox
1
0.75
1.16/1.72 = 0.67
0.5
0.25
1.03 V
-3.21 V
0
-4
-3
-2
-1
VGB