Fin FEt

Seminar Report2009-2010 FinFET
INTRODUCTION
Since the fabrication of MOSFET, the minimum channel length has been
shrinking continuously. The motivation behind this decrease has been an increasing interest
in high speed devices and in very large scale integrated circuits. The sustained scaling
of conventional bulk device reuires innovations to circumvent the
barriers of fundamental ph!sics constraining the conventional
"#SFET device structure$ The limits most often cited are control of the
densit! and location of dopants providing high % on &% o' ratio and (nite
subthreshold slope and uantum-mechanical tunneling of carriers
through thin gate from drain to source and from drain to bod!$ The
channel depletion )idth must scale )ith the channel length to contain
the o'-state leakage % o'$ This leads to high doping concentration* )hich
degrade the carrier mobilit! and causes +unction edge leakage due to
tunneling$ Furthermore* the dopant pro(le control* in terms of depth and
steepness* becomes much more di,cult$ The gate o-ide thickness to-
must also scale )ith the channel length to maintain gate control* proper
threshold voltage .
T
and performance$ The thinning of the gate dielectric
results in gate tunneling leakage* degrading the circuit performance*
po)er and noise margin$
/lternative device structures based on silicon-on-insulator
(SOI) technolog! have emerged as an e'ective means of e-tending
"#S scaling be!ond bulk limits for mainstream high-performance or lo)-
po)er applications $Partially depleted (PD) SOI )as the (rst S#%
technolog! introduced for high-performance microprocessor
applications$ The ultra-thin-body fully depleted (FD) SOI and the
0ept$ of Electronics$
"$E$S$1ollege*"arampall!
1
non-planar FinFET device structures promise to be the potential
2future3 technolog!&device choices$
%n these device structures* the short-channel e'ect is controlled
b! geometr!* and the o'-state leakage is limited b! the thin Si (lm$ For
e'ective suppression of the o'-state leakage* the thickness of the Si (lm
must be less than one uarter of the channel length$
The desired .T is achieved b! manipulating the gate )ork function*
such as the use of midgap material or pol!-Si4e$ 1oncurrentl!* material
enhancements* such as the use of a5 high-k gate material and b5
strained Si channel for mobilit! and current drive improvement* have
been activel! pursued$
/s scaling approaches multiple ph!sical limits and as ne) device
structures and materials are introduced* uniue and ne) circuit design
issues continue to be presented$ %n this article* )e revie) the design
challenges of these emerging technologies )ith particular emphasis on
the implications and impacts of individual device scaling elements and
uniue device structures on the circuit design$ 6e focus on the planar
device structures* from continuous scaling of 70 S#% to F0 S#%* and ne)
materials such as strained-Si channel and high-k gate dielectric$

PARTIA! DEPETED "PD# SOI
The 70 8oating-bod! "#SFET )as the (rst S#% transistor
genericall! adopted for high-performance applications* primaril! due to
device and processing similarities to bulk 1"#S device$
The 70 S#% device is largel! identical to the bulk device* e-cept for
the addition of a buried o-ide 92:#;35 la!er$ The active Si (lm thickness
is larger than the channel depletion )idth* thus leaving a uasi-neutral
28oating3 bod! region underneath the channel$ The . T of the device is
completel! decoupled from the Si (lm thickness* and the doping pro(les
can be tailored for an! desired .T $

!
The device o'ers several advantages for performance& po)er
improvement<
15 reduced +unction capacitance*
25 lo)er average threshold due to positive . :S during s)itching$
=5 d!namic loading e'ects*in )hich the load device tends to be in
high .
T
state during
s)itching
The performance comes at the cost of some design comple-it!
resulting from the 8oating bod! of the device* such as
15 parasitic bipolar e'ect and
25 h!steretic .T variation$
Parasitic $ipolar E%ect
%n 70S#% an n-p-n transistor is formed )ith source and drain as
emitter > collector respectivel! and bod! as the base$ The topolog!
t!picall! involves an 2o'3 transistor )ith the source and drain voltage
set up in the 2high3 state 9hence bod! voltage at2high35 6hen the
source is subseuentl! pulled do)n* large overdrive is developed across
the bod!-source +unction* causing bipolar current to 8o) through the
lateral parasitic bipolar transistor$This ma! result in circuit failure$

"
%n SR/" bitline structures* the aggregate parasitic
bipolar e'ect of the unselected cells on the selected bitline disturbs the
read&)rite operations and limits the number of cells that can be
attached to a bitline pair
Hysteretic V T Variation
The h!steretic .T variation due to long time constants of
various
bod! charging&discharging mechanisms$
/ commonl! used gauge for h!steretic .T variation 9or
2histor! e'ect3 as it is kno)n in the S#% communit!5 is the disparit! in
the bod! voltages and dela!s bet)een the so-called 2(rst s)itch3 and
2second s)itch3 $ The 2(rst s)itch3 refers to the case )here a circuit
9e$g$* inverter5 starts in an initial uiescent state )ith input 2lo)3 and
then undergoes an input-rising transition$ %n this case* the initial dc
euilibrium bod! potential of the s)itching n"#SFET is determined
primaril! b! the balance of the back-to-back drain-to-bod! and bod!-to-
source diodes$ The 2second s)itch3 refers to the case )here the circuit
is initiall! in a uiescent state )ith input 2high$3 The input (rst falls and
then rises 9hence* the name 2second s)itch35$ For this case* the
pres)itch bod! voltage is determined b! capacitive coupling bet)een
the drain and the bod!$
#
$nput%output &aveforms'nMOS body voltage for a () SO$ *MOS inverter under +first s&itch, ' +second
s&itch, condition is sho&n above
The dut! c!cle* sle) rate* and output load also a'ect the
h!steretic behavior of the circuits$ / higher dut! c!cle increases
h!steretic behavior due to higher s)itching activit! causing a gain or
loss of bod! charge and less time for the
device to return&settle to its initial euilibrium state
S&AI'( Si FI)* FRO) PD SOI TO FD SOI
The ma+or bene(ts of scaling&thinning of the Si (lm are< 15
reduction of +unction capacitance for performance improvement* 25
better short channel roll-o'* and =5 better soft error rate 9SER5 due to
less charge generation and collection volume$
%n addition* the histor! e'ect 9disparit! bet)een (rst s)itch and
second s)itch5 is also reduced$ The reduced +unction capacitance
improves dela!s of both the (rst and second s)itches$ ?o)ever* for the
second s)itch the reduced +unction capacitance reduces the capacitive
coupling bet)een the drain and the bod! $The resulting decrease in the
pre-s)itch bod! voltage for the second s)itch partiall! o'sets the
performance improvement$
@nfortunatel!* the thinning of Si (lm degrades the bod!
resistance* rendering bod! contacts less e'ective and eventuall! useless
$Self-heating becomes more severe$ Furthermore* as the (lm thickness is
scaled belo) A0nm*the device ma! become d!namicall! full! depleted
9or uasi-depleted5Bthe bod! )ould become full! depleted under certain
bias conditions or during certain circuit-s)itching transients$ This
necessitates a uni(ed 70CF0 device model )ith smooth and seamless
-
transitions among di'erent modes of operation$ T!picall!* this is
modeled b! var!ing the built-in potential bet)een the bod! and source
+unction* thus changing the amount of bod! charges the bod!-to-source
+unction diode can sink for a given change in the bod! potential $The
presence of d!namic full depletion also complicates the static timing
methodolog!$ The various bod! voltage bounds* established based on
the assumption of partial depletion need to be e-tended to cover this
ne) phenomenon$ Dotice that d!namic depletion tends to occur (rst in
long-channel* lo) .
T
devices$ For short channel devices* the pro-imit!
of the heavil! doped 2halo3 regions to each other increases the e'ective
bod! doping* and the device is less likel! to be d!namicall! full!
depleted$ %n a F0ES#% device* the channel depletion la!er e-tends
through the entire Si (lm$ This signi(cantl! reduces the 8oating bod!
e'ect 9completel! eliminating the 8oating-bod! e'ect )ith ultra-thin Si
(lms5$ / raised source&drain structure is t!picall! emplo!ed to overcome
the large source&drain series resistance of the thin Si (lm$ There are t)o
approaches to achieve the desired .T$ #ne can use the traditional dual
7F&DF pol!-silicon )ith a highl! doped channel$ This approach has
several dra)backs and limitations< a5 .
T
)ould be sensitive to Si (lm
thickness variation* b5 high doping degrades the carrier mobilit! and
results in +unction edge leakage due to tunneling* and c5 in devices )ith
ultra-thin bod!* the amount of dopant reuired for the desired .T can not
be realisticall! achieved$ E-cessivel! high bod! doping )ould turn the
device into a 2resistor3 rather than a 2transistor$3 1onseuentl!* the
preferred and more scalable approach is to build an 2undoped3 channel
)ith the desired .T set either b! the source&drain halo or b! the use of
midgap gate materials$ The use of undoped channel a5 reduces the .T
sensitivit! to Si (lm thickness variation* b5 reduces dopant fluctuation effect, c.
reduces transverse electric (eld and impurit! scattering* leading to higher
/
mobilit!* and d5 reduces band-to-band tunneling leakage at the +unction
edge+

The use of midgap gate materials ma! allo) the use of a single
electrode for both n"#SFETs and p"#SFETs$
/s the Si (lm thickness is reduced* the gate has more control of
the channel charges* and the subthreshold slope improves$ The channel
leakage in the device is limited b! the Si (lm thickness and decreases as
the (lm thickness is reduced$ The fringing electric (eld from source&drain
penetrates into the buried o-ide underneath the channel* )hich causes
back interface virtual biasing* resulting in increased %
o'
and degraded
subthreshold slope$ This can be suppressed b! thinning the buried o-ide
at the e-pense of larger +unction capacitance to the substrate$ The F0 S#%
technolog! is * in general* uite 2transparent3 for design migration and
the challenge is primaril! in technolog! development and manufacturing$
)A,OR DESI(' ISS-ES
(ate O.ide Tunnelin/ ea0a/e
/s the gate o-ide thickness is scaled to maintain gate control .
T
and
performance*
gate insulator direct tunneling leakage increases$ Ditrided o-ide* )hich
reduces the leakage b! an! order of magnitude * has been )idel! used in
0
the industr! to contain this leakage$ Devertheless* the o-ide tunneling
leakage increases b! 2 AG for ever! 0$1 nm decrease in o-ide thickness$
This amounts to over a =0G increase per technolog! generation$ #n the
contrar!* the channel leakage increases b! about =-A per technolog!
generation$ /s such * the o-ide tunneling leakage has uickl! approached
%
o'
and )ill surpass %
o'
at room temperature for o-ide thickness around
1$0nm or belo) * thus becoming a serious concern for overall chip
leakage$
Furthermore* at 1$0nm* the tunneling leaking for nitrided o-ide
reaches 100/&cm
2
*
)hile the traditional reliabilit! limitation for silicon dio-ide gate insulator
leakage is 1$0/&cm
2
$/ recent stud! sho)ed that* at 100 /&cm
2
* static
1"#S and domino circuits in bulk 1"#S still e-hibit 2acceptable
functionalit! and noise margin3$
The o-ide tunneling current consists of several components$ The electron tunneling
from the valence band 9E.:5 generates the substrate current in both
n"#S and p"#S $This substrate current component is signi(cantl! less
than the tunneling current bet)een the gate and the channel* and its
e'ect can usuall! be neglected in bulk 1"#S $%n 70 S#% devices* ho)ever*
this substrate current charges or discharges the bod!* thus changing .
T
and a'ecting circuit operation$ /s this gate-to-bod! tunneling current has
a )eaker temperature dependence than the channel current* and other
leakage and bod! charging&discharging current components* its e'ect is
more pronounced at lo)er temperature$
The detailed study on a !"1kb 21 directory S34M sho&ed that the presence of in
the gate1to1body tunneling current resulted in much more significant degradation +&rite,
operation compared &ith the +read, operation. On the other hand , the initial cycle parasitic
bipolar disturb resulting from the aggregate e'ect of unselected cells in
the same bitline )as reduced$
5
The gate-to-bod! tunneling current increases the disparit!
bet)een the (rst s)itch and the second s)itch$
%n F0 S#% and FinFET )ith ultra-thin bod!* the gate tunneling
leakage is significantly reduced. This is because 1. in these, an undoped or very lightly
doped body 6channel. is used and the depletion charges essentiall! eual to
Hero* thus reducing the vertical electric (eld in the channel* and 25 the
uantum con(nement e'ect in ultra-thin Si (lm results in a broader
inversion charge distribution and lo)er vertical electric (eld at the
bottom of the inversion la!er$ 1onseuentl!* the gate tunneling leakage is
reduced b! about =-I;$%f a high-k gate dielectric such as ?f#
2
*the
reduction in gate current can e-ceed an order of magnitude as the
increased ph!sical thickness of the gate dielectric barrier makes the
tunneling current more dependent upon the shape
of the potential )ell in Si$ %n general* scaling of the bod! thickness
reduces the gate leakage current because the potential )ell becomes
shallo)er$ ?o)ever* e-cessive scalingJthinning of bod! thickness
belo)KAnm increases con(nement of carriers to)ard the gate dielectric
interface* and the gate current increases to approach that of the bulk
devices$ This ma! not be of concern since Anm is close to the practical
limit of bod! thickness in actual device technologies$
Self heatin/
The heat transfer is dominated b! phonon transport in
semiconductors and b! electron transport in metals$ The thermal
conductivit! of the buried o-ide 91$I 6&m-$15 is about t)o orders of
magnitude lo)er than that of Si 9120 6&m-$15* giving rise to local self-
heating in S#% devices$ This is particularl! a concern for devices that are
2on3 most or all the time 9e$g$* biasing elements* current source* current
mirror* bleeder* etc$5 and for circuits )ith high dut! c!cle and slo) sle)
rate 9such as clock distribution* %&# driver5$
17
Scaling of the Si (lm degrades the thermal conductivit! and
increases the thermal resistance$ %n scaled S#% devices* both the
channel length and Si (lm thickness are much smaller than the phonon
mean free path for Si 9K=00 nm at room temperature5* and the thermal
conductivit! is severel! degraded due to phonon boundar! scattering$
The thermal resistance increase is particularl! signi(cant for
thinner Si (lm )ith thick buried o-ide$ /s the Si (lm thickness is scaled
further to approach the 7honon )avelength 9K tens of nm5* the phonon
con(nement e'ect becomes signi(cant$ This is the mechanical&thermal
analog! of the uantum con(nement e'ect in electronic devices )ith an
ultra-thin Si (lm$ The boundar! conditions change from the usual
periodic boundar! conditions for bulk materials to essentiall! Hero
displacements on the boundaries in S#%$
Soft Error Rate
The L-generated charges in S#% devices are substantiall! less
than in bulk devices due to the presence of the buried o-ide* and
appreciable charge generation can onl! occur )hen an L-particle hits
the channel region$ 6hile scaling of the device reduces the charge
generation volume* the M
crit
also decreases due to a lo)er capacitance at
the cellNs storage node and scaled .
00
$
%n a 70 S#% device* the total charges accumulated at the cell
storage node can be significantl! higher than the L-generated charges
due to the parasitic bipolar e'ect$ For properl! scaled 70 S#% devices*
the parasitic bipolar gain is reduced* and the resulting overall single-
event-upset-induced failure rate is less than that of bulk silicon$
Furthermore* scaling&thinning of the Si (lm reduces the charge
generation volume and the base-emitter 9bod!-source5 +unction area of
the parasitic bipolar transistor* thus improving SER as )ell$
Strained-Si channel And 1i/h-0 (ate
11
Strained-Si surface channel 1"#S has recentl! emerged as
an e'ective means of e-tending scaling for future high-performance
applications due to higher mobilit! and improved %
on
$ The lattice
mismatch bet)een the Si channel and the underl!ing rela-ed Si4e la!er
results in bia-ial tensile strain* )hich reduces the intervalle! scattering
b! increasing sub-band splitting and enhances carrier transport b!
reducing conductivit! e'ective mass$
1ombining strained si-channel and S#% complements the
improved %
on
of strained Si channel device )ith the bene(t of S#%$
?o)ever* there are numerous design implications$ The narro)er
bandgap of the Si4e la!er causes a heterostructural band o'set* )hich
reduces .
T
and increases %
o'
$ The mobilit! enhancement for n"#S and
p"#S ma! be uite di'erent due to device design and process
integration constraints* )hich ma! upset the established O9p&n strength5
ratio of e-isting designs$ The tensile strain is 2bia-ial3* so mobilit!
enhancements 9therefore %
on
improvement5 are the same along ;- and P-
a-is$ ?o)ever* in some high-densit! design 9eg< SR/" cell5* 2bent gates3
at a IAQ angle are sometimes used* )hich )ould result in disparit! in
mobilit! enhancement and %
on
improvement$ The Si4e la!er )ith 20R 4e
has a S0R higher dielectric constant and a 10R lo)er built-in potential
due the narro)er band gap* resulting in higher +unction capacitance$
Furthermore* higher bod! doping densit! could be needed to
compensate for the .
T
reduction )hich further increases the +unction
capacitance$ The thermal conductivit! of the Si4e la!er is about 1A;
lo)er than that for Si thus aggravating the self-heating e'ect$
The presence of the Si4e la!er also signi(cantl! a'ects the
8oating-bod! e'ect$ For 20R 4e content* the band gap is about 90R of
that of Si$ This narro)er bandgap results in higher 9K10;5 intrinsic
carrier densit! n
i
* and thus proportionall! higher recombination current
1
at the bod!-to-source +unction$ The narro)er bandgap and higher
dielectric constant of the Si4e la!er* and the higher bod! doping to
compensate for the lo)ered .
T
caused b! the band o'set* give rise to
larger band-to-band tunneling current and trapped-assisted tunneling
current at the drain-to-bod! +unction$ The latter e'ect ma! overpo)er
the increase in recombination current at the bod!-to-source-+unction*
resulting in more signi(cant 8oating-bod! e'ect$
?igh-k gate dielectric has recentl! been pursued to contain the
gate leakage and e-tend device scaling$ "ost of the potential high-k
gate insulators have lo)er bandgap than Si#
2
and therefore must be
thicker to keep the tunneling leakage do)n$ These materials also have
charge-trapping related .
T
instabilit! and mobile degradation$ The
integration of high-k gate dielectric )ith strained-Si channel signi(cantl!
enhances the mobilit!$ Dotice that* as the high-k gate material o'ers
higher gate capacitance per unit area* some circuit resiHing&retuning
ma! be necessar!* especiall! in the critical paths )here device
capacitances tend to dominate$
I'TROD-&TIO' TO DO-$E2(ATE &)OS
%nnovative device architectures )ill be necessar! to continue
the bene(ts that previousl! acuired through rote scaling$ 0ouble-gate
1"#S 9041"#S5 o'ers distinct advantages for scaling to ver! short
gate lengths$ Furthermore* adoption of gate dielectrics )ith permittivit!
substantiall! greater than that of Si#
2
9so-called 2high-k materials35 ma!
be deferred if a 041"#S architecture is emplo!ed$ 7reviousl!* serious
structural challenges have made adoption of 041"#S architecture
untenable$ Recentl!* through use of the delta device* no) commonl!
referred to as the FinFET* signi(cant advances in 041"#S device
technolog! and performance have been demonstrated$ Fabrication in
1!
FinFET-041"#S is ver! close to that of conventional 1"#S process* )ith
onl! minor disruptions* o'ering the potential for a rapid deplo!ment to
manufacturing$ 7lanar product designs have been converted to FinFETT
041"#S )ithout disruption to the ph!sical area*
thereb! demonstrating its compatibilit! )ith toda!Ns planar 1"#S design
methodolog! and automation techniues$
O3erco4in/ Obstacles $y Doublin/ -p
1"#S technolog! scaling has traversed man! anticipated
barriers over the past 20 !ears to rapidl! progress from 2Um to 90 nm
rules$ 1urrentl!* t)o obstacles* namel! subthreshold and gate-dielectric
leakages* have become the dominant barrier for further 1"#S scaling*
even for highl! leakage-tolerant application such as microprocessors$
DO-$E (ATE FET
)ouble1gate *MOS 6)8*MOS. offers distinct advantages for scaling to very short
gate lengths. Fabrication of FinFET1)8*MOS is very close to that of conventional *MOS
process, &ith only minor disruptions, offering the potential for a rapid deployment to
manufacturing. (lanar product designs have been converted to FinFET1)8*MOS &ithout
disruption to the physical area, thereby demonstrating its compatibility &ith today9s planar
*MOS design methodology and automation techni:ues.
Overcoming Obstacles By Doubling Up
*MOS technology scaling has traversed many anticipated barriers over the past 7
years to rapidly progress from m to 57nm rules. *urrently, t&o obstacles, namely
subthreshold and gate1dielectric leakages, have become the dominant barrier for further
*MOS scaling, even for highly leakage1tolerant applications such as microprocessors.
)ouble1gate 6)8. FETs, in &hich a second gate is added opposite the traditional
6first. gate, have better control over short1channel effects ;S*Es<. S1E limits the
minimum channel length at )hich an FET is electricall! )ell behaved$
1"
Figure schematicall! illustrates the advantage of 04-FETs$
/s the channel length of an FET is reduced* the drain potential
begins to strongl! in8uence the channel potential* leading to an inabilit!
to shut o' the channel current )ith the gate$ This short-channel e'ect is
mitigated b! use of thin gate o-ide 9to increase the in8uence of the gate
on the channel5 and thin depletion depth belo) the channel to the
substrate* to shield the channel from the drain$ 4ate o-ide thickness has
been reduced to the point )here* at 90 nm 1"#S* the po)er drain from
gate leakage is comparable to the po)er used for s)itching of circuits$
Thus* further reduction of the thickness )ould lead to unreasonable
po)er increases$
/lternativel!* further decrease of the depletion region ;
0
degrades
gate in8uence on the channel and leads to a slo)er turn on of the
channel region$
%n 04-FETs* the longitudinal electric (eld generated b! the drain is
better screened from the source end of the channel due to pro-imit! to
the channel of the second gate* resulting in reduced short-channel
e'ects* in particular* reduced drain induced- barrier lo)ering 90%:V5 and
improved subthreshold s)ing 9S5$ Therefore* as 1"#S scaling becomes
limited b! leakage currents* 041"#S o'ers the opportunit! to proceed
be!ond the performance of single-gate 9S45 bulk-silicon or 70S#% 1"#S$
:oth the 0%:V and subthreshold s)ing for the 04 device are dramaticall!
1#
improved relative to those of the bulk-silicon counterpart$ From a bulk-
silicon device design perspective* increased bod! doping concentration
could be emplo!ed to reduce 0%:VB ho)ever* at some point it )ould also
increase the subthreshold s)ing* thereb! reuiring higher threshold
voltage .
T
to keep the subthreshold current adeuatel! lo)$ Similarl!*
decreasing the bod! doping concentration could improve the
subthreshold s)ing but degrade 0%:V$ ?ence a compromise is necessar!
for the bulk-silicon device design$ Dote that* for a scaled bulk-silicon 9or
70 S#% 5 device* a highl! doped channel&halo must be used to control
severe S1Es* and lo)er S for e-tremel! short V
e'
could not be achieved
b! use of lo) channel&halo doping$

%n Figure* simulations of the %0ST.4S characteristics of 04 and S4
FETs sho)s the steeper turn on of the 04-FET* )hich results from the
gate coupling advantage$ This propert! enables the use of lo)er
threshold voltage for the 04-FET for a given o'-current$ /s a direct
result* higher drive currents at lo)er po)er-suppl! voltages .00 are
attainable$
1-
Double_Gate Tresol! Voltage
The ver! thin silicon bod! associated )ith full! depleted 04-FETs
suggests that the centering of .T could be a challenging proposition$
Three basic techniues have been e-plored both theoreticall! and
e-perimentall!* namel!* use of bod! doping* use of as!mmetric gate
)ork function* and use of s!mmetric mid-gap )ork-function gate-
electrodes$
/deuate bod! doping can be achieved b! directl! doping the
silicon bod! or b! use of 2halo3 9also kno)n as 2pocket35 ion implants
introduced laterall! from the gate edges* or a combination of these t)o
techniues$ #ne techniue uniuel! available to 04-FETs is the use of
as!mmetric gates* )herein the t)o gate electrodes are of materials of
di'ering )ork functions$
:od! doping has been the techniue of choice for .
T
centering
in both bulk and 70-S#% planar 1"#S technologies$ /deuate bod!
doping can be achieved b! directl! doping the silicon bod! or b! use of
2halo3 ion implants introduced laterall! from the gate edges* or a
combination of these t)o techniues$
"etal gates o'er the possibilit! of centering threshold voltage
)ith asingle )ork function for both gate electrodes )ithout rel!ing on
bod! doping$ "an! metals )ith )orkfunctions near the middle of the
silicon bandgap e-ist$ @se of these metals in S4-FETs is problematic
since the .
T
of such devices is t!picall! above 0$A . * )hich is too high
for most 1"#S applications$ Vo)er .
T
ma! be achieved b! counter-
doping the
bod!* )hich results in buried conduction channels in the o'-state* thus
degrading short channel e'ects$ "etal gates on 04-FETs* on the other
hand* naturall! achieve the .
T
s in the vicinit! of 0$2 .9the e-act value
depending on the details5 and good short channel characteristics$
1/
DO-$E-(ATE TA5O'O)!
Dumerous structures for 04-FETs have been proposed and
demonstrated$ These structures ma! be classi(ed into one of the three
basic categories$
Type I6 The Planar D(-FET*
This is a direct e-tension of a planar 1"#S process )ith a
second* buried gate

Type II6 The 7ertical D(FET*
?ere bthe silicon bod! has been rotated to a vertical
orientation on the silicon )afer )ith the source and drain on the top and
bottom boundaries of the bod!* and the gates on either side$
Type III 'on Planar FinFET*
%n FinFET the silicon bod! has been rotated on its edge into
a vertical orientation so onl! the source and drain regions are placed
horiHontall! about the bod!* as in a conventional planar FET$ Referred to
as FinFETs as the silicon resembles the dorsal (n of a (sh$
10
TH" DOUB#"$G%T" CH%##"NG"
)81FETs have been the sub=ect of much research for over 7 years> hence, if
)8*MOS offers significant advantage over S8 devices, one must :uestion &hy )8 devices
have not played a significant role on the *MOS technology scene to date.
The four ma+or obstacles to 041"#S are represented
schematicall!$
15
The (rst three issues are closel! related to one another and consist of
1$ de(nition of both gates to the same image siHe accuratel!
2$ self-alignment of the source&drain regions to both top and bottom
gates
=$ alignment of the t)o gates to one another$
These three goals are critical for short devices to
provide high drive current and lo) gate capacitance
simultaneousl!$
I$ The fourth obstacle is that of providing an area-e,cient means of
connecting the t)o gates )ith a lo)-resistance path
T!pe % planar 04-FETs are severel! challenged to deliver all of the
(rst three reuirements since the 2second3 gate is buried belo) a la!er
of active silicon$ The fourth hurdle also challenges the planar 04-FETB a
process module is reuired to de(ne the additional contact to the buried
gate if space is not to be lost to it* and a lo)-resistance gate material
must be introduced in the buried o-ide$
7
T!pe %% vertical 04-FETs t!picall! address problems 1 and I uite
successfull!$ %n this case the gate length is usuall! de(ned b! the
thickness of a deposited gate-electrode material* )hich automaticall!
makes both gates the same length and self-aligned to each other$
Similarl!* the source and drain +unctions can be s!mmetricall! de(ned to
have the same alignment to both gatesB ho)ever* uniue challenges are
presented to de(ning both self-alignment of the bottom +unction to the
gates and to keeping the parasitic series resistances associated )ith the
bottom +unction lo)$ Furthermore* a space-e,cient lo)-capacitance
contact scheme to the lo)er +unction reuires a high-)ire act in process
integration$ 6hile high drive currents have been achieved )ith T!pe %%
structures* high performance 9e$g$* lo) capacitance5 and 1"#S
integration have met )ith limited progress$
T!pe %%% vertical fin1type )81FETs have the advantages access to both gates, and
both sides of source and drain, from the front of the &afer. 8ate length is conventionally
defined since the direction of the current is in the &afer plane. 8ate &idth, ho&ever, is no
longer controlled by lithography> rather, the &idth is given by t&ice the height of the
silicon fin ?Fin .
Finfet
1
&"%TUR"' O& &IN&"T
Finfet consists of a vertical Si fin controlled by self@aligned double gate.
Main Features of Finfet are
1. Altra thin Si fin for suppression of short channel effects
. 3aised source%drain to reduce parasitic resistance and improve currrent drive
!. 8ate@last process &ith lo&@T,high@k gate dielectrics
". Symmetric gates yield great performance,but can built asymmetric gates that target
BT
Finfets are designed to use multiple fins to achieve larger channel
&idths.Source%)rain pads connect the fins in parallel. 4s the number of fins is increased

,the current through the device increases.For egC 4 # fin device # times more current than
single fin device.
Schematic eDplaining the parts of a FinFET
!
(ROC"'' &#O) O& &IN&"T

"
&in&"T$DGC*O' (rocess &lo+ in Detail
#
4 conventional SO$ &afer can be used as starting material, eDcept that the
alignment notch of the &afer is preferably rotated "#E about the aDis of symmetry of the
&afer. The reason for this deviation is to provideF177G planes on silicon fins that are
oriented along the conventional +D, and +y, directions on the &afer.
The process of defining fins and source%drain silicon is very similar to that used to
define trench isolation in today9s *MOS. (atterns are defined and etched into the active top
silicon layer in both processes. The conventional process re:uires additional processing to
fill and planariHe the isolation trenches> the FinFET process, on the other hand, proceeds
directly to channel processing, such as sacrificial oDidations, masked ion implantations for
channels, or specialiHed passive elements, follo&ed by the gate dielectric module.
8ate deposition and etch are very similar, &ith less1severe demands on the
selectivity of the gate1electrode etch to gate oDide, since the oDide surface is orthogonal to
the etch direction. $on implantation of source%drain species and halos6 or pockets. must
differ for obvious geometrical reason but other&ise are largely similar to conventional
planar implantation steps. *onventional *oSi or IiSi processes are used to silicide the
tops of the mesas and the gate, for contacts to source%drain and gate, respectively.
Ho+ To Convert (lanar To &in&"T Tecnology
4s described above, FinFET processing on SO$ &afers uses standard
manufacturing process modules. To etch the ultra thin 6TS$J1#nm. fins, spacer lithography
;side &all image transfer< is used. Since the S$T process al&ays generates an even number
of fins, an eDtra process step is needed for removal of fins to allo& odd number of fins or
other&ise break fin, +loops, &here needed. This means, that for conversion of an eDisting
design, t&o additional levels have to be introduced, namely the + fin, and the +Trim, level.
4ll other design levels remain the same.
*onsider no& a planar design to be converted for processing in the 57 nm
FinFET technology node. The FinFET height ?Fin together &ith the fin pitch 6determined
by photolithography. defines the FinFET device &idth KFin &ithin the given silicon &idth
of the planar device, to get the same or better device strength . For automatic Fin and Trim
generation, Fin18EI, a soft&are tool, has been developed, &hich takes the active area and
poly gate levels, and, based on special FinFET ground rules, generates the additional
-
levels.the circuit 6as &ell as other L1ratio sensitive circuitry. may additionally re:uire
manual ad=ustment on the number of fins in the I1 and (1devices after automatic addition
of fins in the I1 and (1 devices after automatic addition of the FinFET levels.
Mesides device &idth :uantiHation, other factors like &idth variation, threshold
variation, and self1heating must be taken into account &hen designing &ith FinFETs. 4
process &ith multiple threshold voltages and multiple gate oDide thickness is re:uired to
take full advantage of this ne& device.
4s already discussed, the &idth :uantiHation imposes some restrictions on the
device strength fleDibility, but most of them can be absorbed easily &hen converting an
eDisting design or starting a ne& design, respectively. Of course, as stated earlier, latches,
dynamic circuit styles in general, and S34M cells need careful optimiHation &hen
designing &ith FinFETs.
)iscrete devices and circuits for analog applications re:uire special attention. 4s an
eDample, consider a driver%receiver circuit &ith an ES) protection diode. $n a planar
process the protection voltage is proportional =unction length of the diode. $n FinFET
technology the same =unction length per fin pitch may be only about one1eigth of that of the
planar device.
4nother eDample is the total output driver impedance matching, &hich is usually
implemented &ith a planar resistor re:uiring a silicon block resistor, on a silicon island to
ad=ust output impedance 6including the &ire to the pad. to #7 N. For such applications, and
analog circuits in general, special devices may be necessary for optimiHed designs using
FinFETs.
%((#IC%TION' O& &in&"Ts
/
)8 devices like Fin FETs offer uni:ue opportunities for microprocessor
design.compared to a planar process in the same technology node, FinFETs have reduced
channel and gate leakage currents. This can lead to considerable po&er reductions &hen
converting a planar design to fin FET technology. AtiliHing fin FETs &ould lead to a
reduction in total po&er by a factor of t&o, &ithout compromising performance.
4nother possibility to save po&er arises &hen both gates can be controlled
separately. The second gate can be used to control the threshold voltage of the device,
thereby allo&ing fast s&itching on one side and reduced leakage currents &hen circuits are
idle.
Finally, separate access to both gates could also be used to design simplified logic
gates. This &ould also reduce po&er, and save chip area, leading to smaller, more cost1
efficient designs. ?o&ever chip designs using finFETs must cope &ith :uantiHation of
device &idth, since every single transistor consists of an integral number of fins,each fin
having the same height.
'I*U#%TION O& V"RTIC%# DOUB#"$G%T" 'OI
*O'&"T' U'ING D"VIC",D
Intro!uction
This article &ill present the simulation methodology of a self1aligned double1gate
MOSFET structure 6FinFET. using S$2B4*O !1) simulation suite. The double1gate
MOSFET is one of the most attractive alternative to classical MOSFET structure for gate
length do&n to 7nm. The main advantage of the FinFET is the ability to drastically reduce
the short channel effect. $n spite of his double1gate structure, the FinFET is closed to its
root, the conventional MOSFET in layout and fabrication. !1) numerical simulations of the
FinFET are performed in this article, in order to validate the basic principles and to uncover
several important aspectsC evaluation of the length , &idth and :uantum effects.
0
Device &eatures
The features of the structure are sho&n in Figure 1 areC 61. a transistor is formed in
a vertical ultra Othin Si fin and is controlled by a double1gate, &hich considerably reduced
short channel effects> 6. the t&o gates are self aligned and are aligned to S%)> 6!. S%) is
raised to reduce the access resistance> 6". Ap to date gate processC lo& temperature, high 1k
dielectrics can be used and 6#. the structure is :uasi1planar because Si Fin is relatively short
;1,<.
Device 'imulation
The !1) S$2B4*O simulation suite including Device3D, DevEdit3D and
TonyPlot3D, allo&s device engineers to study deep sub1micron devices &hich are !1) by
nature like the FinFET presented above. Furthermore, !1) simulations give access to data
impossible to measure like charge distribution, potential, electric field and current lines.
4 !1) FinFET structure &as designed by using DevEdit3D. This is an advanced
tool for structure editing and mesh generation. The device structure &as realiHed by
dra&ing first the FinFET, from the bottom vie& 6Figure .,in a 6D,y. plane before eDtending
it in the H1direction.
Figure 1: Illustration of DEVEDIT3D used to build the FinFET structure
The H1direction in this case corresponds to the vertical to the substrate. The final !1
) structure is sho&n in TonyPlot3D 6Figure !..
5
Figure 2: Plot of a 50-n FinFET 3-D structure for a !idth of 50n
The basic characteristics of this FinFET &as ToDJnm lengthJ#7nm &idthJ#7nm
and Fin heightJ#7nm. Iote that &e have defined a parameteriHed structure for subse:uent
use in our automation tool, &hich make much more easier any kind of variation 6length,
&idth. to perform large scale simulation.
The main physical effects 6mobility, carrier statistics, recombination. &ere
eDpressed by a set of models universally used for simulating the MOS technologyC mobility
dependence of the electric field and doping level, MoltHmann statistics and Schokley13ead1
?all generation recombination mechanisms ;!<.
'imulation Results
Typical $1B characteristics of a #71nm gate length are sho&n in Figure ". The
leakage current caused by )$M2 &as &ell suppressed.
!7
Figure 3: 50-n FinFET IdVg cur"es for a !idth of 50n#
The roll1off of a FinFET &ith a &idth of #7nm is &ell controlled as can be seen in
Figure #. This result can be correlated to the good control of the channel potential due to
the double gate.
Figure $: Threshold "oltage as a function of gate length for a !idth of 50-n#
!1
The &idth of this FinFET is ad=usted by the number of Si fins. 2et say you &ant to
double the &idth of your device then you have to put Fins bet&een source and drain
6Figure -..
Figure 5: %tructure of a 2-&arallel channel de"ice# 'ate length 50-n#
Iote that this can be achieved very simply using the PmirrorP feature in DevEdit3D.
The resulting $1B curve can be seen
Figure (: Drain current co&arison bet!een single and
2-&arallel channel de"ice# 'ate length 50-n#
!
Finally &e have made simulations using our :uantum module named Quantum3D.
The result is plotted in Figure 0. One can see a shift in the threshold voltage indicating
some :uantum effect. This correction is :uite small as indicated in ;<.
Figure ): *uantu effect in a 50-n !ith a !idth of 50n#
Sub #71nm FinFETs &ere successfully simulated using !1) S$2B4*O simulation
tools. $t is very easy to study the impact of the geometry and doping of this !1) device
using Device3D. $ndeed more and more people take a look at this novel structure since it is
an attractive successor to the single1gate MOSFET.
!!
CONC#U'ION'
Simulations sho& that this structure should be scalable do&n to 17 nm. Formation
of ultra thin fin 67./ 2g, for a lightly doped body. is critical for suppressing short channel
effects. This structure &as fabricated by forming the SQ) before the gate, a techni:ue that
may be needed for future high1k dielectric and metal1gate technologies that cannot tolerate
the high temperatures re:uired for SQ) formation. Further performance improvement is
possible by using a thinner gate dielectric and thinner spacers. )espite its double gate
structure, the FinFET is similar to the conventional MOSFET &ith regard to layout and
!"
fabrication. $t is an attractive successor to the single gate MOSFET by virtue of its superior
electrostatic properties and comparative ease of manufacturability. $ndustrial research
groups such as $ntel, $MM and 4M) have sho&n interests in developing similar devices, as
&ell as mechanisms to migrate mask layouts from Mulk1MOS to FinFETs. $ssues such as
gate &ork function engineering, high :uality ultra thin fin lithography and sourceQdrain
resistance need to be resolved and a high1yield process flo& needs to be established by
process researchers before FinFETs can be used in commercial $*s. )evice researchers
need to understand and model :uantum effects, and circuit design researchers need to
eDploit the packing density afforded by the :uasi1planar device to design efficient
architectures.
R"&"R"NC"'-
1$ S. Thompson, (. (ackan and M. Mohr, +MOS scaling , Transistor challenges for the
1
st
century,, $ntel Tech.R.,vol.S!, pp1115,1550
2$ *.?.Kann, ?. Ioda, T. Tanaka, M.Toshida and *. ?u, +4 comparative study of
advanced MOSFET concepts ,, $EEE Trans. Electron )evices, vol. "!, no. 17, pp
1/"11/#!, Oct. 155-
!#
=$ ).?isamoto, K.*. 2ee, R.UeidHerski, ?.Takeuchi, U.4sano, *.Uuo, T.R.Uing,
R.Mokor and *.?u, +4 folded channel MOSFET for deep1sub1tenth micron era,,in
$E)M Tech. )ig. 1550, pp 17!117!"
I$ ).?isamoto, K.*. 2ee, R.UeidHerski, ?.Takeuchi, U.4sano, *.Uuo. T.R.Uing,
R.Mokor and *.?u, +FinFET1a self1aligned double1gate MOSFET scalable beyond
7 nm,, $EEE Trans.Electron )evices, vol."/, pp. !71!#, )ec. 777.
A$ V. ?uang, K.*. 2ee, *.Uuo, ).?isamoto, 2. *hang, R$ WeidHerski* E$
/nderson* ?$Takeuchi* P$W$ 1hoi* W$/sano* .$Subramanian* T$X$Wing*
X$:okor* 1$?u* 2 Sub-A0 nm FinFET< 7"#S*3 in %E0" Tech$
0ig$1999$*pp YS-S0
Y$ ?$S$ 6ong* W$ 1han and P$Taur* 2Self-aligned 9 top and bottom5
double-gate "#SFET )ith a 2A nm thick silicon channel*3 in %E0"
Tech$*0ig$199S*pp$ I2S-I=0
S$ X$ ?ergenrother et al* 2 The vertical replacement-gate 9.R45
"#SFET< / A0 nm vertical "#SFET )ith lithograph!-independent
gate length*3 in %E0" Tech$ 0ig$ 1999 * pp$ SA-SZ
CONT"NT'
!-
$IT3O)A*T$OI 1
(43T$422T )E(2ETE) SO$ !
(434S$T$* M$(O243 EFFE*T "
?TSTE3ET$* BT B43$4T$OI "
S*42$I8 F3OM () SO$ TO F) SO$ #
M4RO3 )ES$8I $SSAES /
)OAM2E 84TE FET 1
)OAM2E 84TE T4VOIOMT 1#
T?E )OAM2E 84TE *?422EI8E 1/
FE4TA3ES OF F$IFET 15
(3O*ESS F2OK OF F$IFET 1
4((2$*4T$OIS OF F$IFET "
S$MA24T$OI 3ESA2TS "
*OI*2AS$OI !7
3EFE3EI*ES !1
%C.NO)#"DG"*"NT
!/
First, and foremost $ thank Go! %lmigty for making this venture a success.
$ eDtend my sincere gratitude to (ro/0 N0 (remacan!ran, (rincipal, 8ovt.
Engineering *ollege, Thrissur and (ro/0 .0 (0 In!ira!evi1 ?ead of Electronics '
*ommunication )epartment, 8ovt. Engineering *ollege, Thrissur for providing me &ith
necessary infrastructure.
$ &ould like to convey a deep sense of gratitude to the seminar coordinator
*rs0 C0 R0 *uneera for the timely advices.
$ also eDtend my sincere thanks to my friends and seniors for their help.
!0
%B'TR%CT
The introduction of FinFET Technology has opened ne& chapters in Iano1
technology. Simulations sho& that FinFET structure should be scalable do&n to 17 nm.
Formation of ultra thin fin enables suppressed short channel effects. $t is an attractive
successor to the single gate MOSFET by virtue of its superior electrostatic properties and
comparative ease of manufacturability.
!5

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