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    Anonymous BjaA0IiY
    The document discusses modeling combinational logic in Verilog HDL. It presents simple examples to illustrate modeling of combinational logic functions. A more detailed presentation of Verilog HDL can be found in the next chapter. The reader familiar with combinational logic can go directly to Section 4.12 to continue with this subject. The rest of the document contains problems related to simplifying Boolean functions and implementing them using logic gates.

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    97 views4 pages
    The document discusses modeling combinational logic in Verilog HDL. It presents simple examples to illustrate modeling of combinational logic functions. A more detailed presentation of Verilog HDL can be found in the next chapter. The reader familiar with combinational logic can go directly to Section 4.12 to continue with this subject. The rest of the document contains problems related to simplifying Boolean functions and implementing them using logic gates.

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    The document discusses modeling combinational logic in Verilog HDL. It presents simple examples to illustrate modeling of combinational logic functions. A more detailed presentation of Verilog HDL can be found in the next chapter. The reader familiar with combinational logic can go directly to Section 4.12 to continue with this subject. The rest of the document contains problems related to simplifying Boolean functions and implementing them using logic gates.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    97 views4 pages

    Problems: Be As and

    Uploaded by

    Anonymous BjaA0IiY
    The document discusses modeling combinational logic in Verilog HDL. It presents simple examples to illustrate modeling of combinational logic functions. A more detailed presentation of Verilog HDL can be found in the next chapter. The reader familiar with combinational logic can go directly to Section 4.12 to continue with this subject. The rest of the document contains problems related to simplifying Boolean functions and implementing them using logic gates.

    Copyright:

    © All Rights Reserved
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    Download as pdf or txt
    of 4

    Chapter 3 Gate-tewl Mhrhnlzrvtion

    m d l of a ~equentialUDP r q h that Iu output be & l a d as a reg data type, and that


    a column be added to the truth table to b r i b e the next state. So the columns arc organizes as inputs :state :next state.
    In this mtion,we W u d the Verilog HDL and presented simple examples to illustrate
    al-vcs
    for model@ combbtimal lo&. A rnm detailed pentation of Verilog HDL
    ~anbefounainhnextchap.Thereaderfamiliarwith~binational~cango~
    to Section 4.12 to contlnue with this subjdct.

    _=.

    2'

    PROBLEMS
    of the bwk,
    Answers to problems marked with * I*
    st
    3.1' Skllplify tho following B o o b functions, using thra-variable maps:
    01 F ( x , y, t ) = X(0,2.3,4,6)
    (a) F(x, y, t ) = Z(O,2,6,7)
    (dl F(x, y, z ) = BC3,S. 6 7 )
    (c) F(x, y. r )
    X(O.1, Z 3.7)
    Simplify the folio* Boolean fuactim, using three-varinbla maps:
    3.2
    @Y F ( x . y, z ) = 8(1,2.3,6,7)
    (aYC F I X ,g, e) = 2 (0, I, 5.7)
    (d) P ( x , y, z ) = P ( 4 1,3,4,5)
    (c) F ( x , y , z ) = Z(O,1,6,7)
    (0 F(x, y. z) = P(1,4.5.6,7)
    le) F ( x , y, z) = XI1,3,5,7)
    3.3* Simplify the following Bwla ezpsshns, using t h r a - v h b b maps:
    (ay F(x,y,z) = xy + x'y'z' + x'yz'
    IbY F(x,y.z) = x'y' + yz + *'ye'
    (d) F(x, y, z ) = xyz + x'y'e + xy'z'
    Icy F ( x , y, r ) = x'y + yz' + y'z'
    3.4 Simplify the following Boolorn funcdons, using Ku:ansa&gcgkmapn:
    ( b p F(A, B, C, D) = 2(4,6,7,15)
    (a)W F ( x , y, 2) = 2(2,3,& 7)
    ( c ) * F ( A , B , C , D )= E(3,7,11,13,14,15) (d)*F(w,x,y,z) = E(2,3,12,13,14,15)
    (el F(w,x,y, z) = X(1,4,5,6,7,13)
    (0 F(w, x, y, r ) = X(O, 1,5,8,9)
    Simplify
    the
    follow@
    Bwlertn
    function6,
    using
    fowvariabla maps:
    33
    (aY FF(,x, y, z) = 2(1,4,5,6,12,14,15)
    0 F ( A , B , C , D) = X(1,5,9,10,11,14,15)
    (cl F(w, x , y , e ) X(O,1,4.5,6,7,8,9)
    (dyF(A, B, C, D) = X(O,24.5,6,7,8,10,13,15)
    Simplify the following Boolean qmssions, using fwr-variable map:
    3.6
    (arA'B'C'D' + AC'D' + B'CD' + A'BCD + BC'D
    (by x'z w'xy' + w(x'y + x y ' )
    (c) A'B'C'D'
    A'CL)' AB'D' + ABCD + A'BD
    (d) A'B'C'D' + AB'C + B'CD' + ABCD' + BC'D
    Simplify the followhg Boolsan eqmdons, using fow-variable maps:
    3.7

    (ap w'e
    (b)

    + xz + x'y -t wx'z

    + ABC' + AE'C
    + BCD + ACD' + A'B'C + A'BC'D
    xyz + wy + wxy' + x'y
    C'D + A'B'C

    (cp AB'C + B'C'D'


    3

    (d)
    Find the mintsrms of tho following Bwleaa -S

    (arxy + yz + xy'z
    (c) wyz

    f W'X'

    + WXZ'

    by first plotting each function ina q:


    (by C'P + ABC' + ABD' + A'B'D
    (d) A'B

    + A'CD + B'CD + E D '

    3 . 1 Draw n laic diagram using only t w d r p t NOR

    to implement the following fanction:

    F(A, 8,C, D ) = ( A $ B)' (C 0 )

    3,f 9 Simplify tha following hctions,d impkmmt them with tw+level NOR gate dmtits:

    (a)*F = wxt y'zr w'yz'


    @) F(w, x, y, z ) = X(1,2,13,14)
    Ic) F(x.y. r ) = [(x + y)(xl + z)l'

    f ,ZO Drsw the multi-levelNOR and multi-he1 NAND circuits for the following expression:
    3Xl k

    w the multi-level NAND Circlrit for the followingexpssim:

    3 a Convat the logic & a p m of the circuit shown in Fig. 4.4 into a multipbhvd NAND circuit.

    3.23 hqiement tha following Boolean function F,, togetha


    with tha don't-,
    ..
    more than two NOR gate#:
    .
    .

    ~onditimsd, usingno

    '

    >

    F(A,B.C.D)=2(2.4,6,10.12)
    d(A, 8, C, D) = X(0,8, 9.13)
    3

    ' 1

    -#.,

    5..
    - .. .
    .*

    Assume that both h e normal and complsmtnt iapurs arc available.


    ..
    Implement ths following Boolean function F,using the two-level f k of logic (a) NANDAND,@) AND-NOR, .@)OR-NAND, a d (d) NOR-OR
    .:, ; 1 "

    3.m tistd;eetgh'tdsgrmetatew1~f-~~tbst~~sdwtoasinsleolpuation.~xplrin
    how the degwmte tw+lavtl fmms em be used to exttnd the numba of inputs to a gate.
    3.26 With the use of maps,fhd the simplest sum-of-products farm of the function F = fg, where

    f = ak',+ c'd .+ a'cd'


    and
    -

    .' --,.
    - -

    g = (a

    + b'cd'

    + b + e' + d')(b' + c ' + d ) ( a ' + c $ d ' )

    3.27 Show that the dual of the ~ c h s i v o - O RIs also its mplemant.
    3
    Dwive the circuits for a three-bit parity generam and four-bit parity checker using an odd
    parity bit.

    3.29 Impkmat tke following four Boolean uxpradons with three half adders

    li

    D=AOBBC
    E A'BC + A3'C

    F = ABC'
    G = ABC

    ..-

    + (A' + 3')C
    ..

    3-36. Implement the following Boolean w c p w s h with exclusive-OR mdAND


    F = AB'CD' + A'BCD' + AB'C'D + A'BC'D

    gates:

    rlnpolupus
    :(a 'PI
    wu
    v ' 6 WU
    j

    K Z)
    !(a'z 'M)
    !(3'* x)
    :(P'3 '8 'x)
    !P 'S ' 2 % 'X M
    '

    m
    JO

    pus
    pus
    pue
    PIIM

    :A
    :a '3 'a 'V

    Uldlno
    wdu~
    :(j 'a '3 'a 'v) v - q m J g elnpoim R)

    :m$ww

    8 0 ~ r 3m ~w o ?m
    ~ ~q FWWJS i ! w a I~.@!P
    L eu~i
    II

    =IIJO ~ J % V

    =II*w WE

    ~alnpouyopua
    :(3 :a '3)
    80
    '(3 'v 'a)
    wu
    :(a 'a 'v) ~6
    PUQ
    a
    vnchno
    '3 'a m d m o '3 'a 'v
    W~UI
    (4 'a '3 'a 'v)e-ldwx3 e ~ n ~ o u l

    Q aun N
    s eun 11

    r aun 11

    E eull N
    z eu!i 11
    L eun 11

    :~vog&
    UP sal88 on!lrmud lo& samo 1q
    .)

    aiou) ruo!rorspap Su!mo!~oj aqr o! s o l l a muA9 aqa p u ! ~&T.S


    'xo!nsqq s.i!n~~!~
    31
    mmlnug pue q ~ u aa
    q B apfi

    .va + (8
    (,a

    + av)3 = c " D

    + V)(B.J + 38V + ,8J) = <1n0


    .#(a + ,vKs + 3) =

    rime
    :"opu", wqma b!

    -WO
    IJ

    31
    rcq p w d s 1 1 n q~~ J uopdumap
    O
    %IP~A

    = nw h m d ! s m monu!loo~a"!=

    WE

    ' ( a )usd u! rlmrva aql LJPA 01 I!">


    -naaq ae[nm!s pw'(('c ~I~X~~(THOIJVI~I
    g ~ ~ q > n"v!)
    i oqnpou s n l n w r s a"fi ($1
    'sLe~apawSmpnpu! ' W J ~ J
    n p j o uogdu~rapp ~ q -ad
    o l u a ~e apfi (4)
    'ruK = r o l o ~~ u r m l ~ q ~ ~ i ) ~ o l ~ ~ a (u)
    q ~ m s ~ s q l a
    'lo ,ixol = rr
    moq sw8 i!nwa a q JOlndm w 'mil M 20) Lqap so 01 B
    'am%aw neO
    JI islap
    sm 8 B 'JOY%+ M 10) OU p JO BI'P B W!m
    m q (B)iE'E 'SH ;I0 i!n3Jp 1I@Pn!S"IJXo aW.

    we

    LZ'E'S'J UJ

    m omoqr i!ou!l

    (r1n.c '8%

    (3)

    a q j o w q d ~ ~ aa o
    p p s~

    9 7 3 'S'J (a)
    (q)ECE .)!rl (P)
    ( ~ ) z z ' z'Z!A (41
    (~)ZZ'C'$3 ( 8 )
    huamal8le luawa!rrc rnon+moJ B+sn

    rr.~

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