Pal A Charla 1997
Pal A Charla 1997
Subbarao Palacharla
Norman P. Jouppi
J. E. Smith
Abstract
The performance tradeoff between hardware complexity and
clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic, and operand bypassing are analyzed. Each is modeled and Spice simulated for feature sizes of
0.8pm, 0 . 3 5 p and 0.18pm. Performance results and trends are
expressed in terms of issue width and window size. Our analysis indicates that window wakeup and selection logic as well as operand
bypass logic are likely to be the most critical in the future.
A microarchitecture that simplifies wakeup and selection logic
is proposed and discussed. This implementation puts chains of dependent instructions into queues, and issues instructions from multiple queues in parallel. Simulation shows little slowdown as compared with a completely flexible issue window when performance is
measured in clock cycles. Furthermore, because only instructions at
queue heads need to be awakened and selected, issue logic is simplified and the clock cycle is faster - consequently overall performance
is improved. By grouping dependent instructions together, the proposed microarchitecture will help minimize performance degradation due to slow bypasses in future wide-issue machines.
1 Introduction
For many years, a major point of contention among microprocessor designers has revolved around complex implementations that attempt to maximize the number of instructions issued per clock cycle,
and much simpler implementations that have a very fast clock cycle. These two camps are often referred to as brainiacs and speed
demons -taken from an editorial in Microprocessor Report [7]. Of
course the tradeoff is not a simple one, and through innovation and
good engineering, it may be possible to achieve most, if not all, of
the benefits of complex issue schemes, while still allowing a very
fast clock in the implementation; that is, to develop microarchitectures we refer to as complexity-effective. One of two primary objectives of this paper is to propose such a complexity-effective microarchitecture. The proposed microarchitecture achieves high performance, as measured by instructions per cycle (IPC), yet it permits
a design with a very high clock frequency.
Supporting the claim of high IPC with a fast clock leads to the
second primary objective of this paper. It is commonplace to meaPermission to make digital/hard copy of part or all this work for
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206
sure the effectiveness (i.e. IPC) of a new microarchitecture, typically by using trace driven simulation. Such simulations count
clock cycles and can provide IPC in a fairly straightforward manner. However, the complexity (or simplicity) of a microarchitecture
is much more difficult to determine - to be very accurate, it requires
a full implementation in a specific technology. What is very much
needed are fairly straightforward measures of complexity that can
be used by microarchitects at a fairly early stage of the design process. Such methods would allow the determination of complexityeffectiveness. It is the second objective of this paper to take a step
in the direction of characterizing complexity and complexity trends.
Before proceeding, it must be emphasized that while complexity
can be variously quantified in terms such as number of transistors,
die area, and power dissipated, in this paper complexity is measured
as the delay of the critical path through a piece of logic, and the
longest critical path through any of the pipeline stages determines
the clock cycle.
The two primary objectives given above are covered in reverse
order - first sources of pipeline complexity are analyzed, then a
new complexity-effective microarchitecture is proposed and evaluated. In the next section we describe those portions of a microarchitecture that tend to have complexity that grows with increasing
instruction-level parallelism. Of these, we focus on instruction dispatch and issue logic, and data bypass logic. We analyze potential
critical paths in these structures and develop models for quantifying
their delays. We study the variation of these delays with microarchitectural parameters of window size (the number of waiting instructions from which ready instructions are selected for issue) and the issue width (the number of instructions that can be issued in a cycle).
We also study the impact of the technology trend towards smaller
feature sizes. The complexity analysis shows that logic associated
with the issue window and data bypasses are likely to be key limiters of clock speed since smaller feature sizes cause wire delays to
dominate overall delay [20,3].
Taking sources of complexity into account, we propose and evaluate a new microarchitecture. This microarchitecture is called
dependence-based because it focuses on grouping dependent instructions rather than independent ones, as is often the case in superscalar implementations. The dependence-based microarchitecture
simplifies issue window logic while exploiting similar levels of parallelism to that achieved by current superscalar microarchitectures
using more complex logic.
The rest of the paper is organized as follows. Section 2 describes
the sources of complexity in a baseline microarchitecture. Section
3 describes the methodology we use to study the critical pipeline
structures identified in Section 2. Section 4 presents a detailed analysis of each of the structures and shows how their delays vary with
microarchitectural parameters and technology parameters. Section
5 presents the proposed dependence-based microarchitecture and
some preliminary performance results. Finally, we draw conclusions in Section 6.
2 Sources of Complexity
In this section, specific sources of pipeline complexity are considered. We realize that it is impossible to capture all possible microarchitectures in a single model, however, and any results have some
obvious limitations. We can only hope to provide a fairly straightforward model that is typical of most current superscalar processors,
and suggest that analyses similar to those used here can be extended
to other, more advanced techniques as they are developed.
FETCH
I. 4
3 Methodology
The key pipeline structures were studied in two phases. In the
first phase, we selected a representative CMOS circuit for the structure. This was done by studying designs published in the literature
(e.g. ISSCC proceedings) and by collaborating with engineers at
Digital Equipment Corporation. In cases where there was more than
one possible design, we did a preliminary study of the designs to
decide in favor of one that was most promising. By basing our circuits on designs published by microprocessor vendors, we believe
the studied circuits are similar to circuits used in microprocessor designs. In practice, many circuit tricks could be employed to optimize
critical paths. However, we believe that the relative delays between
different structures should be more accurate than the absolute delays.
20 7
LOGlCAL
SOURCE
REGS
4-1
PHYSICAL
MAP
TABLE
REGS
MUX
REGMAPPED
PHYSICAL
TO LOGICAL
REG R
LOGICAL
DEST
RF.Gs
LOGICAL
'
DEPENDENCE
CHECK
LOGIC
(SLICE)
-'
CAM scheme
An altemate scheme for register renaming uses a CAM
(content-addressable memory) [ 191 to store the current mappings. Such a scheme is implemented in the HAL SPARC [2]
and the DEC 21264 [lo]. The number of entries in the CAM is
equal to the number of physical registers. Each entry contains
two fields: the logical register designator that is mapped to the
physical register represented by the entry and a valid bit that is
set if the current mapping is valid. Renaming is accomplished
by matching on the logical register designator field.
4 Pipeline Complexity
In this section, we analyze the critical pipeline structures. The
presentation for each structure begins with a description of the logical function being implemented. Then, possible implementation
schemes are discussed, and one is chosen. Next, we summarize our
analysis of the overall delay in terms of the microarchitectural parameters of issue width and issue window size; a much more detailed version of the analysis appears in [ 151. Finally, Hspice circuit
simulation results are presented and trends are identified and compared with the earlier analysis.
In general, the CAM scheme is less scalable than the RAM scheme
because the number of CAM entries, which is equal to the number
of physical registers, tends to increase with issue width. Also, for
the design space we are interested in, the performance was found to
be comparable. Consequently, we focus on the RAM method below.
A more detailed discussion of the trade-offs involved can be found
in [ E ] .
The dependence check logic proceeds in parallel with the map table access. Every logical register designator being renamed is compared against the logical destination register designators of earlier
instructions in the current rename group. If there is a match, then
the physical register assigned to the result of the earlier instruction is
used instead of the one read from the map table. In the case of multiple matches, the register corresponding to the latest (in dynamic
order) match is used. Dependence check logic for issue widths of
2,4, and 8 was implemented. We found that for these issue widths,
the delay of the dependence check logic is less than the delay of the
map table, and hence the check can be hidden behind the map table
access.
4.1.2 Delay Analysis
As the name suggests, the RAM scheme operates like a standard
RAM. Address decoders drive word lines; an access stack at the addressed cell pulls a bitline low. The bitline changes are sensed by a
sense amplifier which in tum produces the output. Symbolically the
rename delay can be written as,
4.1.1 Structure
The mapping and checkpointing functions of the rename logic
can be implemented in at least two ways. These two schemes, called
the RAM scheme and the CAM scheme, are described next.
Trename
= Tdecode
Tvlordline
Tbitline
-b
Tsemseamp
RAMscheme
In the RAM scheme, implemented in the MIPS RlOOOO [22],
the map table is a register file where the logical register designator directly accesses an entry that contains the physical reg-
208
l6O01
Sense Amp delay
Bitline delay
Wordline delay
Decoder delay
where I W is the issue width and C O , c1, and cz are constants that are
fixed for a given technology and instruction set architecture; derivation of the constants for each component is given in [15]. In each
case, the quadratic component, resulting from the intrinsic RC delay of wires, is relatively small for the design space and technologies we explored. Hence, the decode, wordline, and bitline delays
are effectively linear functions of the issue width.
For the sense amplifier, we found that even though its structural
constitution is independent of the issue width, its delay is a function
of the slope of the input - the bitline delay - and therefore varies
linearly with issue width.
4.1.3 Spice Results
For our Hspice simulations, Figure 3 shows how the delay of the
rename logic varies with the issue width i.e. the number of instructions being renamed every cycle for the three technologies. The
graph includes the breakdown of delay into components discussed
in the previous section.
A number of observations can be made from the graph. The total delay increases linearly with issue width for all the technologies.
This is in conformance with our analysis, summarized in the previous section. Furthermore, each of the components shows a linear
increase with issue width. The increase in the bitline delay is larger
than the increase in the wordline delay as issue width is increased
because the bitlines are longer than the wordlines in our design. The
bitline length is proportional to the number of logical registers (32 in
most cases) whereas the wordline length is proportional to the width
of the physical register designator (less than 8 for the design space
we explored).
Another important observation that can be made from the graph is
that the relative increase in wordline delay, bitline delay, and hence,
total delay as a function of issue width worsens as the feature size is
reduced. For example, as the issue width is increased from 2 to 8,
the percentage increase in bitline delay shoots up from 37% to 53%
as the feature size is reduced from 0.8pm to 0.18pm. Logic delays
in the various components are reduced in proportion to the feature
size, while the presence of wire delays in the wordline and bitline
components cause the wordline and bitline components to fall at a
slower rate. In other words, wire delays in the wordline and bitline
structures will become increasingly important as feature sizes are reduced.
4.2
Wakeup Logic
0.8
0.35
0.18
tagl
I...I
??
inst0
instN- 1
Figure 4:Wakeup logic.
Ttagmatch
4-T m a t c h O R
The time taken to drive the tags depends on the length of the tag
lines and the number of comparators on the tag lines. Increasing the
window size increases both these terms. For a given window size,
~~~
We assume that only one pull-down stack is tumed on since we are interested in the worst-case delay.
increasing issue width also increases both the terms in the following way. Increasing issue width increases the number of matchlines
in each cell and hence increases the height of each cell. Also, increasing issue width increases the number of comparators in each
cell. Note that we assume the maximum number of tags produced
per cycle is equal to the maximum issue width.
In simplified form (see [ 151for a more detailed analysis), the time
taken to drive the tags is:
+ + cz I W ) x W I N S I Z E +
(c3 + c4 x IW + c5 x IW) x WIN SIZE^
CO
Ttagdrive
(CI
The above equation shows that the tag drive time is a quadratic function of the window size. The weighting factor of the quadratic term
is a function of the issue width. The weighting factor becomes significant for issue widths beyond 2. For a given window size, the tag
drive time is also a quadratic function of the issue width. For current technologies (0.35pm and longer) the quadratic component is
relatively small and the tag drive time is largely a linear function of
issue width. However, as the feature size is reduced to 0.18pm, the
quadratic component also increases in significance. The quadratic
component results from the intrinsic RC delay of the tag lines.
In reality, both issue width and window size will be simultaneously increased because a larger window is required for finding more independent instructions to take advantage of wider issue.
Hence, the tag drive time will become significant in future designs
with wider issue widths, bigger windows, and smaller feature sizes.
The tag match time is primarily a function of the length of the
matchline, which varies linearly with the issue width. The match
OR time is the time taken to OR the match lines, and the number of
matchlines is a linear function of issue width. Both of these (refer
to [ 151) have a delay:
expected, the delay increases as window size and issue width are increased. The quadratic dependence of the total delay on the window
size results from the quadratic increase in tag drive time as discussed
in the previous section. This effect is clearly visible for issue width
of 8 and is less significant for issue width of 4. We found similar
curves for 0.8pm and 0.35pm technologies. The quadratic dependence of delay on window size was more prominent in the curves for
0.18pm technology than in the case of the other two technologies.
Also, issue width has a greater impact on the delay than window
size because increasing issue width increases all three components
of the delay. On the other hand, increasing window size only lengthens the tag drive time and to a small extent the tag match time. Overall, the results show that the delay increases by almost 34% going
from 2-way to 4-way and by 46% going from 4-way to 8-way for
a window size of 64 instructions. In reality, the increase in delay
is going to be even worse because in order to sustain a wider issue
width, a larger window is required to find independent instructions.
Figure 6 shows the effect of reducing feature sizes on the various components of the wakeup delay for an 8-way, 64-entry window processor. The tag drive and tag match delays do not scale as
well as the match OR delay. This is expected since tag drive and tag
match delays include wire delays whereas the match OR delay only
consists of logic delays. Quantitatively, the fraction of the total delay contributed by tag drive and tag match delay increases from 52%
to 65% as the feature size is reduced from 0.8pm to 0.18pm. This
shows that the performance of the broadcast operation will become
more crucial in future technologies.
1500,
,1200
Match OR delay
Tag match delay
& 900
However, in both cases the quadratic term is very small for the design space we consider, so these delays are linear functions of issue
width.
8
4
300
0
350
300
0.8
Feature size
250
200
3
Y
a,
150
100
50
0
16
24
32
40
Window Size
48
56
64
210
Selection logic is responsible for choosing instructions for execution from the pool of ready instructions in the issue window. Some
form of selection logic is required because the number and types of
ready instructions may exceed the number and types of functional
units available to execute them.
Inputs to the selection logic are request (REQ) signals, one per
instruction in the issue window. The request signal of an instruction
is raised when the wakeup logic determines that all its operands are
available. The outputs of the selection logic are grant (GRANT) signals, one per request signal. On receipt of the GRANT signal, the
associated instruction is issued to the functional unit.
A selection policy is used to decide which of the requesting instructions is granted. An example selection policy is oZdest$rst the ready instruction that occurs earliest in program order is granted
the functional unit. Butler and Patt [5]studied various policies for
scheduling ready instructions and found that overall performance is
largely independent of the selection policy. The HP PA-8000 uses
a selection policy that is based on the location of the instruction in
the window. We assume the same selection policy in our study.
ISSUE WINDOW
MI I 7
1
25004
Grant propagation delay
Figure 7: Selection logic.
Root delay
Request propagation delay
4.3.1 Structure
The basic structure of selection logic is shown in Figure 7. Modifications to this scheme for handling multiple functional units of the
same type are discussed in [15]. Selection logic consists of a tree of
arbiters that works in two phases. In the first phase, request signals
are propagated up the tree. Each cell raises the anyreq signal if any
of its input request signals is high. This in tum raises the input request signal of its parent arbiter cell. At the root cell one or more
of the input request signals will be high if there are one or more instructions that are ready. The root cell grants the functional unit to
one of its children by raising one of its grant outputs. This initiates
the second phase where the grant signal is propagated down the tree
to the instruction that is selected. The enable signal to the root cell is
high whenever the functional unit is ready to execute an instruction.
The selection policy implemented is static and based strictly on
location of the instruction in the issue window. The leftmost entries
in the window have the highest priority. The oldestjrst policy can
be implemented using this scheme by compacting the issue window
to the left every time instructions are issued and by inserting new instructions at the right end. However, it is possible that the complexity of compaction could degrade performance. In this case, some
restricted form of compacting can be used - so that overall performance is not affected. We did not analyze the complexity of compacting in this study.
64 1215
0.8
16 32 64 128
16 32 64 128
0.35
0.18
4.4
211
pass values from each functional unit source to all possible destinations. Buffers are used to drive the bypass values on the result busses. In addition to the result busses, the datapath comprises
operand MUXes. Operand MUXes are required to gate in the appropriate result on to the operand busses. The control logic is responsible for controlling the operand MUXes. It compares the tags of the
result values with the tag of source value required at each functional
unit. If there is a match, the MUX control is set so that the result
value is driven on the appropriate operand bus. The key factor that
determines the speed of the bypass logic is the delay of the result
wires that are used to transmit bypassed values, not the control.
1 length (A) 1
Wire
Delay
(ps)
20500
49000
184.9
1056.4
I
1
Issue
width
4.4.1 Structure
A commonly used structure for bypass logic is shown in Figure 9.
The figure shows a bit-slice of the datapath. There are four functional units marked F U O to FU3. Consider the bit slice of WO. It
gets its two operand bits from the opd0-1 and opd0-r wires. The result bit is driven on the res0 result wire by the result driver. Tristate buffers are used to drive the result bits on to the operand wires
from the result wires of the functiond units. These buffers implement the MUXes shown in the figure. To bypass the result of functional unit FU1 to the left input of functional unit WO, the tristate
driver marked A is switched on. The driver A connects the res1 wire
and the opd0-1 wire. In the case where bypasses are not activated,
operand bits are placed on the operand wires by the register file read
ports '. The result bits are written to the register file in addition to
being bypassed.
Tbypass
= 0.5
X %=tal
X Cmetai X
L2
where L is the length of the result wires, and Rmetal and Cmetal
are the resistance and parasitic capacitance of metal wires per unit
length respectively.
Increasing issue width increases the length of the result wires,
and hence causes the bypass delay to grow quadratically with issue
width. Increasing the depth of the pipeline also increases the delay
of the bypass logic in the following manner. Making the pipeline
deeper increases the fan-in of the operand MUXes connected to a
given result wire. This in turn increases the amount of capacitance
on the result wires, and hence adds to the delay of the result wires.
However, this component of the delay is not captured by our simple
model. This component of the delay is likely to become relatively
less significant as feature size is reduced.
wires
result
The results presented above assume a particular layout; the functional units are placed on either side of the register file. However,
as mentioned before, the length of the result wires is a function of
the layout. Hence, VLSI designers will have to study altemative layouts in order to reduce bypass delays. Alternative layouts alone will
only decrease constants; the quadratic delay growth with number of
bypasses will remain.
In the long term, microarchitects will have to consider clustered
organizations where each cluster of functional units has its own copy
of the register file and bypasses within a cluster complete in a single cycle while inter-cluster bypasses take two or more cycles. The
hardware or the compiler or both will have to ensure that intercluster bypasses occur infrequently. In addition to mitigating the delay of the bypass logic, this organization also has the advantage of
faster register files since there are fewer ports on each register file.
;;;'
Figure 9: Bypass logic.
212
Issue
width
Window
size
32
64
8
4
32
64
4
8
32
64
Rename
Wakeup+Select
delay (ps)
delay (ps)
0.8pm technology
2903.7
1577.9
3369.4
1710.5
1248.4
627.2
1484.8
726.6
0.18pm technology
578.0
351.0
724.0
427.9
[l], and take a penalty for those that are not present. For an 8-way
machine with deep pipelines, this would exclude a large number of
bypass paths. Another solution is to generalize the method used in
the DEC 21264 [ 101and use multiple copies of the register file. This
is the cluster method referred to in Section 4.4.
In the following section we tackle both the window logic and
bypass problems by proposing a microarchitecture that simplifies
window logic and which naturally supports clustering of functional
units.
Bypass
delay (ps)
184.9
1056.4
184.9
1056.4
5 A Complexity-EffectiveMicroarchitecture
184.9
1056.4
FIFOS
FETCH
SELECT
BYPASS
ACCESS
COMMIT
...
~KEUPI
SELECT EXEC
. ..
...
AKEUP SELECT
...
EXEC
JAKEUI SELECT
The idea behind the dependence-based microarchitecture is to exploit the natural dependences among instructions. A key point is
that dependent instructions cannot execute in parallel. In the proposed microarchitecture, shown in Figure 11, the issue window is
replaced by a small number of FIFO buffers. The FIFO buffers are
constrained to issue in-order, and dependent instructions are steered
to the same FIFO. This ensures that the instructions in a particular
FIFO buffer can only execute sequentially. Hence, unlike the typical issue window where result tags have to be broadcast to all the
entries, the register availability only needs to be fanned out to the
heads of the FIFO buffers. The instructions at the FIFO heads monitor reservation bits (one per physical register) to check for operand
availability. This is discussed in detail later. Furthermore, the selection logic only has to monitor instructions at the heads of the FIFO
buffers.
The steering of dependent instructions to the FIFO buffers is
performed at run-time during the rename stage. Dependence information between instructions is maintained in a table called the
S R C - F I F O table. This table is indexed using logical register designators. S R C - F I F O ( R a ) , the entry for logical register R a , contains the identity of the FIFO buffer that contains the instruction
that will write register R a . If that instruction has already completed
i.e. register R a contains its computed value, then S R C - F I F O (Ra)
is invalid. This table is similar to the map table used for register renaming and can be accessed in parallel with the rename
table. In order to steer an instruction to a particular FIFO, the
S R C - F I F O table is accessed with the register identifiers of the
source operands of an instruction. For example, for steering the instruction add r10,r 5 , 1 where r10 is the destination register,
I add r10, r l , r2
...
EXEC
bubble
...
sub r l , r10,2
213
fetch width^
I-cache
Branch Predictor
~~
All the operands of I have already been computed and are residing in the register file. In this case, 1is steered to a new
(empty) FIFO acquired from a pool of free FIFOs.
1requires a single outstanding operand to be produced by instruction I s o u r c e residing in FIFO Fa. In this case, if there
is no instruction behind I s o u r c e in F a then I is steered to
Fa, else I is steered to a new FIFO.
1 requires two outstanding operands to be produced by instructions I l e f t and I r i g h t residing in FIFOs F a and Fb
respectively. In this case, apply the heuristic in the previous
bullet to the left operand. If the resulting FIFO is not suitable
(it is either full or there is an instruction behind the source instruction), then apply the same heuristic to the right operand.
If all the FIFOs are full or if no empty FIFO is available then the
decoderlsteering logic stalls. A FIFO is returned to the free pool
when the last instruction in the FIFO is issued. Initially, all the FIFOs are in the free pool. Figure 12 illustrates the heuristic on a code
segment from one of the SPEC benchmarks.
Physical Registers
D-cache
any 8 instructions
McFarlings gshare 1131
4K 2-bit counters, 12 bit history
unconditional control instructions
uredicted uerfectlv
64
128
4*01
$@ Baseline microarch
3*5i
Dependence-based microarch.
TUZE
0: addu $18,$0,$2
1: addiu $2,$0,-1
2: beq $18,$2,L2
$4,-32768($28)
3: IW
4: sllv $2,$18,$20
5: xor $16,$2,$19
6: IW$3,-32676($28)
7: sll$2,$16,0x2
8: addu $2,$2,$23
9: lw $2,0($2)
1 0 sllv $4,$18,$4
31
I
11101
13: SW $3,-32676($2S)
1 4 beq $2,$17,L3
0,1,3issue
5,lO issue
.~
compress
li
m88ksim
This figure shows how instructions are steered to FIFOs using the heuristic
presented in Section 5.1 for a sample code segment. Instructions can issue
only from the heads of the four FIFOs. The steering logic steers four instructions every cycle and a maximum of four instructions can issue every cycle.
We compare the performance of the dependence-based microarchitecture against that of a typical microarchitecture with an issue
window. The proposed microarchitecture has 8 FIFOs, with each
FIFO having 8-entries. The issue window of the conventional processor has 64 entries. Both microarchitectures can decode, rename,
and execute a maximum of 8 instructions per cycle. The timing simulator, a modified version of Simplescalar [4], is detailed in Table 3.
214
I Issue I
1
No. physical
128
No. table
16
Bits per
Total
251.7
CLUSTER 1
LOCAL BYPASSES
Figure 14: Clustering the dependence-based microarchitecture: 8way machine organized as two 4-way clusters (2 X 4-way).
Consider the 2x4-way clustered system shown in Figure 14. Two
clusters are used, each of which contains four FIFOs, one copy of
the register file, and four functional units. Renamed instructions are
steered to a FIFO in one of the two clusters. Local bypasses within a
cluster (shown using thick lines) are responsible for bypassing result
values produced in the cluster to the inputs of the functional units in
the same cluster. As shown by the delay results in Table 2, local
bypassing can be accomplished in a single cycle. Inter-cluster bypasses are responsible for bypassing values between functional units
residing in different clusters. Because inter-cluster bypasses require
long wires, it is likely that these bypasses will be relatively slower
and take two or more cycles in future technologies. The two copies
of the register file are identical, except for the one or more cycles
difference in propagating results from one cluster to another.
This clustered, dependence-based microarchitecture has a number of advantages. First, wakeup and selection logic are simplified
as noted previously. Second, because of the heuristic for assigning
dependent instructions to FIFOs, and hence indirectly to clusters,
local bypasses are used much more frequently than inter-clusler bypasses, reducing overall bypass delays. Third, using multiple copies
of the register tile reduces the number of ports on the register file and
will make the access time of the register file faster.
215
signs. In each case there are two clusters with inter-cluster bypasses
taking an extra cycle to complete.
plete in a single cycle. From the graph we can see that for most of
the benchmarks, the dependence-based microarchitecture is nearly
as effective as the window-based microarchitecture even though the
dependence-based microarchitecture is handicapped by slow intercluster bypasses that take 2 cycles. However, for two of the benchmarks, m88ksim and compress, the performance degradation is close
to 12% and 9% respectively. We found that this degradation is
mainly due to extra latency introduced by the slow inter-cluster bypasses.
CENTRAL WINDOW
i
Ef
2-cluster dependence-based8-way
i
CLUSTER 0
CLUSTER 1
A
+b
3.2
3.0
2.8
2.6
2.4
2.2
CLUSTER 0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
t;
7
-
w
CLUSTER 1
0.4
0.2
0.0
compress gcc
go
li
m88ksim per1
vortex
Figure 16: Clustered microarchitectures.
Cuin
In the dependence-based microarchitecture described above, instructions are pre-assigned to a cluster when they are dispatched; we
refer to this as dispatch-driven instruction steering. In contrast, Figure 16(a) illustrates a microarchitecture where instructions reside in
a central window while waiting for their operands and functional
units to become available. Instructions are assigned to the clusters
at the time they begin execution; this is execution-driven instruction
steering.
With this method, cluster assignment works as follows. The register values in the clusters become available at slightly different
times; that is, the result register value produced by a cluster is available in that cluster one cycle earlier than in the other cluster. Consequently, an instruction waiting for the value may be enabled for execution one cycle earlier in one cluster than in the other. The selection
logic monitors the instructions in the window and attempts to assign
them to the cluster which provides their source values first (assuming there is a free functional unit in the cluster). Instructions that
have their source operands available in both clusters are first considered for assignment to cluster 0. Static instruction order is used
to break ties in this case.
The execution-driven approach uses a greedy policy to minimize
the use of slow inter-cluster bypasses while maintaining a high utilization of the functional units. It does so by postponing the assignment of instructions to clusters until execution time. While this
greedy approach may gain some IPC advantages, this organization
suffers from the previously discussed drawbacks of a central window and complex selection logic.
In other words, the dependence-based microarchitecture is capable of supporting a clock that is 25% faster than the clock of
the window-based microarchitecture. Taking this factor into account (and ignoring other pipestages that may have to be more
deeply pipelined), we can estimate the potential speedup with a
dependence-based microarchitecture. The performance improvements vary from 10%to 22% with an average improvement of 16%.
216
cluster has a completely flexible window instead of FIFOs. Instructions are steered to the windows using a heuristic that takes both dependences between instructions and the relative load of the clusters
into account. We tried a number of heuristics and found a simple extension of the FIFO heuristic presented in Section 5.1 to work best.
In our scheme the window is modeled as if it is a collection of FIFOs with instructions capable of issuing from any slot within each
individual FIFO. In this particular case, we treat each 32-entry window as eight FIFOs with four slots each. Note that these FIFOs are a
conceptual device used only by the assignment heuristic -in reality,
instructions issue from the window with complete flexibility.
Kemp and Franklin [ll] studied an organization called PEWs
(Parallel Execution Windows) for simplifying the logic associated
with a central window. PEWs simplifies window logic by splitting
the central instruction window among multiple windows much like
the clustered microarchitecture described above. Register values are
communicated between clusters (called pews) via hardware queues
and a ring interconnection network. In contrast, we assume a broadcast mechanism for the same purpose. Instructions are steered to
the pews based on instruction dependences with a goal to minimize
inter-pew communication. However, for their experiments they assume that each of the pews has as many functional units as the central window organization. This assumption implies that the reduction in complexity achieved is limited since the wakeup and selection logic of the windows in the individual pews still have the same
porting requirements as the central window.
217
cluster i.e. cases in which the operands arrived from the remote cluster in advance. As expected, we see that there is a high correlation
between the frequency of inter-cluster communication and performance - organizations that exhibit higher inter-cluster communication commit fewer instructions per cycle. The inter-cluster communication is particularly high in the case of random steering, reaching
as high as 35% in the case of m88ksim.
4.0
1-cluster.1window
*2 2-cluster.FIFOs.dispatch-steer
2-cluster.windows.dispatch-steer
3.2
fl
gcc
go
li
m88ksim per1
vortex
compress gcc
go
li
m88ksim perf
vortex
compress
5 40,
h
8 35
a,
30
25
20
15
10
fr
F 5
B o
6 Conclusions
We studied the variation of delays of key structures in a generic
superscalar processor with two important microarchitectural parameters: issue width and issue window size. We also analyzed the impact of advanced technologies with smaller feature sizes on the delay of these structures. Our results show that the logic associated
with the issue window and the data bypass logic are going to become
increasingly critical as future designs employ wider issue widths,
bigger windows, and smaller feature sizes. Furthermore, both of
these structures rely on broadcasting values on long wires, and in
future technologies wire delays will increasingly dominate total delay.
This is not to say that the delay of other structures, for example register files and caches, will not cause problems. However,
these structures can be pipelined to some extent. In contrast, window logic and data bypass logic implement atomic operations that
cannot be pipelined while allowing dependent instructions to execute in successive cycles. This characteristic makes the delay of the
window logic and the data bypass logic even more crucial.
Hence, as architects build machines with wider issue widths and
larger window sizes in advanced technologies, it is essential to consider microarchitectures that are complexity-effective i.e. microarchitectures that facilitate a fast clock while exploiting similar levels
of ILP as an ideal large-window machine.
In the second half of the paper, we proposed one such microarchitecture called the dependence-based microarchitecture. The
dependence-based microarchitecture detects chains of dependent instructions and steers the chains to FIFOs which are constrained to
execute in-order. Since only the instructions at the FIFO heads have
to be monitored for execution, the dependence-based microarchitecture simplifies window logic. Furthermore, the dependence-based
microarchitecture naturally lends itself to clustering by grouping dependent instructions together. This grouping of dependent instructions helps mitigate the bypass problem to a large extent by using
fast local bypasses more frequently than slow inter-cluster bypasses.
We compared the performance of a 2x4-way dependence-based microarchitecture with a typical 8-way superscalar. Our results show
two things. First, the proposed microarchitecture has IPC performance close to that of a typical microarchitecture (average degradation in IPC performance is 6.3%). Second, when taking the clock
speed advantage of the dependence-based microarchitecture into account the 8-way dependence-based microarchitecture is 16% faster
than the typical window-based microarchitecture on average.
Acknowledgements
This work was supported in part by an internship at DEC Western Research Laboratory, and by grants from the NSF Grant MIP9505853, and the U.S. Army Intelligence Center and Fort Huachuca
under Contract DABT63-95-C-0127 and ARPA order no. D346.
The views and conclusions contained herein are those of the authors
and should not be interpreted as necessarily representing the official
policies or endorsements, either expressed or implied, of the U. S.
Army Intelligence Center and Fort Huachuca, or the U.S. Govemment.
We thank the staff at DEC-WRL, especially Annie Warren and
Jason Wold, for providing us with the CAD tools used in this study.
Thanks to Andy Glew for answering specific questions regarding the
implementation of the Intel Pentium Pro and for related discussions.
Thanks also to Todd Austin, Scott Breach, and Shamik Das Sharma
for comments on a draft of this paper.
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