Ti VDP Programmers Guide PDF

Video
Programmers Guide
INSTRUMENTS
Video
Display
Processors
Programmers Guide
T~
INSTRUMENTS
IMPORTANT NOTICE
Texas Instruments reserves the right to make changes at any time
in order to improve design and to supply the best product possible.
Texas Instruments assumes no responsibility for infringement of
patents or rights of others based on Texas Instruments applications
assistance or product specifications, since TI does not possess full
access to data concerning the use or applications of customers
products. TI also assumes no responsibility for customer product
designs.
Copyright 1984, Texas Instruments Incorporated
CONTENTS
SECTION
1.
TITLE
PAGE
INTRODUCTION ...................................................
1.1 GeneraIVDPOperation ..........................................
1.2 Reference Material .............................................
1-1
1-1
1-2
FEATURES .......................................................
2.1 Display Planes ................................................
2.2 Display Modes ................................................
2.3 Available Colors ...............................................
2-1
2-1
2-1
2-3
COMMUNICATION BREAKDOWN ......................................

3-1
3.1 CPU to VDP Interface ...........................................
3-2
3.2 Software Operations ...........................................
3-2
TALKING TO THE VDP ...............................................
4-1
4.1 Writing to the VDP Registers ......................................
4-1
4.2 Reading the VDP Status Register ...................................
4-1
4.3 Writing and Reading VRAM .......................................
4-1
DESCRIPTION OF THE VDP REGISTERS ..................................
5-1
5.1 VDP Write-Only Registers ........................................
5-1
5.1.1 Register 0 (Contains Two VDP Control Bits) .....................5-1
5.1.2 Register 1 (Contains Eight VDP Control Bits) .....................5-1
5.1.3 Register 2 .............................................
5-2
5.1.4 Register 3 .............................................
5-3
5.1.5 Register 4 .............................................
5-3
5.1.6 Register 5 .............................................
5-4
5.1.7 Register 6 .............................................
5-4
5.1.8 Register 7 .............................................
5-5
5.2 Read-Only Status Register .......................................
5-5
5.2.1 Interrupt Flag (F) ........................................
5-5
5.2.2 Coincidence Flag (C) .....................................
5-5
5.2.3 Fifth Sprite Flag (SS) and Number ............................
5-6
INITIALIZING THE VDP ..............................................
6-1
6.1 Choosing the Right Mode ........................................
6-1
6.1.1 Graphicsl Mode Initialization ...............................
6-2
6.1.2 Graphicsll Mode Initialization ...............................
6-3
6.1.3 Multicolor Mode Initialization ...............................
6-4
6.1.4 Text Mode initialization ....................................
6-5
CREATING PATTERNS ...............................................
7-1
7.1 All Patterns Are Created Equal .....................................
7-1
7.1.1 Defining Patterns for Text ..................................
7-3
7.1.2 Defining Patterns for Sprites ................................
7-4
iii
THE DIFFERENT DISPLAY MODES ......................................

8-1
8.1 Graphicsl Mode ...............................................
8-1
8.1.1 The Pattern Table ........................................
8-1
8.1.2 The Name Table .........................................
8-1
8.1.3 The Color Table .........................................
8-2
8.2 Graphicsll Mode ..............................................
8-3
8.3 The Pattern Table ..............................................
8-3
8.3.1 The Color Table .........................................
8-4
8.4 The Name Table ...............................................
8-4
8.4.1 Graphics II Mode As a Bit-Mapped Display ......................
8-6
8.4.2 Playing Games with VRAM Addressing ........................
8-8
8.5 Text Mode ...................................................
8-9
8.5.1 The Name Table ........................................
8-10
8.5.2 The Pattern Table .......................................
8-11
8.6 Multicolor Mode ..............................................
8-12
SPRITES ........................................................
9-1
9.1 The Sprite Pattern Table .........................................
9-1
9.2 The Sprite Attribute Table ........................................
9-2
9.2.1 VerticaIPosition .........................................
9-3
9.2.2 Horizontal Position .......................................
9-4
9.2.3 Sprite Name ...........................................
9-4
9.2.4 Sprite Color and Early Clock Bit ..............................
9-5
10.
PROGRAMMING TIPS ..............................................

10-1
10.1 Horizontal and Vertical Scrolling ..................................
10-1
10.2 Animating Sprites ............................................
10-2
10.3 Sprite Coincidence ............................................
10-6
iv
APPENDICES
PAGE
B.
C.
D.
E.
F.
G.
REGISTER VRAM LOOKUP TABLES .....................................

A-1
CPU TO VDP ACCESS TIMES ..........................................
B-1
PATTERN GRAPHICS ADDRESS LOCATION TABLES .........................
C-1
IC PINOUTS FOR TMS9918A/28A/29A AND TMS9118/28/29 .................D-1
DEMO ASSEMBLY LANGUAGE PROGRAMS ...............................
E-1
SPECIAL CHARACTER SET FOR GRAPHICS MODES .........................F-1
GRAPHICS WORKSHEET ............................................
G-1
LIST OF ILLUSTRATIONS
FIGURE
1-1
2-1
3-1
6-1
6-2
6-3
6-4
6-5
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
9-1
9-2
9-3
9-4
PAGE
VDP Flow of Operation ..............................................

1-1
VDP Display Planes .................................................
2-2
CPU to VDP Interface ...............................................
3-1
Register Initialization ................................................
6-1
Graphic I Mode VRAM Memory Map .....................................
6-2
Graphic II Mode VRAM Memory Map ....................................
6-3
Multicolor Mode VRAM Memory Map ....................................
6-4
Text Mode VRAM Memory Map ........................................
6-5
8x8 Pixel Pattern Grid ...............................................
7-1
Example 8x8 Pixel Patterns ...........................................
7-1
Hexidecimal Conversion .............................................
7-2
Pattern Table .....................................................
7-3
6x8 Pixel Pattern Grid for Text Mode .....................................
7-4
8x8 Sprite Grid and Sprite Table ........................................
7-4
16x16 Sprite Grid ..................................................
7-5
Size 1 Sprite Pattern ................................................
7-5
Size 1 Sprite Organization ............................................
7-6
Sprite Pattern Table .................................................
7-7
Graphics I Mode Name Table Mapping ....................................
8-2
Graphics I Mode Mapping ............................................
8-3
Pattern/Color Display Mapping .........................................
8-4
Graphics II Mode Name Table Segmented Into Three Equal Blocks ................
8-5
Graphics II Mode Mapping ............................................
8-5
Graphics II Pattern Table Arranged for Bit-Mapped Graphics ....................
8-7
Text Mode Name Table Pattern Positions .................................
8-10
Pattern Graphics Name Table Mapping ..................................
8-10
6x8 Pixel Pattern Grid for Text Mode ....................................
8-11
Mapping of VRAM Into the Pattern Plane in Text Mode .......................
8-12
Mapping an 8x8 Pixel Multicolor Pattern .................................
8-13
Multicolor Mapping Scheme .........................................
8-15
Sprite Attribute Table As Related to Sprite Planes ............................
9-2
Sprite Attribute Table Entry ...........................................
9-3
Vertical Sprite Positioning ............................................
9-3
Horizontal Sprite Positioning ..........................................
9-4
v
9-5
10-1
10-2
10-3
1 0-4
Sprite Mapping ....................................................

Scrolling the Name Table ............................................
Animated Walking Man .............................................
Animated Planet ..................................................
Animated Planet with Overlay ........................................
9-6
10-1
10-2
10-2
10-3
LIST OF TABLES
TABLE
2-1
3-1
4-1
4-2
4-3
4-4
6-1
6-2
6-3
6-4
8-1
8-2
10-1
PAGE
VDP Color Assignments .............................................

2-3
CPU to VDP Data Transfers ...........................................
3-3
Write to VDP Registers ..............................................
4-1
Read from Status Register ............................................
4-1
Write to VRAM ....................................................
4-2
Read from VRAM ..................................................
4-2
Graphic I Mode Initialization ...........................................
6-2
Graphic II Mode Initialization ..........................................
6-3
Multicolor Mode Initialization ..........................................
6-7
Text Mode Initialization ..............................................
6-9
Graphics I Mode Color Table ...........................................
8-2
New Mode Initialization Values .........................................
8-9
Animation Example Data ............................................
10-4
vi
1.
INTRODUCTION
This is the first in a series of publications concerned with programming Texas Instruments
Video Display Processors. This programmers guide will pay close attention to the fundamentals of initializing and creating a display with the TMS9118/28/29 VDPs. The book also covers their predecessors, the TMS9918A/28A/29A VDPs, and serves as a prerequisite to
future publications on the next generation of Texas Instruments Advanced Video Display
Processors. Device differences are noted for your convenience.
The programming approach in this publication is at the assembly language level. Most programming examples are very general for the sake of clarity. Actual working programs written
in 8088, 6502, TMS7000, and TMS9995 assembly languages are included in Appendix E.*
All necessary subjects about programming a VDP are covered in this programmers guide. If a
subject is not at first discussed thoroughly enough or if more information about a particular
subject is desired, let the Table of Contents guide you to a more detailed discussion of that
topic.
1.1
GENERAL VDP OPERATION

The VDP fetches data from Video RAM (VRAM) and processes it into a serial stream of data
used to control the beam of a CRT as it sweeps across the screen. The VDP performs this
operation over and over again, much like a program executing in a loop. The VDP does, however, perform many more functions in this simulated loop (see Figure 1-1 ).
POWER UP/
RESET
EXAMINE
FETCH GRAPHIC
INFORMATION
FROM
VIDEO RAM
PROCESS
INFORMATION
AND SHIFT IT
OUT SERIALLY
TO THE CRT
DISPLAY
ALLOW HOST
CPU ACCESS TO
REGISTERS OR
VIDEO RAM
REPEATSEQUENCE
FIGURE 1-1 -- VDP FLOW OF OPERATION
Much of the VDPs versatility stems from the fact that it is not restricted to fetching data from
the same place in memory in the same sequence. The VDP has nine internal registers, eight of
which contain option and control bits which may be programmed by the user. The ninth register is the Status Register and may be read by the user in order to determine certain things that
are happening within the VDP. By programming information into the eight control registers,
the VDP can be directed to fetch data from different VRAM locations in various sequences.
The VDP takes time out every few microseconds to see if the host CPU would like access to
one of its internal registers or VRAM. If the VDP did not perform this function, it would not be
possible to program the internal registers, read the status, or even load an artistic masterpiece
into VRAM for display.
* 8088 is a registered trademark of the Intel Corporation, and 6502 is a registered trademark of MOS Technology.
1-1
1.2
REFERENCE MATERIAL
1 ) TMS9918A/28A/29A Video Display Processors Data Manual (MP010A)
2) TMS9118/28/29 Video Display Processors Data Manual (SPPS002)
3) TMS9928/29 and TMS9128/29 Interface to Color Monitors ApplicationReport
(SPPA004)
4) TMS9118/TMS9128/TMS9129 Evaluation Module Users Guide (SPPU003)
5) Dual Video Display Processor Application Report (SPPA005)
1-2
2.
FEATURES
2.1
DISPLAY PLANES
The VDP displays an image on the screen that can best be thought of as a set of 35 display
planes stacked on top of one another (see Figure 2-1). Looking at a monitor or television
screen, we can visualize the highest priority plane as the closest to us and the lowest priority
plane as the plane farthest away.
If patterns on different planes happen to be occupying the same spot on the screen, then the
pattern on the highest priority plane will show through at that spot. For a particular pattern on
a plane to show through, any pattern on higher priority planes directly in front of it must be set
to the VDP color transparent. See the TMS9118/28/29 Video Display Processors Data
Manual (SPPSO02) for more details.
The 35 prioritized planes are shown in Figure 2-1, with each of the first 32 planes containing a
single sprite. A sprite is a definable object whose position on the screen is relative to X,Y
coordinates. The X,Y coordinates are composed of two bytes in VRAM. By changing the data
in these two bytes, a sprite can be moved smoothly around the screen to an X,Y position of
one pixel. Sprites are available in two sizes, either 8x8 pixels or 16xl 6 pixels. These sprites
can also be magnified to 16x 16 or 32x32 pixels.
Behind the 32 Sprite Planes is the Pattern Plane. This plane is used to display either graphics
or text. The VDP can display patterns on this plane in one of four possible modes: Text, G raphics I, Graphics II, or Multicolor.
2.2
DISPLAY MODES
Text Mode breaks the screen down into 6x8 pixel blocks specifically designed for displaying
text. In Graphics I Mode, the screen is broken up into 32 horizontal blocks by 24 vertical
blocks. Each block in Graphics I Mode contains 8x8 pixels, yielding a total screen resolution of
256xl 92 pixels. In Graphics II Mode, the screen breakdown and resolution are the same as in
Graphics I Mode, but more complicated color and pattern displays are possible. Multicolor
Mode is a low-resolution display mode which divides the screen into 64 horizontal blocks by
48 vertical blocks. Each block in Multicolor Mode contains 4x4 pixels and may be one of the
sixteen colors available.
Behind the Pattern Plane is the Backdrop, which is larger in area than the other planes so that it
forms a border around the other planes. The color of the Backdrop is defined by four bits in
VDP Register 7.
The 35th and lowest priority plane is the External VDP Plane. If the output of a second VDP
(slave) is detected by the main VDP (master), then all 35 planes generated by the second VDP
will show through on this 35th plane. For an entity on the 35th plane to show through, all
planes in front of the 35th plane must be transparent at that point.
2-1
)EFAULT
VDP
B~C KD ROP PLANE
I
PATTERN OR MULTICOLOR
PLANE
SPRITE 31
RITE 7
SPRITE
SPRITE 4
SPRITE 3
SPRITE 2
SPRITE 1
~PRITE 0
FIGURE 2-1 -- VDP DISPLAY PLANES
2-2
2.3
AVAILABLE COLORS
The VDP can display 16 colors (including transparent) as shown in Table 2-1. The VDP can
also display fifteen different gray levels on monochrome monitors.
TABLE 2-1 -- VDP COLOR ASSIGNMENTS
COLOR NUMBER
(IN HEX)
ACTUAL COLOR
COLOR NUMBER
(IN HEX)
ACTUAL COLOR
Transparent
Medium Red
Black
Light Red
Medium Green
Dark Yellow
Light Green
Light Yellow
Dark Blue
Dark Green
Light Blue
Magenta (Purple)
Dark Red
Gray
Cyan (Aqua Blue)
White
2-3
3.
COMMUNICATION BREAKDOWN
The circuit shown in Figure 3-1 is actually part of the Texas Instruments TMS9118/28/29
Evaluation Module (available for demonstration at your local TI Field Sales Office). We will use
this circuit to help describe how the CPU and VDP communicate. This circuit is a complete
working system.
DECODER
TMS9995
XTAL1
TMS9118
XTAL1
+5 V
A0
A2
XTAL2
DO
TMS4416
VRAM
DBIN
RESET
D3
cs-~W
W"~
DO
CPU
INT4
DO
D1
D2
D3
D4
D5
D2
D3
D4
A3
A2
A3
A4
A5
A6
A7
D4
D5
D6
D7
+5 V
NMI
VDP
A0
A5
TMS4416
VRAM
A8
A9
A13
A14
AlS
MODE
VIDEO
-~ VIDEO JACK
FIGURE 3-1 - CPU TO VDP INTERFACE
3.1
CPU TO VDP INTERFACE

The CPU communicates with the VDP through an eight-bit bidirectional data bus, three control lines, and an interrupt line. The three control signals are ~ (chip select read), CSW (chip
select write), and MODE. CSR and CSW determine whether the VDP gets information off the
data bus or puts information onto it. If ~ is active, the VDP will output information for the
CPU onto the data bus. If CSW is active, the VDP will get information sent by the CPU off the
data bus.
The MODE signal determines the VDPs source or destination for a data transfer. If the MODE
signal is low, the VDP will do a VRAM operation. If the MODE signal is high, the VDP will do a
VDP register operation.
3-1
One of the easiest ways to design the hardware interface is to set aside two addresses in the
host CPU memory map for VDP communication. In the circuit shown in Figure 3-1, the two
addresses set aside are Hex CO00 and Hex C002. Performing a CPU operation at location Hex
C000 will make the MODE signal low. Performing an operation at Hex C002 will make the
MODE signal high. ~ and ~ are controlled by the CPU read/write logic. If a read operation is performed, CSR will be active (low), and if a write operation is performed, CSW will be
active (low).
NOTE
The addresses you will use in a particular VDP system will probably be different than Hex CO00 and Hex C002, but the function will be the same.
In order to have the full capability of each VDP graphics mode, our VDP must have 16K bytes
of VRAM available. This is also the most popular amount of VRAM found in VDP systems.
VRAM is located in the VDP memory map from Hex 0000 to Hex 3FFF. As described earlier,
VRAM can only be accessed through the VDP by reading or writing from memory locations
Hex C000 and Hex C002.
Another important note to make concerns the examples using address and data lines. Examples in this guide refer to the most significant data line bit (MSB) as DO and the least significant data line bit (LSB) as D 7. This also holds true for the 14 bit address bus, with A0 being the
MSB and A 13 being the LSB.
3.2
SOFTWARE OPERATIONS
The CPU can be programmed to conduct one of four operations:
1 ) Write a byte of data to VRAM
2) Read a byte of data from VRAM
3) Write to one of the eight VDP internal registers, or set up the VRAM address by writing to
the 14-bit Address Register
4) Read the VDP Status Register.
Each of these operations requires one or more data transfers to take place from the CPU to the
VDP. The VDP determines which of these four data transfers is being performed by the state
of the three control signals (CSR, CSW, and MODE) as shown in Table 3-1.
3-2
TABLE 3-1 -- CPU TO VDP DATA TRANSFERS

CSW
CSR
MODE
PORT ADDRESS
Write to VRAM
CO00
Read from VRAM
CO00
Write to VDP register
C002
Read VDP Status Register
C002
OPERATION
NOTE
Memory-mapped addresses >CO00 and >C002 are arbitrary addresses
chosen for this guide.
3-3
4.
TALKING TO THE VDP
4.1
WRITING TO THE VDP REGISTERS

The VDP has eight write-only registers and one read-only Status Register. The write-only registers contain information that controls the operation of the VDP, including the way VRAM is
allocated. The Status Register contains interrupt and sprite information.
A VDP write-only register is loaded using two eight-bit data transfers from the CPU. The first
byte written is the data, and the second byte is the register number and tells the VDP where to
put the data just sent to it. The MSB of the second byte must be a 1, the next four bits must be
Os, and the lowest three bits are the actual register number (from 0 to 7). Table 4-1 shows the
format for the eight write-only registers.
TABLE 4-1 -- WRITE TO VDP REGISTERS
OPERATION
MSB
0
LSB
6
7
Data Write
(Byte 1 )
DO
D1
D2
D3
D4
D5
D6
D7
Register Select
(Byte 2)
Rn
Rn
Rn
CSR CSW MODE
EXAMPLE 4-1.
Lets say we wish to initialize Register 0 (RO) with a value of Hex 00. The first byte written to
address Hex C002 will be Hex 00, the second byte will be Hex 80 (remember from Table 4-1
that the MSB must be set to 1 ). If we had wanted to write Hex O0 to Register 7 (R7), then the
second byte transferred would have been Hex 87. If Hex O0 was to be written to Register 7
(R7), then the second byte transferred would be Hex 87.
4.2
READING THE VDP STATUS REGISTER

The Status Register contents can be read with a single byte transfer, just by doing a read from
address Hex C002 (see Table 4-2).
TABLE 4-2 -- READ FROM STATUS REGISTER
OPERATION
Data Read
(Byte 1 )
4.3
MSB
0 123456 7
DO D1 D2 D3
LSB
D4
D5
D6
CSR CSW
D7
MODE
1
WRITING AND READING VRAM

The VDP is connected to VRAM via a 14-bit autoincrementing Address Register. Once the
address to read from or write to is set up (two-byte data transfer), we can read or write a byte
of data using a one-byte transfer. Continuing to read or write to the VDP causes the address to
increment automatically. Therefore, reading or writing a sequential chunk of data can be performed very quickly. The MODE signal is high (MODE1) for the first two data transfers (address setup), and low (MODEO) for the third when actually reading from or writing to VRAM.
4-1
The following sequences illustrate the proper steps for writing to and reading from VRAM.
Refer to Table 4-3 and Table 4-4 for details.
Write to VRAM
1)
2)
Transfer lower eight bits of address to MODE HIGH.

Transfer upper eight bits of address to MODE HIGH. (The two MSBs must be set to 0 and
1, respectively.)
3) Write a byte to MODE LOW.
4) Write next byte.
TABLE 4-3 -- WRITE TO VRAM
MSB
0
Setup Address
(Byte 1 )
A6
A7
A8
A9
Setup Address
(Byte 2)
Write Data
(Byte 3)
AO
DO
D1
D2
OPERATION
LSB
4
CSR
CSW
MODE
A10
All
A12
A13
A1
A2
A3
A4
A5
D3
D4
D5
D6
D7
Read from VRAM

1)
2)
3)
4)
Transfer lower eight bits of address to MODE HIGH.

Transfer upper eight bits of address to MODE HIGH. (The two MSBs must be set to 0.)
Read a byte from MODE LOW.
Read next byte.
TABLE 4-4 -- READ FROM VRAM
MSB
0
LSB
4
3
Setup Address
(Byte 1 )
A6
A7
A8
A9
A10 All
A12 A13
Setup Address
(Byte 2)
Read Data
(Byte 3)
A0
A1
A2
A3
A4
A5
DO
D1
D2
D3
D4
D5
D6
D7
OPERATION
CSR CSW MODE
EXAMPLE 4-2.
Write To VRAM
Suppose we wish to write Hex 00 to VRAM location Hex 20A0. The first byte transferred to
address Hex C002 would be the lower address byte or Hex A0. The second byte transferred
to address Hex C002 is the upper eight address bits with the two MSBs set to 0 and 1, respectively. Therefore, Hex 60 would be sent as the second byte instead of Hex 20. Now that the
address is set up, a byte of data can be written to Hex 20A0 by a doing a write to address Hex
CO00.
4-2
EXAMPLE 4-3.
Read From VRAM
Suppose we wish to read the byte of VRAM located at Hex 20A0. The first byte transferred to
address Hex C002 would be the lower address byte or Hex A0. The second byte transferred
to address Hex C002 is the upper eight address bits or Hex 20. The address is now set up, and
location Hex 20A0 can be read by doing a read from address Hex C000.
4-3
DESCRIPTION OF THE VDP REGISTERS

VDP WRITE-ONLY REGISTERS
The eight VDP registers are described in the following paragraphs. Registers 0 and 1 contain
bits to enable or disable various features and modes. Registers 2 through 6 contain values
that specify the starting locations of various tables in VRAM. These VRAM tables are used to
generate displays on the Pattern Plane and Sprite Planes. Register 7 contains the color of text
(if in Text Mode) and contains the Backdrop color for all modes.
In some of the registers not all eight bits are used. To insure software compatibility with the
next generation Advanced Video Display Processor, the unused bits must be set to 0s.
NOTE
Bit 0 is the MSB, and Bit 7 is the LSB.
5.1.1
Register 0 (Contains Two VDP Control Bits)

REGISTER 0
MSB
DO
LSB
D7
Bit 6 = M3 (Pattern Mode Bit 3)

This is one of three bits that, when set, determine the display mode the VDP is in. The other
two mode bits are located in Register 1.
M1
0
0
0
1
M2
0
0
1
0
M3
0
1
0
0
Display Mode
Graphics I Mode
Graphics II Mode
Multicolor Mode
Text Mode
Bit 7 = External VDP Plane Enable/Disable

0-Disables External VDP Plane
1 -Enables External VDP Plane
5.1.2
Register I (Contains Eight VDP Control Bits)

REGISTER 1
LSB
DO
MSB
D7
5-1
Bit 0 = 4/16K Selection

O-Selects 4K bytes of VRAM
1 -Selects 16K bytes of VRAM.
NOTE
This bit is used only on the TMS9918A/28A/29A. When using TMS9118/28/
29 this bit is a "Dont Care" and can be set to either state. The TMS9118/28/
29 Family assumes 16K of VRAM is present.
Bit 1 = Display Blank Enable/Disable
0-Causes the active display area to blank
1 -Enables the active display
Blanking causes the Sprite and Pattern Planes to blank but still allows the Backdrop color to
show through. Blanking the display does not destroy any tables in VRAM.
Bit 2 = IE (Interrupt Enable)
O-Disables VDP interrupt
1 -Enables VDP interrupt
If the VDP interrupt is connected in hardware and enabled by this bit, it will occur at the end of
the active screen display area, just before vertical retrace starts. Exceptionally smooth, clean
pattern drawing and sprite movement can be achieved by writing to the VDP during the period
this interrupt is active.
Bit 3,4 = M1 ,M2 (Pattern Mode Bits 1 and 2)
Refer to Bit 6 of Register 0 for a description of these bits.
Bit 5 = Reserved Bit (must be set to O)
Bit 6 = Sprite Size Select
O-Selects Size 0 sprites (8x8 pixels)
1 -Selects Size 1 sprites (16xl 6 pixels)
Bit 7 = Sprite Magnify Option
O-Selects no magnification
1-Selects a magnification of 1, thus 8x8 sprites become 16xl 6 and 16xl 6 sprites become 32x32.
5.1.3
Register 2
REGISTER 2
MSB
LSB
:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
A0
A13
14--BIT VDP ADDRESS
5-2
Register 2 tells the VDP where the starting address of the Name Table is located in VRAM. The
range of its contents is from O-F. The contents of the register form the upper four bits of
the 14-bit VDP address, therefore making the location of the Name Table in VRAM equal to
(Register 2) * 400 (Hex).
5.1.4
Register 3
REGISTER 3
MSB
AO
LSB
I ...............................
A13
14-BIT VDP ADDRESS
Register 3 tells the VDP where the starting address of the Color Table is located in VRAM. The
range of its contents is from O-FF. The contents of the register form the upper eight bits of
the 14-bit VDP address, therefore making the. location of the Color Table in VRAM equal to
NOTE
Register 3 functions differently when the VDP is in Graphics II Mode. In this
mode the Color Table can only be located ~n one of two places in VRAM, either
Hex 0000 or Hex 2000. If Hex 0000 is where you wish the Color Table to be
located, then the MSB in Register 3 has to be a O. If Hex 2000 is the location
choice for your Color Table, then the MSB in Register 3 must be a 1. In either
case, all the LSBs in Register 3 must be set to ls. Therefore, in Graphics II
Mode the only two values that work correctly in Register 3 are Hex 7F and Hex
FF.
5.1.5 Register 4
REGISTER 4
MSB
LSB
A0
A13
14--BIT VDP ADDRESS
Register 4 tells the VDP where the starting address of the Pattern Table is located in VRAM.
The range of its contents is from 0-7. The contents of the register form the upper three bits of
the 14 bit VDP address, therefore making the location of the Pattern Table in VRAM equal to
5-3
NOTE
Register 4 functions differently when the VDP is in Graphics II Mode. In this
mode the Pattern Table can only be located in one of two places in VRAM, either Hex 0000 or Hex 2000. If Hex 0000 is where you wish the Pattern Table to
be located, then the MSB in Register 4 has to be a 0. If Hex 2000 is the location
choice for your Pattern Generator Table, then the MSB in Register 4 must be a
1. In either case, all the LSBs in Register 4 must be set to ls. Therefore, in
Graphics II Mode the only two values that work correctly in Register 4 are Hex
03 and Hex 07.
5.1.6 Register 5
REGISTER 5
MSB
14--BIT VDP ADDRESS
Register 5 tells the VDP where the starting address of the Sprite Attribute Table is located in
VRAM. The range of its contents is from 0-7F. The contents of the register form the upper
seven bits of the 14 bit VDP address, therefore making the location of the Sprite Attribute
Table in VRAM equal to (Register 5) * 80 (Hex).
5.1.7
Register 6
REGISTER 6
MSB
0
A0
LSB
A13
00
14-BIT VDP ADDRESS
Register 6 tells the VDP where the starting address of the Sprite Pattern Table is located in
VRAM. The range of its contents is from 0-7. The contents of the register form the upper
three bits of the 14 bit VDP address, therefore making the location of the Sprite Pattern Table
in VRAM equal to (Register 6) * 800 (Hex).
5-4
5.1.8 Register 7
REGISTER 7
MSB
DO
LSB
D7
The upper four bits of Register 7 contain the color of bits on in Text Mode. The lower four bits
contain the color of bits off in Text Mode and the Backdrop color in all modes.
5.2
READ-ONLY STATUS REGISTER

STATUS REGISTER
MSB
DO
LSB
D7
I
FIFTH SPRITE NUMBER
The VDP Status Register contains the Interrupt Flag, Coincidence Flag, Fifth Sprite Flag, and
the Fifth Sprite Number (if one exists). Each of these is explained in the following paragraphs.
5.2.1
Interrupt Flag (F)

The F flag in the Status Register is set equal to 1 at the end of the raster scan of the last line of
the active display, just before the Backdrop color at the bottom of the screen begins. It is reset
to a 0 after the Status Register is read or whenever the VDP is externally reset (hardware
reset). If the Interrupt Enable bit located in VDP Register 1 is active (1), then the VDP interrupt
output line (INT) will be active (0) whenever the F status flag is 1.
NOTE
The Status Register needs to be read frame-by-frame in order to clear the interrupt and receive the new interrupt for the next frame.
5.2.2
Coincidence Flag (C)

The C status flag will be set to a 1 if two or more sprites coincide. Coincidence occurs if any
two sprites on the screen have at least one overlapping pixel. Sprites set to the VDP color
transparent, as well as those partially or completely off the screen, are considered. Sprites
beyond the Attribute Table terminator of Hex DO are not considered. The C flag is cleared
whenever the VDP Status Register is read or the VDP is externally reset.
5-5
5.2.3
Fifth Sprite Flag (5S) and Number

The Fifth Sprite Flag is set to a 1 whenever there are five or more sprites active on a horizontal
line. The Fifth Sprite Flag is cleared to a 0 after the Status Register is read or whenever the
VDP is externally reset. The number of the lowest priority sprite on the horizontal line is
loaded into thee lower five bits of the Status Register whenever the Fifth Sprite Flag is set and
is valid whenever the Fifth Sprite Flag is a 1. The setting of the Fifth Sprite Flag will not generate an interrupt.
5-6
6.
INITIALIZING THE VDP

After powerup of our VDP system, the first thing to be done is register initialization. In order to
do this we need to know a few things, such as which pattern display mode to use and where
in VRAM we are going to place the tables required. Figure 6-1 shows a procedure for initializing all eight VDP registers. The next section is a brief description of the popular uses for each
mode.
START
SET UP VDP ADDRESS
GET DATA FROM SYSTEM RAM
SEND DATA TO VDP (MODE HIGH)
SEND VDP THE REGISTER NUMBER
NO
YES
CONTINUE
WITH
PROGRAM
FIGURE 6-1 -- REGISTER INITIALIZATION
6.1
CHOOSING THE RIGHT MODE

Most applications displaying text use either Text or Graphics I Mode. Video games needing a
high-resolution display normally use Graphics I or Graphics II Mode. Graphics I Mode is a bit
more popular for games because a colorful, detailed, high-resolution picture can be generated
using very little data. Graphics II Mode is used when a high-resolution picture needs extremely fine detail and color or when you wish to organize memory in a bit-map arrangement
for calculating pixels, lines, circles, etc. The Graphics II Mode bit-map arrangement is also
very popular for personal computer business graphics. Multicolor Mode is popular for games
requiring only a low-resolution display. Sprites are available in all modes except Text and are
primarily used for objects that move and change shape (animation).
6-1
Detailed descriptions of Graphics I, Graphics II, Text, and Multicolor Mode appear in Section
8. Refer to these sections to decide which display mode is best suited to your particular application.
Some typical table values used to initialize the registers in each graphic mode are shown and
described in the following figures. The resulting VRAM Memory Map is shown after the table
values. Actual assembly language programs written for various CPUs and using the following
register initialization values are included in Appendix E.
The typical register initialization values are given here only as one example. Those of you preferring a different VRAM memory map can either calculate the values as described in Section
5 or refer to the Register Address Look-Up Tables provided in Appendix A.
6.1.1
Graphics I Mode Initialization

TABLE 6-1 -- GRAPHIC I MODE INITIALIZATION
REGISTER
MSB LSB
HEX
DESCRIPTION
REG 0
00000000
00
Graphics I Mode,No External Video
REG 1
11000000
CO
16K,Enable Display, Disable Int.,8x8 Sprites,Mag.Off
REG 2
00000101
05
Address of Name Table in VRAM = Hex 1400
REG 3
10000000
80
Address of Color Table in VRAM = Hex 2000
REG 4
00000001
01
Address of Pattern Table in VRAM = Hex 0800
REG 5
00100000
20
Address of Sprite Attribute Table in VRAM = Hex 1000
REG 6
00000000
00
Address of Sprite Pattern Table in VRAM = Hex 0000
REG 7
00000001
01
Backdrop Color = Black
oooo
SPRITE PATTERNS
0800
PATTERN TABLE
1000
SPRITE ATTRIBUTES
UNUSED
1080
1400
NAME TABLE
1800
UNUSED
2000
COLOR TABLE
2020
UNUSED
3FFF
FIGURE 6-2 -- GRAPHIC I MODE VRAM MEMORY MAP
6-2
6.1.2 Graphics II Mode Initialization
TABLE 6-2 -- GRAPHIC II MODE INITIALIZATION

REGISTER
MSB LSB
HEX
DESCRIPTION
REG 0
00000010
02
Graphics II Mode,No External Video
REG 1
11000010
C2
16K,Enable Disp.,Disable Int., 16xl 6 Sprites, Mag.Off
REG 2
00001110
OE
REG 3
11111111
FF
Address of Color Table in VRAM --- Hex 2000
REG 4
00000011
03
REG 5
01110110
76
Address of Sprite Attribute Table in VRAM = Hex 3BOO
REG 6
00000011
03
REG 7
00001111
OF
Backdrop Color = White
0000
PATTERN TABLE
1800
SPRITE PATTERNS
2O00
COLOR TABLE
3800
NAME TABLE
3B00
SPRITE ATTRIBUTES 3C00

UNUSED
3FFF
FIGURE 6-3 -- GRAPHIC II MODE VRAM MEMORY MAP
6-3
6.1.3 Multicolor Mode Initialization
TABLE 6-3 -- MULTICOLOR MODE INITIALIZATION

REGISTER
MSB LSB
HEX
DESCRIPTION
REG 0
00000000
O0
Multicolor Mode,No External Video
REG 1
11001011
CB
16K,Enable Display, Disable Int., 16xl 6 Sprites,Mag.On
REG 2
00000101
05
REG 3
XXXXXXXX
XX
Color Table not used. All bits are dont cares.
REG 4
00000001
01
REG 5
O0100000
20
Address of Sprite Attribute Table in VRAM = Hex 1000
REG 6
00000000
00
REG 7
00000001
04
Backdrop Color = Dark Blue
0o00
SPRITE PATTERN
0800
PATTERN TABLE
0E00
UNUSED
1000
SPRITE ATTRIBUTES 1080
UNUSED
1400
NAME TABLE
1700
UNUSED
3FFF
FIGURE 6-4 -- MULTICOLOR MODE VRAM MEMORY MAP
6-4
6.1.4 Text Mode Initialization
TABLE 6-4 -- TEXT MODE INITIALIZATION

REGISTER
MSB LSB
HEX
REG 0
00000000
O0
Text Mode,No External Video
REG 1
11010000
DO
16K,Enable Disp.,Disable Int..
REG 2
00000010
02
REG 3
XXXXXXXX
XX
Color Table not used. Color is defined in Reg.7
REG 4
00000000
O0
REG 5
XXXXXXXX
20
REG 6
XXXXXXXX
O0
REG 7
11110101
F5
DESCRIPTION
White Text on Light Blue Background
oooo
PATTERN TABLE
0800
NAME TABLE
OBCO
UNUSED
3FFF
FIGURE 6-5 -- TEXT MODE VRAM MEMORY MAP
6-5
CREATING PATTERNS
ALL PATTERNS ARE CREATED EQUAL
If you can create 8x8 pixel patterns you can create fonts for Graphics I Mode, Graphics II
Mode, Text Mode, and sprites. In the following pages we will define some patterns and show
how they should be entered into VRAM in order to produce a display.
1)
Figure 7-1 is a sample grid which will be used to create 8x8 pixel patterns. Each small
square within the grid represents one pixal on the screen.
FIGURE 7-1 -- 8X8 PIXEL PATTERN GRID
2) Fill in the squares within the grid to create your text, graphic, or sprite pattern. Examples
of the letter "A", an arrow, and a star are shown in Figure 7-2.
: II
FIGURE 7-2 -- EXAMPLE 8X8 PIXEL PATTERNS
NOTE
If you are defining patterns to be used in Text Mode (40 patterns per line), the
patterns should be left justified within a 6x8 pixel block like the letter "A"
shown in Figure 7-2. Refer to Section 8.5 for a further description.
3) Now comes the task of converting the pattern to numbers. First assign 1 s to the filled in
squares and Os to the blanks. Then convert the ls and Os to their hexadecimal equivalents as shown in Figure 7-3.
7-1
00100000=20
01010000=50
= O0
= O0
= 04
= 06
= FF
= 06
= 04
= O0
10001000=88
10001000=88
11111000=F8
10001000=88
10001000=88
00000000=00
= 10
FIGURE 7-3 -- HEXIDECIMAL CONVERSION
7-2
4) Now place the 8 bytes that define the pattern into the Pattern Table. Assume that the
location of the Pattern Table in VRAM is defined to be Hex 800, and the arrow is to be
named pattern number 00. Next place the eight bytes into the table as shown in Figure
7-4.
800
801
802
803
804
805
806
807
808
809
80A
80B
80C
80D
80E
80F
810
o0
oo
900
901
902
903
904
905
906
907
oo
oo
oo
0o
0o
00
oo
o0
04
06
FF
PATTERN
NAME 00
O6
04
0o
PATTERN
NAME 01
PATTERN
NAME 20
908
A08
A09
A0A
A0B
A0C
A0D
A0E
A0F
20
5O
88
88
F8
PATTERN
NAME 41
88
88
00
FIGURE 7-4 - PATTERN TABLE
7.1.1
Defining Patterns for Text

When using text in your application, it is often convenient to place the eight bytes defining
your text character in its actual ASCII number location. This will simplify writing text to the
screen. Writing the ASCII value directly to the Name Table causes the appropriate character to
appear on the screen. As shown in Example 7-1, a space character is contained in Pattern
Table position Hex 20, and the letter "A" is contained in Pattern Table position Hex 41.
7-3
EXAMPLE 7-1.
ASCII
Space = Hex20
?
= Hex 3F
A
= Hex 41
B
= Hex 42
C
= Hex 43
Etc.
NOTE
When defining patterns for Text Mode, the pattern must be defined within a
6x8 pixel grid as shown in Figure 7-5. The two LSBs are unused and therefore
not displayed by the VDP.
oo
oo
oo
oo
oo
00
oo
o,o,
UNUSED
FIGURE 7-5 - 6X8 PIXEL PATTERN GRID FOR TEXT MODE
7.1.2
Defining Patterns for Sprites
1) To use Size 0 sprites (8x8 pixels), the patterns are defined exactly like the arrow and the
star shape done earlier with one change. Instead of entering the code in the Pattern
Table, it is now entered into the Sprite Pattern Table. Figure 7-6 shows a sprite grid and
the Sprite Generator Table for an 8x8 pixel sprite pattern.
lO
8x8
oo0
OOl
002
003
004
005
006
007
008
009
00A
00B
00C
00D
00E
00F
010
SPRITE
NAME 00
SPRITE
NAME 01
FIGURE 7-6 -- 8X8 SPRITE GRID AND SPRITE TABLE
7-4
2) If you are going to use Size 1 sprites (1 6xl 6 pixels), then the patterns are still defined as
8x8 pixel patterns. It takes four 8x8 pixel patterns to form a 1 6x 16 pixel grid as shown in
Figure 7-7.
FIGURE 7-7 -- 16X16 SPRITE GRID

3) Fill in the squares to create your Size 1 sprite pattern, An example is shown in Figure 7-8,
07=
1F=
3F=
67=
67=
FF=
FF=
FF=
DF=
CF=
C3=
60=
70=
3C=
1F=
O7=
=EO
=F8
=FC
=E6
=E6
=FF
=FF
=FF
=FB
=F3
=C3
=06
=0E
=3C
=F8
=E0
FIGURE 7-8 -- SIZE 1 SPRITE PATTERN
7-5
4) Next encode the sprite pattern. This is done by splitting the sprite into four sections as
shown in Figure 7-9. The four 8x8 pixel patterns should be encoded in the following
order.
Pattern 1 = upper left
Pattern 2 = lower left
Pattern 3 = Upper right
Pattern 4 = Lower right
PATTERN 2
FIGURE 7-9 -- SIZE 1 SPRITE ORGANIZATION
7-6
PATTERN 4
5) Place the 32 bytes of information in the Sprite Pattern Table, assuming that the table in
VRAM is located at Hex 0000. Figure 7-10 shows how the Sprite Generator Table looks
for our 16x 16 pixel sprite.
000
001
002
003
004
005
006
007
008
009
00A
00B
00C
00D
00E
00F
010
011
012
013
014
015
016
017
018
019
01A
01B
01C
01D
01E
01F
16 X 16
07
1F
3F
67
67
FF
FF
FF
DF
CF
C3
60
70
3C
1F
07
E0
F8
FC
E6
E6
FF
FF
FF
FB
F3
C3
06
0E
3C
F8
E0
UPPER
LEFT
CORNER
LOWER
LEFT
CORNER
SPRITE
NAME00
UPPER
RIGHT
CORNER
LOWER
RIGHT
CORNER~
SPRITE
NAME 04
FIGURE 7-10 -- SPRITE PATTERN TABLE
7-7
THE DIFFERENT DISPLAY MODES

GRAPHICS I MODE
The VDP is in Graphics I Mode when all three mode bits (M 1 ,M2,M3) located in VDP Registers
0 and 1 are set to zero. When in this mode, the Pattern Plane has a resolution of 256 horizontal
pixels by 192 vertical pixels. The screen is broken up into blocks each containing an 8x8 pixel
pattern. There are 32 of these blocks horizontally and 24 of them vertically. Figure 8-1 shows
the position of these 768 blocks on the screen.
ROW C 000
ROW 1 032
ROW ; 064
ROW 096
ROW 2( 640
ROW 21 672
ROW 21 704
ROW
736
001
033
065
097
002
034
066
098
641
673
705
737
003
035
067
099
028
060
092
124
029
061
093
125
ACTIVE DISPLAY AREA

642
674
706
738
643
675
707
739
668
700
732
764
669
701
733
765
030
062
094
126
031
063
095
127
670
702
734
766
671
703
735
767
HEX 01 F)
HEX 03F)
HEX 05F)
HEX 07F)
HEX 29F)
HEX 2BF)
HEX 2DF)
HEX 2FF)
FIGURE 8-1 -- GRAPHICS I MODE NAME TABLE MAPPING
Three tables are required in VRAM in order to create a Graphics I Mode picture, these are the
Name Table, Pattern Table, and the Color Table. If every possible bit of color and pattern detail
is defined, a Graphics I Mode picture would take up 2848 (Hex B20) bytes.
8.1.1
The Pattern Table

The Pattern Table contains a library of user defined patterns that can be displayed in any of the
788 screen positions. It is 2048 bytes long and is arranged as 256 eight byte patterns. Each
one of these eight byte patterns defines an 8x8 pixel area. All of the 1 s within a pattern designate one color (lets call this color 1 ), while all of the Os designate another color (color 0).
A unique feature of Graphics I Mode, as opposed to bit-mapped graphics, is the fact that once
an 8x8 pixel pattern has been defined and stored in the Pattern Table, it can be used multiple
times on the screen without being redefined.
EXAMPLE 8-1.
If only the first eight byte pattern in the Pattern Table was defined (Pattern 0), you could place
this pattern in every single one of the 768 screen positions by writing Hex O0 to every byte of
the 768 byte Name Table.
8.1.2
The Name Table

As illustrated in Figure 8-1, there are 768 screen locations. Each of these locations is represented by one byte of memory located in the Name Table. The first byte of the Name Table
specifies which pattern will be located in the upper left hand corner of the screen. The last
8-1
byte in the Name Table specifies the pattern for the lower right hand screen corner. Each byte
entry in the Name Table can designate one of 256 (Hex FF) patterns. The location of the 768
byte Name Table in VRAM is defined by the base address located in VDP Register 2.
8.1.3
The Color Table

The Color Table for a Graphics I Mode picture is 32 bytes long. Its location in VRAM is determined by the eight-bit Color Table base address in VDP Register 3.
The color of the 1 s and Os within a pattern is defined by the Color Table. Each byte entry in the
Color Table defines two colors. The upper nibble (four bits) defines the color of the 1 s, and the
lower nibble defines the color of the 0s. Since we can create 256 unique 8x8 pixel patterns
but can only have 32 Color Table entries, each entry in the Color Table must define the color
for more than one pattern. In fact, the first byte in the Color Table defines the color for the first
eight patterns. Likewise, the second byte in the Color Table defines the color for the next eight
patterns defined.
Table 8-1 illustrates the Graphics I Mode Color Table.
Figure 8-2 illustrates how the Pattern Table, Name Table, and Color Table are mapped to the
screen.
TABLE 8-1 -- GRAPHICS I MODE COLOR TABLE
BYTE NO.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
8-2
PATTERN NO.
0..7
8..15
16,.23
24..31
32..39
40..47
48..55
56..63
64..71
72..79
80..87
88..95
96..103
104.. 111
112..119
120..127
BYTE NO.
PATTERN NO.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
128..135
136..143
144..151
152..159
160..167
168.,175
176..183
184..191
192..199
200..207
208..215
216..223
224..231
232..239
240..247
248..255
BASE ADDRESS
0
1
2
~PATTERN POSITION 0
--PATTERN POSITION 1
0
1
2
32POSITIONS ~-~ PATTERN
L_LJ
BASE
ADDRESS
M
8M PATTERN =N
m --1~
8M+~ (8 BYTES)
~ POSITION 31
~ PATTERN
t
== ~ POSITION
~ ~ "N" 24 POSITIONS
766
767
PATTERN
NAME TABLE
2046
2047
PATTERN
GENERATOR TABLE
PATTERN PLANE ~. PATTERN

POSITION
767
PATTERN
COLOR TABLE
FIGURE 8-2 -- GRAPHICS I MODE MAPPING
8.2
GRAPHICS II MODE
Graphics II Mode is similar to Graphics I Mode in the way the screen is organized. The resolution is still 256 horizontal pixels by 192 vertical pixels. Three tables are still required in VRAM
in order to generate a display, these being the Name Table, Color Table, and Pattern Table. The
Name Table is still 768 bytes long, but the length of the Color and Pattern Tables has been
extended. Instead of having to choose from a library of 256 8x8 pixel patterns for display in
the 768 screen locations (which means patterns have to be reused) you can define 768 8x8
pixel patterns in Graphics II Mode. This allows a unique pattern to be created for every possible screen location. Instead of one byte of color information for every eight patterns, there are
now eight bytes of color information per pattern, thereby making the Pattern Table and the
Color Table in Graphics II Mode the same length.
Since there are eight bytes of color information per pattern, two unique colors can be specified for each line of an 8x8 pixel pattern. This allows up to 16 colors within a pattern.
8.3
THE PATTERN TABLE

The Pattern Table is 6144 (Hex 1800) bytes long, assuming all patterns are defined, and is
best thought of as three equal blocks of 2048 bytes of pattern information. Each of the three
2048 byte blocks is divided into 256 8x8 pixel pattern definitions. The first 256 patterns can
only be displayed on the upper third of the screen. The second 256 patterns can only be displayed on the middle section of the screen, and the last 256 patterns can only be displayed on
the lower third of the screen.
8-3
8.3.1 The Color Table

The Color Table is 6144 (Hex 1800) bytes long, assuming all colors are defined, and is segmented into three 2048 byte blocks exactly like the Pattern Table. Each 2048 byte block is
divided into 256 color definitions, each being eight bytes long. The first 256 color definitions
correspond directly to the first 256 patterns defined. Likewise, the second 256 color definitions correspond to the second 256 patterns, and the third 256 color definitions correspond
to the last 256 patterns defined.
It takes eight bytes to define a pattern shape and eight bytes to define what color that pattern
will be. Each byte in a color definition defines the color of the bits that are on or off for the
corresponding line of the pattern. The upper four bits define the color of the bits on, the lower
four bits define the color of the bits off in a line of the pattern. An example of how color is
mapped to a pattern is shown in Figure 8-3.
0
ROW 0
1 (BLACK)
B (LT. YELLOW)
0 ROW
7 (CYAN)
B (LT. YELLOW)
B C
B B
C (GREEN)
B (LT. YELLOW)
B B
E (GRAY)
B (LT. YELLOW)
B B
8 (MED. RED)
B (LT. YELLOW)
B B
5 (LT. BLUE)
B (LT. YELLOW)
6 (DK. RED)
B (LT. YELLOW)
D (MAGENTA)
B (LT. YELLOW)
PATTERN GENERATOR
TABLE ENTRY
PATTERN COLOR
PATTERN
TABLE ENTRY
FIGURE 8-3 -- PATTERN/COLOR DISPLAY MAPPING
8.4
THE NAME TABLE

As in Graphics I Mode, the Name Table of Graphics II Mode contains 768 entries which correspond to each of the 768 pattern positions on the display screen. Because each Name Table
entry is only one byte long, it can only specify one of 256 patterns (Hex FF). In order to be able
to specify a unique pattern for each of the 768 pattern positions, the screen is broken up into
three sections as shown in Figure 8-4. Each of the screen sections is 256 bytes long, and
since a byte can specify 256 different values, a unique pattern can be specified for each
screen location. An example of Graphics II Mode mapping is shown in Figure 8-5.
8-4
III
ooo_L[__L_J
(HEX OFF)
(HEX 1FF)
(HEX 2FF)
FIGURE 8-4 -- GRAPHICS II MODE NAME TABLE SEGMENTED INTO THREE EQUAL BLOCKS
PATTERN
(8 BYTES)
~ PATT, ERN POST ON 0

PATTERN
POSITION
31
,~j PATTERN POSITION 1
PATTERN=M2
~,~._ PATTERN
POSITION
"NI"
PATTERN
POSITION
255
,,,
._,~"PATTERN POSITION 256
255
256
(8 BYTES)
6143
N2
"~
P2
PATTERN GENERATOR]
TABLE
|
0
512
N3
~] p 2---~.__~lk_ P A T T E R N POSITION
"N2"
.~"PATTERN POSITION 512
PATTERN
II,-- POSITION
511
PATTERN POSITION
PATTERN
I-.-- POSITION
767
: PATTERN=M1
(8BYTES)
P3
i-
PATTERN PLANE
204;
204~
767
PATTERN NAME
TABLE
PATTERN=M2
(8 BYTES)
--
~
409~
40~
PATTERN=M3
(SBYTES)
6143
PATTERN COLOR
TABLE
FIGURE 8-5 - GRAPHICS II MODE MAPPING
8-5
8.4.1
Graphics II Mode As a Bit-Mapped Display

A neat feature of Graphics II Mode is that it can be arranged by the programmer to act as a bitmapped display. This is extremely useful when your application allows the use of an algorithm
to calculate the position of pixels on the screen instead of hand drawing them (coding each
pixel at a time). Using Graphics II Mode as a bit-map lets you address every pixel on the screen
individually for plotting points, drawing lines, circles, etc. The only drawback to this arrangement is that even though the Pattern Plane is completely bit-mapped, the color assignments
are not. Since a unique color cannot be specified for each pixel on the screen, one of two
things can be done; use more than two colors (but be careful where you plot them on the
screen) or use only two colors (pixels on could be one color, pixels off another) and not worry
about where you plot.
The way to arrange Graphics II Mode as a bit-map is to write a different value to each of the
768 Name Table entries. This means that the VDP will map a unique Pattern Table entry to
each screen position. By writing to a byte within an eight byte Pattern Table entry, any pixel on
the screen can be turned on or off.
The simplest way to illustrate this point is to write the same value to each of the Color Table
entries. A color value of Hex 4F written to all Color Table locations makes for nice blue pixels
on a white background (pixels on will be blue, and pixels off will be white).
As stated earlier, to specify a bit-map a unique pattern is defined for each entry in the Narr~e
Table. An organized way to do this is to write Hex 00 to the first Name Table entry, Hex 01 to
the second, Hex 02 to the third, and so forth. After reaching Hex FF the process is repeated
twice more so that a dump of the 768 byte Name Table would render the values 0 - FF, O- FF,
0-FF.
At this point we can forget about the Name Table and the Color Table and concentrate on the
Pattern Table. Each bit within a Pattern Table byte entry now represents a unique pixei on the
screen. Figure 8-6 illustrates how the Pattern table is currently mapped to the screen. This
figure assumes that the location of the Pattern Table in VRAM starts at Hex 0000.
8-6
000 008
001 009
002 00A
003 00B
004 00C
005 00D
006 00E
007 00F
100 108
101
109
102 10A
103 10B
104 10C
~I05__10D
010 018 020 028

011 019 021
029
012 01A 022 02A
013 01B 023 02B
014 01C 024 02C
015 01D 025 02D
016 01E 026 02E
017 01F 027 02F
110
118 120 128
111
119 121
129
112-.11A
122 12A
113 11B 123 12B
114
11C 124 12C
115 11D J25 , 12D
030
031
032
033
034
035
036
037
130
131
132
133
13~
135
0381
039
03A
03B
03C
03D
03E:
03F
138
139
13A
13B
13C
13D
!0C0 0C8
0C1 0C9
0C2 0CA
0C3 0CB
0C4 0CC
0C5 0CD
0C6 0CE
0C7 0CF
1C0 1C8
1C1 1C9
1C2 1CA
1C3 1CB
1C4 1CC
1C5 _ICD
0D0
0D1
0D2
0D3
0D4
0D5
0D6
0D7
1D0
1D1
1D2
1D3
1D4
1D5
0D8
0D9
0DA
0DB
0DC
ODD
ODE
0DF
1D8
1D9
1DA
1DB
1DC
1DD
0E0
0El
0E2
0E3
0E4
0E5
0E6
0E7
1E0
1E1
1E2
1E3
1E4
1E5
0E8 0F0
0E9 0F1
0EA 0F2
0EB 0F3
0EC 0F4
0ED 0F5
0EE 0F6
0E~: -~OF7
1E8 1F0
1E9 1F1
lEA 1F2
1EB 1F3
1EC 1F4
1ED__IF5
0F8
0F9
0FA
0FB
0FC
0FD
0FE
OFF
1F8
1F9
1FA
1FB
1FC
1Fr
/!
161A 1622 162A
1603 160B 1613 161B 1623 162BI
1605
1606
1607
1700
1701
1702
1703
1704
1705
1706
1707
160D
160E
160F
1708
1709
170A
170B
170C
170D
170E
170F
1615
1616
1617
1710
1711
1712
1713
1714
1715
1716
1717
161D
161E
161F
1718
1719
171A
171B
171C
171D
171E
171F
1625
1626
1627
1720
1721
1722
1723
1724
1725
1726
1727
162D
1626
162F
1728
1729
172A
172B
172C
1720
172E
172F
\
\
16D2 16DA 16E2 16EA 16F2 16FA

16D3 16DB 16E3 16EB 16F3 16FB
16D4 16DC 16E4 16EC 16F4 16FC
16D5 16DD 16E5 16ED 16F5 16FD
16D6 16DE 16E6 16EE 16F6 16FE
16D7 16DF 16E7 16EF 16F7 16FF
!17D0 17D8 17E0 17E8 17F0 17F8
17D1 17D9 17E1 17E9 17F1 17F9
17D2 17DA 17E2 17EA 17F2 17FA
17D3 17DB 17E3 17EB 17F3 17FB
17D4 17DC 17E4 17EC 17F4 17FC
~ 17D5 17DD 17E5 17ED 17F5 17FD
17D6 17DE 17E6 17EE 17F6 17FE
17D7 17DF 17E7 17EF 17F7 17FF
FIGURE 8-6 -- GRAPHICS II PATTERN TABLE ARRANGED FOR BIT-MAPPED GRAPHICS
Looking at Figure 8-6 we can see that in order to turn on the pixel located in the upper lefthand
corner of the display we would write Hex 80 to the first byte of the Pattern Table (location Hex
0000). Likewise, to turn on the pixel at the bottom righthand screen edge Hex 01 would be
written to location Hex 1755.
At this point we can do ourselves a favor by writing a routine that, given any X,Y coordinates,
will tell us the address of the byte we wish to write to and the data we need to write to it. The
following is a step-by-step procedure of one way to calculate the address and the data.
8-7
EXAMPLE 8-2.
INPUTS: X = Hex O0-FF or Decimal 0-255
Y = HexOO-C0orDecima10-192
1)
Take the integer value of (X/8) and multiply it times 8. This will give the horizontal byte
offset. The actual bit we need to plot is determined by whatever remainder is left after
calculating (X/8).
2) Take the integer value of (Y/8) and multiply it times Hex 100. This will give the vertical
byte offset to the nearest eight bits. If there is any remainder after calculating (Y/8), add
it to the vertical byte offset. This gives the vertical starting address.
3) Add the horizontal byte offset to the vertical starting address. This will give the actual
address of the byte we need to write data to in order to plot our pixel.
4) Use the re~nainder of (X/8) to look up in a table (below) the actual data to plot. The values
corresponding to different remainders are as follows:
Remainder (X/8)
0
1
2
3
4
5
6
7
Data to Write
Hex 80
Hex 40
Hex 20
Hex 10
Hex 08
Hex 04
Hex 02
Hex01
The equation just described in the above paragraphs could be represented as follows:
BYTE ADDRESS = 8(INT(X/8)) + 256(INT(Y/8)) + R(Y/8)
WHERE R(Y/8) is equal to the remainder of (Y/8)
The actual data to write to the byte address is still obtained by taking the remainder of (X/8)
and looking up the appropriate data value in the table.
8.4.2
Playing Games with VRAM Addressing

So far in Section 2.1 we have described how to use Graphics II Mode in its normal table-driven
environment and how to arrange it as a bit-map. Now we are going to explain some other
tricks you can play with the VDP. By experimenting with the values in VDP Registers R2 thru
R6 (entering nonstandard initialization values), some interesting effects can be obtained.
You are forewarned that experimenting with VRAM addressing can cause some interesting
effects but almost always produces some undesirable side effects such as losing the ability to
use sprites or being only able to use a small number of sprites. Rather than dwell too long on
this subject, we will describe one interesting new configuration that can be obtained and
leave the rest to you.
Table 8-2 shows the register initialization values for the mode about to be described. Note that
the only registers containing nonstandard values are Registers 3 and 4, which determine the
Color Table and Pattern Table base address.
8-8
TABLE 8-2 -- NEW MODE INITIALIZATION VALUES

REGISTER
MSBLSB
HEX
DESCRIPTION
REG 0
00000010
O2
Graphics II Mode,No External Video
REG 1
11000010
C2
16K,Enable Disp.,Disable int., 16xl 6 Sprites,Mag.Off
REG 2
00001110
0E
REG 3
10011111
9F
Color Table Address = Hex 2000 to Hex 2800
REG 4
00000000
00
Pattern Table Address = Hex 0000 to Hex 0800
REG 5
01110110
76
Address of Sprite Attribute Table in VRAM = Hex 3BOO
REG 6
00000011
O3
Address of Sprite Pattern Table in VRAM = 1800
REG 7
00001111
OF
Backdrop Color = White
What this mode does is effectively shrink the Graphics II Mode Color and Pattern Tables down
from Hex 1800 bytes to Hex 800 bytes. This enables us to define up to 256 8x8 pixel patterns
and 256 corresponding eight byte Color Table entries. Color is still mapped onto a pattern
exactly as in Graphics II Mode.
The 768 byte Name Table is not split up into three equal sections as in Graphics II Mode but
works as in Graphics I Mode. A byte of information written anywhere in the Name Table will
select the appropriate pattern and the corresponding eight byte color entry and place it on the
screen. In Appendix C can be found the Pattern Graphics Address Location Tables.
This mode is useful because it provides the memory savings of Graphics I Mode while allowing the color detail available in Graphics II Mode. However, a unique pattern for each screen
position can no longer be defined, which is neccesary for highly detailed pictures or for bitmapping the screen. When in this mode 32 sprites can no longer be used. If you try to put
more than eight sprites on the screen at once, they will start to duplicate themselves on the
screen.
8.5
TEXT MODE
The VDP is in Text Mode when mode bits M 1 = 1, M2 = 0, and M3 = O. When in this mode the
screen is divided up into 40 horizontal blocks by 24 vertical blocks, each of which may contain a character shape (see Figure 8-7.). Each of these character positions is six horizontal
pixels by eight vertical pixels. There are only two tables required in VRAM in order to produce
a Text Mode display, these are the Name Table and the Pattern Table. No Color Table is required
in VRAM because the color of the character patterns is defined by the byte of information
contained in VDP Register 7. The upper four bits define the color of all the bits on, and the
lower four bits define the color of all the bits off. Therefore, if you had a value of Hex F 1 written to Register 7, the text colorWould be white (F) while the background would be black (1).
8-9
ACTIVE DISPLAY AREA
920 I 921 I
FIGURE 8-7 -- TEXT MODE NAME TABLE PATTERN POSITIONS
8.5.1
The Name Table

The Name Table in Text Mode is very similar to the one in Graphics I Mode except that the
screen is now 40x24 instead of 32x24 (8x8 pixel blocks). This gives 960 screen positions
and 960 (40x24 = 960) entries in our Name Table. Figure 8-8 shows the Name Table positions.
Each entry in the Name Table is one byte long and therefore can specify one of 255 (Hex FF)
patterns. If the first entry in the Name Table is Hex 00, then the first pattern defined (Pattern
00) would be displayed in the upper left hand corner of the screen. If the first Name Table entry
contains Hex FF, then the last pattern defined (Pattern FF) would be displayed in the upper left
hand corner.
ROW 0
ROW 1
ACTIVE DISPLAY AREA
ROW 22
ROW 23
FIGURE 8-8 -- PATTERN GRAPHICS NAME TABLE MAPPING
8-10
8.5.2 The Pattern Table

The Pattern Table is 2048 (Hex 8007 bytes long and is composed of 256 eight-byte patterns,
each of which may represent a text or graphics character. Since each screen position is only
six pixels across by eight pixels down instead of eight pixels across and eight pixels down as
in the graphics modes, the VDP ignores the two least significant bits of each pattern. Therefore, in Text Mode a pattern is defined as show in Figure 8-9, leaving the two LSBs set to 0s
and defining our character within the remaining 6x8 pixel block.
In order to leave a space between characters on the screen, most of the patterns defined for
Text Mode will only use a 5x7 grid. Special graphics characters might be defined for drawing
lines, graphs, and charts that use the entire 6x8 pixel grid area. A special character set for
Graphics I Mode and Graphics II Mode is included in Appendix F.
oo
o0
00
o0
oo
oo
oo
oo
UNUSED
FIGURE 8-9 -- 6X8 PIXEL PATTERN GRID FOR TEXT MODE
Up to 256 different patterns can be defined in the Pattern Table, though less space is required
if not all 256 patterns are required. For example, if your application only required numbers 0
through 9 and upper case A through Z to be defined, then only the first 36 patterns (288
bytes) would be needed. These 36 patterns would then be selected by writing numbers ranging from 0 to 36 (Hex 24) to bytes in the Name Table. If, for instance, the letter "A" was the
first pattern defined, it could be placed in every possible screen position by writing a zero to all
960 Name Table entries.
Figure 8-10 illustrates how VRAM is mapped to the Pattern Plane in Text Mode.
8-11
0
1
2
TEXT POSITION 0
~-.-40 POSITIONS ~ TEXT POSITION 39
2
N
TEXT
POSITION
M
8M+7
TEXT
PATTERN
958
959
PATTERN
NAME TABLE
24 POSITIONS
2046
2047
TEXT POSITION 959

PATTERN
GENERATOR
TABLE
I COLOR 1 I COLOR0
VDP REGISTER 7
FIGURE 8-10 -- MAPPING OF VRAM INTO THE PATTERN PLANE IN TEXT MODE
8.6
MULTICOLOR MODE
The VDP is in Multicolor Mode when the mode bits located in Registers 0 and 1 are equal to
the following:
M1 =0
M2= 1
M3 = 0
Multicolor Mode provides a low-resolution display of 64 horizontal x 48 vertical color blocks.
Each color block is equal to a 4x4 group of pixels and may be any of the sixteen VDP colors
including transparent. The Backdrop color and Sprite Planes are also active in Multicolor
Mode.
NOTE
Multicolor Mode is not supported by the Texas Instruments Advanced Video
Display Processor.
Only two tables are required in VRAM in order to produce a Multicolor Mode picture, these
being the Name Table and the Pattern Table. The Name Table consists of 768 entries like the
other graphics modes, although the Name Table no longer points to a color list because the
color of the blocks is derived from the Pattern Table. The name points to an eight-byte
segment of VRAM in the Pattern Table.
Only two bytes of the eight-byte segment area are used to specify the screen image. These
two bytes specify four colors, each occupying a 4x4 pixel area. The four MSBs of the first
byte define the color of the upper left hand corner of the multicolor pattern. The LSBs define
the color of the upper right quarter. The second byte similarly defines the lower left and right
quarters of the multicolor pattern. The two bytes thus map into an 8x8 pixel multicolor
pattern as shown in Figure 8-11.
8-12
~ 8 PIXELS
COLOR A COLOR B
8
~, PIXELS
COLOR C COLOR D
2 BYTES FROM
PATTERN GENERATOR TABLE
MULTICOLOR PATTERN
FIGURE 8-1 1 -- MAPPING AN 8X8 PIXEL MULTICOLOR PATTERN
The location of the two bytes within the eight-byte segment pointed to by the name is dependent on the screen position where the name is mapped. For names in the top row (0-31), the
two bytes are the first two in the eight-byte segments pointed to by the names. The next row
of names (32-63) uses bytes number 3 and 4 within the eight-byte segment. The next row of
names uses the 5th and 6th bytes, while the last row of names uses bytes 7 and 8. This series
repeats for the remainder of the screen.
Lets go through a step-by-step example to help clear up any uncertainties about how Multicolor Mode works. Figure 8-12 is composed of a Multicolor Mode Name Table, Pattern Table,
and a corresponding screen representation. Another screen image is also included to depict
how the 767 screen positions, each composed of four 4x4 pixel blocks, fill the screen.
In our example (see Figure 8-12), a Name Table entry of Hex 02 points to locations Hex 08 and
Hex 09. The first nibble of location Hex 08 contains the color red (Hex 06) and the second
nibble contains the color blue (Hex 04). The first and second nibbles of the second byte contain blue and red, respectively. Therefore, screen position 0 contains the four colors specified.
The calculations for this example and the others shown in Figure 8-12 are as follows.
8-13
EQUATION FOR FINDING PATTERN TABLE LOCATIONS

FIRST BYTE = 2 * ROW + NAME * 8
SECOND BYTE = FIRST BYTE + 1
ROW = MOD4[TRUNCATE(PATTERN POSITION/32)]
CALCULATIONS FOR EXAMPLES SHOWN IN FIGURE 8-12

NAME
POSITION
8-14
PATTERN
NAME
PATTERN TABLE ROWS
02
2"0+02"8 =>10(Byte1)
10+ 1 =>11(Byte2)
o0
2"0+00"8 =>OO(Bytel)
OO + 1 = >01 (Byte 2)
31
01
2*001*8=>08(Byte1)
08 + 1 = >09 (Byte 2)
32
02
2" 1 +02*8=>12(Byte1)
12+ 1 =.>13(Byte2)
767
FF
2*3+FF*8=>7FE(Bytel)
01 + 7F8 = >7FF (Byte 2)
COLUMNS
COLOR
DARK BLUF_~--~
DARK"RED
DARK GREEN
WHITE
HEX CODE
04
06
0C
OF
...
SYMBOL
B
R
G
W
30 131.
IIII
VIDEO SCREEN
ACTIVE DISPLAY AREA
DECIMAL
0
1
2
31
32
..
HEX
O2
OF
0C
0C
OF
06
04
06
O4
112
Ol
02
96
97
98
99
100
101
OF
06
04
04
OF
04
06
04
OF
"0
COLUMNS
oI
RIBW
"IRIG
3R~B
14
,O
766
767
FF
NAME TABLE
I 2046
-""-"~" ~ 2047
VIDEO SCREEN
ACTIVE DISPLAY AREA
06
OF
04
04
PATTERN TABLE
FIGURE 8-12 -- MULTICOLOR MAPPING SCHEME
The mapping of VRAM contents to screen image is simpified by using duplicate names in the
Name Table since the series of bytes used within the eight-byte segment specifies a 2x8 pixel
color square pattern on the screen as a straightforward translation from the eight-byte
segment in VRAM pointed to by the common name.
When used in this manner, 768 bytes are still used for the Name Table and 1536 bytes are
used for the color information in the Pattern Table (24 rows x 32 columns x 2-bytes/pattern
position). Thus a total of 1728 bytes (6144 + 768) in VRAM are required. It should be noted
that the tables begin on 1K and 2K boundries and are therefore not contiguous.
8-15
9.
SPRITES
Sprites are special animation-oriented patterns that can be made to move rapidly about the
screen and change shape with very little programming effort. The video display has 32 Sprite
Planes each of which contain a single sprite. These 32 Sprite Planes are numbered from 0 to
31 (see Section 2.1 ) with 0 being the highest priority or outermost Sprite Plane and 31 being
the lowest priority Sprite Plane. When more than one sprite is located at the same screen
coordinate the sprite on the higher priority plane will show through at that point. It should also
be noted that all 32 sprites have a higher priority than the Pattern Plane and the Backdrop
Plane.
Sprites come in two sizes, 8x8 pixels or 16xl 6 pixels. The size of all sprites is determined by
the size bit in VDP Register 1. Register 1 also contains a sprite magnify bit which, when set,
expands a sprite to double its normal size. Thus 8x8 sprites become 16x16, and 16x16
sprites would become 32x32. Unfortunately, when a sprite is magnified, its resolution is cut
in half because the VDP maps each single pixel into a 2x2 pixel area.
Sprite patterns are defined in individual 8x8 pixel blocks exactly as patterns in Text or the
graphics modes are. A Size 0 sprite (8x8 pixels) would require only one pattern to be defined.
A Size 1 sprite (16xl 6 pixels) is made up of four 8x8 pixel patterns. All of the bits on within a
sprite pattern are a single color, which can be any one of the 16 available VDP colors. Any bits
off within a sprite pattern are automatically set to the VDP color transparent, which allows
the Pattern Plane or Backdrop color to show through at those points. Any area within a sprite
display plane outside of the sprite itself is also set to transparent. A good way to visualize this
is to imagine a Sprite Plane as a pane of glass on which you can stick a single 8x8 or 16xl 6
pixel object.
Two tables are required in VRAM in order to produce a sprite display. The Sprite Attribute Table
tells us some characteristics of each sprite, like screen location, color, and what pattern to
pick for the shape of the sprite. The Sprite Pattern Table contains a library of sprite shape data
to choose from.
All 32 VDP sprites may be displayed on the screen at the same time, however, a maximum of
four sprites may be displayed on one horizontal line. If this rule is violated, the four highest
priority sprites will be displayed normally, while the fifth and subsequent sprites will be automatically set to transparent. Furthermore, the Fifth Sprite Flag in the VDP Status Register is
set to a 1, and the number of the violating fifth sprite is loaded into the Status Register, See
Section 5.2 for more information on fifth sprites and the Status Register.
The VDP also provides limited sprite coincidence checking. If any two active sprites have
overlapping bits, then the Coincidence Flag in the VDP Status Register will be set to a 1. It
should be noted that the VDP only tells you if any two sprites are coinciding and does not
specify the numbers of the sprites that are overlapping. Most applications that require knowing which sprites are coinciding continually monitor the Sprite Attribute Table for overlapping
values.
9.1
THE SPRITE PATTERN TABLE

The Sprite Pattern Table has a maximum length of 2048 (Hex 800) bytes and is located in
VRAM beginning on a 2K byte boundry. Its actual location in VRAM is determined by the base
address in VDP Register 6.
9-1
It takes eight bytes of information to define the pattern of a Size 0 (8x8 pixel) sprite and 32
bytes (8x4) of data to define the pattern of a Size 1 (16x16 pixel) sprite. Therefore, 256
patterns can be defined for Size 0 sprites or 64 patterns for Size 1 sprites.
The Sprite Pattern Table can be as short as eight bytes if Size 0 sprites are used and 32 bytes if
Size 1 sprites are used because the same sprite shape can be reused for as many sprites as
desired. To select the same sprite pattern just repeat the name byte located in the Sprite
Attribute Table.
9.2
THE SPRITE ATTRIBUTE TABLE

The Sprite Attribute Table contains four bytes of information for every sprite displayed. If all
32 sprites are to be displayed, then the table would have a maximum length of 128 bytes. The
location of the Attribute Table in VRAM is defined by the base address contained in VDP
Register 5.
The first four byte entry in the Sprite Attribute Table contains information pertaining to Sprite
0, which is the highest priority sprite. The last four byte entry in the Sprite Attribute Table
contains information for the lowest priority sprite, Sprite 31. Figure 9-1 illustrates how the
Sprite Attribute Table relates to the Sprite Planes.
SPRITE
ATTRIBUTE
TABLE
U
U
H
N
EC/CLR
I
t
U
H
N
EC/CLR
H
N
EC/CLR
ENTRY 0w
SPRITE
DISPLAY
PLANES
ENTRY
I SPRITE 31
ENTRY
SPRITE
U
H
N
EC/CLR
ENTRY 31
FIGURE 9-1 -- SPRITE ATTRIBUTE TABLE AS RELATED TO SPRITE PLANES
9-2
Referring to Figure 9-2, lets examine one four byte attribute entry. The first two bytes determine the coordinate of the sprite on the display screen. The first byte is the vertical position
and the second byte is the horizontal position. The third byte is the sprite name and specifies
what pattern in the Sprite Pattern Table will be used as the sprites shape. The fourth byte
performs two functions: the lower four bits (nibble) determine the color of the sprite and the
Early Clock bit (MSB) shifts the horizontal position of the sprite towards the left 32 pixels.
Setting this bit high allows sprites to bleed (flow smoothly) off the left side of the screen. The
other three bits in this fourth byte are unused and should be set to zeros.
BIT NUMBER
MSB
LSB
0
1
2
3
4
5
6
7
VERT.
VERT.
VERT.
VERT.
VERT.
VERT.
VERT.
VERT.
I BYTE 0
VERTICAL COORDINATE
POSN.
POSN.
POSN. POSN. POSN.
POSN.
POSN. POSN.
HORIZONTAL COORDINATE HORIZ. HORIZ. HORIZ. HORIZ. HORIZ. HORIZ. HORIZ. HORIZ. f BYTE 1
POSN.
POSN.
POSN. POSN.
POSN.
POSN.
POSN. POSN.
SPRITE NAME POINTER NAME
COLOR AND EARLY CLOCK BIT, EARLY
CLOCK
NAME
NAME
NAME
0
NAME
COLOR
NAME
NAME
COLOR
NAME
BYTE 2
COLOR COLOR BYTE 3
FIGURE 9-2 -- SPRITE ATTRIBUTE TABLE ENTRY
9.2.1
Vertical Position
The first attribute byte of information is the vertical position of the sprite on the display
screen. This coordinate determines the distance the sprite will be offset from the top of the
screen in pixels. The position of a sprite is measured relative to the upper left hand corner of
the sprite. A value of -1 (Hex FF) in the vertical position will butt a sprite up against the top of
the screen, and a value of 191 (Hex BF) will position the sprite off the screen at the bottom as
shown in Figure 9-3. Negative values can be used to bleed the sprite off the top edge of the
screen. Values in the range of -32 and -1 (Hex E0 to FF) allow even the largest sprite (32x32
pixels) to bleed in from the top of the screen.
-SPRITE POSITION
COORDINATE = 00
Y COORDINATE = BF
POSITION
X COORDINATE = 00
Y COORDINATE = FF
BACKDROP COLOR
BACKDROPCOLOR
FIGURE 9-3 -- VERTICAL SPRITE POSITIONING
9-3
Some applications require no sprites or less than 32 sprites to be displayed at a time. A value
of Hex DO in the vertical position of the Sprite Attribute Table will terminate sprite processing.
If no sprites are to be used, Hex DO should be the first entry in the Sprite Attribute Table. If only
one sprite is to be used, then Hex DO should be the first byte in the second sprites attribute
entry, which would be the fifth byte in the Sprite Attribute Table. Once the VDP finds a value
of Hex DO as a sprite attribute entry, it terminates processing of that sprite and all lower priority sprites.
9.2.2
Horizontal Position
The second byte of information in the Sprite Attribute Table is the horizontal coordinate. This
value determines the distance the sprite will be offset in pixels from the left hand side of the
screen. A value of Hex O0 will butt a sprite up against the left hand edge of the screen, while a
value of 255 (Hex FF) will position the sprite completely off the right hand side of the screen
as shown in Figure 9-4. Using values in the range of 255 (Hex FF) will bleed a sprite off the
right hand edge of the display screen.
COORDINATE = 00
Y COORDINATE = FF
BACKDROP COLOR
SPRITE
C,
COORDINATE = FF
BACKDROP COLOR
FIGURE 9-4 -- HORIZONTAL SPRITE POSITIONING
In order to bleed a sprite off the left hand edge of the screen, a special bit called the Early Clock
bit is used. This bit is the fourth byte of an attribute entry and is described later in this section.
9.2.3
Sprite Name
The third byte of information contained in a sprite attribute entry is the sprite name. The function of this byte is very similar to the function of a Name Table entry in the graphics modes.
The value contained in this byte determines which pattern will be used as the sprites shape. It
points to a byte of information in the Pattern Table where the start of the sprites pattern is
located.
9-4
EXAMPLE 9-1.
8x8 (Size O) Sprites
A value of Hex O0 as a Sprite Name Table entry would mean the first eight bytes in the Pattern
Table would be used as the sprites shape. A value of Hex 01 would choose the next eight
bytes in the Sprite Pattern Table as the sprites shape. Continuing on up to Hex FF gives us
256 8x8 pixel sprite shapes to choose from.
EXAMPLE 9-2.
16x16 (Size 1 ) Sprites
The value in the Sprite Name Table entry points to an eight-byte entry in the Sprite Pattern
Table. Since a 16xl 6 pixel sprite is made up of four eight byte entries, our name values would
be entries such as Hex 00,04,08,0C, 10 etc. When the sprite Size 1 bit is set in VDP Register
1, the VDP will go to the eight-byte block pointed to by the sprite name and choose the next
four eight byte entries in the Pattern Table as the sprites shape.
Having the sprite pattern selectable by the sprite name makes for extremely simplified animation. For example, if the first four sprite patterns are defined as the graphic stages for a man
walking, we could switch through these patterns and animate the man just by switching the
sprite name values from 0-3 and then repeating the sequence.
9.2.4
Sprite Color and Early Clock Bit

The fourth byte in the Sprite Attribute Table entry performs two functions. The lower four bits
(nibble) define the sprite color, which can be any of the 16 available VDP colors. The MSB is
the Early Clock bit, which shifts the horizontal position of the sprite to the left 32 pixels (when
set high). The remaining three bits are unused and should be set to 0.
The Early Clock bit is used to bleed a sprite off the screen or onto the screen from the left hand
edge. When this bit is active (high), the horizontal position of the sprite is shifted to the left 32
pixels. Consider the horizontal position of a sprite being Hex 00, which butts the sprite up
against the left hand edge of the screen. If the Early Clock bit is then set, even the largest
sprite (32x32 pixels) would be completely off the screen. This allows values in the horizontal
position in the range of 0 to 31 to bleed a sprite onto the left hand edge. Of course the Early
Clock bit must be set low again in order to be able to bleed the sprite off the right-hand edge.
Now that all the information on sprites has been covered, refer to Figure 9-5 for an illustration
of how sprites are mapped to the screen.
9-5
SCREEN
VRAM
X
NAME
EC/COLOR
SPRITE
VRAM
SPRITE
ATTRIBUTE
TABLE
SPRITE
DATA
SPRITE
PATTERN
TABLE
FIGURE 9-5 -- SPRITE MAPPING
9-6
10.
PROGRAMMING TIPS
10.1
HORIZONTAL AND VERTICAL SCROLLING

The simplest way to scroll the pattern plane display is to manipulate the values located in the
Name Table. The only drawback to this method is that the screen will move in increments
larger than one pixel. In Graphics I, II and Multicolor Modes the movement will be in eight pixel
increments. In Text Mode the movement will be by six pixels when scrolling horizontally and
eight pixels when scrolling vertically. The movement is determined by the size of a single pattern.
One major advantage to this method is that only a small number of bytes need to be moved in
order to scroll the entire display. In Graphics I,II, and Multicolor Modes the Name Table is 768
bytes long, and in Text Mode the Name Table is 960 bytes long. Figure 10-1 shows the
sequence for scrolling the Name Table left with screen wraparound. The Name Table in this
figure has 768 entries and is designed for scrolling the screen in Graphics I or Graphics II
Modes. Referring to the figure we can see that the steps involved in scrolling are as follows:
1)
Read the data located in column 0 from VRAM and store it. The data consists of entries
numbered 000,032,064,096 ....736.
2) Read the data located in column 1 and write it to column O. Read column 2 and write to
column 1, and so forth, until column 31 has been read and moved to column 30.
3) Take the data stored from column 0 and write to column 31. The screen has now scrolled
one column (eight pixels) to the left and wrapped around the screen.
4) Repeat this sequence to continually scroll the screen.
097 J 098 |
_[641
:673
642
674
.-i 70s 706
I 126 I 127
125
733 734 735

765 766 767
FIGURE 10-1 -- SCROLLING THE NAME TABLE
10-1
10.2
ANIMATING SPRITES
The procedure for animating a sprite is relatively simple. First load the sprite pattern data for
the sprites you wish to animate into the Sprite Pattern Table located in VRAM. Next load sprite
attribute data into the Sprite Attribute Table located in VRAM. In this example we will talk
about animating two sprites, one of which is a man walking and the other being a rotating
planet. The sequence of shapes used for this exercise are shown in Figure 1 0-2 and Figure
10-3.
STAGE 1
STAGE 2
STAGE 3
FIGURE 10-2 -- ANIMATED WALKING MAN
SPRITE 1
SPRITE 2
SPRITE 3
SPRITE 4
SPRITE 5
SPRITE 6
SPRITE 7
SPRITE 8
SPRITE OVERLAY
FIGURE 10-3 -- ANIMATED PLANET
10-2
Referring to Figure 10-2 we can see that the walking man is a Size 1 sprite consisting of three
stages of animation. The Hex data for these shapes is shown as the first three entries in Table
10-1, which is an example of what our source code listing might look like. The rotating planet
is also a Size 1 sprite (see Figure 10-3) and consists of eight stages of animation. The data for
these eight shapes is shown as the next eight entries in Table 10-1.
Since the rotating planet shapes were drawn as flat, square planets, a sprite overlay pattern is
used in Figure 10-4 to make the planets look rounded. Figure 10-4 shows what the planets
would look like with this sprite overlaid on top of them. The data for the overlay sprite is the
last pattern entry in Table 10-1.
SPRITE 1
SPRITE 2
SPRITE 3
SPRITE 4
SPRITE 5
SPRITE 6
SPRITE 7
SPRITE 8
SPRITE OVERLAY
FIGURE 10-4 -- ANIMATED PLANET WITH OVERLAY
Now that all the graphic data for our sprites has been defined we need to create a Sprite Attribute Table in order to have them displayed on the screen. Referring to the section of Table
10-1 labeled Sprite Attribute Table, you will see that three Sprite Attribute Table entries have
been defined. The first four bytes define the first entry, which is the highest priority sprite
(Sprite 0). This is the sprite used for the animated walking man.
An actual program to animate the man would change the name byte from Hex O0 to Hex 04 to
Hex 08. This would shift the sprite through each of the pattern stages defined earlier. Hex O0
is the initial name value because Stage 1 of the walking man shape starts at byte O0 in the
Sprite Pattern Table.
10-3
The next two Sprite Attribute Table entries (Sprites 1 and 2) are used to define the rotating
planet. The spherical overlay is defined as a higher priority sprite than the rotating planet. This
enables us to mask off bits around the square edges of the planet in order to make it appear
round.
The spherical overlay name byte is set to Hex 2C because the pattern data for it falls on byte
number 2C in the Sprite Pattern Table. This byte would remain the same in a program that
animated the planet. If the horizontal and vertical positions of the rotating planet were
changed during program execution, the horizontal and vertical positions of the overlay would
have to be changed also.
The third Sprite Attribute Table entry (Sprite 2) is for the different stages of the rotating planet
animation. The initial setting of 0 points to the pattern which falls on byte O in the Sprite
Pattern Table. This is stage 1 of the rotating planet. During the course of a program we would
shift the name byte through all eight stages of planet animation. Referring to the Pattern Table
we can see that the values are OC, 1 O, 14,18,1C,20,24,28. After shifting through all eight
patterns the sequence would be repeated.
TABLE 10-1 - ANIMATION EXAMPLE DATA
(* SPRITE PATTERN TABLES *)
3 Stage Animation for "Man Walking" Sprite

DATA
DATA
DATA
DATA
>0103,>0303,>0103,>0305
>0F03,>0307,>070E,>0C06
>C0A0,>E0C0,>80C0,>FOF8
>C0C0,>F070,>6030,>0000
Sprite Name = 00
(Man Walking. Stage 1)
DATA
DATA
DATA
DATA
>0103,>0303,>0103,>0307
>0303,>0307,>0E0C,>0800
>COA0,>E0C0,>80C0,>EOA0
>C0C0,>C0C0,>C0C0,>C060
Sprite Name = 04
(Man walking. Stage 2)
DATA
DATA
DATA
DATA
>0103,>0303,>0103,>0305
>0503,>0307,>0503,>0303
>C0A0,>E0C0,>80C0,>C0A0
>A0C0,>EOEO,>8080,>0080
Sprite Name = 08
(Man walking. Stage 3)
8 Stage Animation for "Rotating Planet"
10-4
DATA
DATA
DATA
DATA
>0003,>070F,>07A3,>F1F0
>FOE0,>801C,>0C02,>O000
>0000,>8098,>0C41,>2303
>075F,>3F1E,>3E1C,>0800
Sprite Name = 0C
(Rotating Planet. Stage 1)
DATA
DATA
DATA
DATA
>0000,>0103,>0168,>FCFC
>FCF8,>E007,>0300,>0000
>00C0,>EOE6,>C2D0,>4800
>0117,>0F06,>0E84,>0000
Sprite Name = 10
(Rotating Planet. Stage 2)
DATA
DATA
DATA
DATA
>0000,>0000,>401A,>3F3F
>7EFE,>F860,>6100,>0000
>0030,>78F8,>7034,>1200
>0005,>0300,>C2C0,>2000
Sprite Name = 14
Rotating P anet
Stage 3)
DATA
DATA
DATA
DATA
>O000,>0060,>3006,>8FOF
>1F7F,>FE78,>7830,>0000
>0008,>IC3E,>IC8D,>C4CO
>C181,>0000,>7030,>0800
Sprite Name = 18
Rotating P anet
Stage 4)
DATA
DATA
DATA
DATA
>0000,>0018,>0C41,>2303
>075F,>3F1E,>3E1C,>0800
>0000,>040E,>O6A3,>F1F0
>FOE0,>8000,>ICOC,>0000
Sprite Name = 1C
Rotating P anet
Stage 5)
DATA
DATA
DATA
DATA
>0000,>2066,>43D0,>4800
>0117,>0F07,>OF07,>0200
>O000,>0002,>0068,>FCFC
>FCF8,>E080,>8600,>0000
Sprite Name = 20
Rotating P anet
Stage 6)
DATA
DATA
DATA
DATA
>0010,>3879,>7034,>1200
>0005,>0301,>0301,>0000
>O000,>0080,>C01A,>3F3F
>7FFE,>F8E0,>EOC0,>8000
Sprite Name = 24
Rotating P anet
Stage 7)
DATA
DATA
DATA
DATA
>000C,>IE3E,>IC8D,>C4C0
>(3081,>0000,>7030,>0800
>O000,>0060,>3006,>8FOF
>1F7F,>FE78,>F870,>2000
Sprite Name = 28
Rotating P anet
Stage 8)
DATA
DATA
DATA
DATA
>071F,>3F7F,>7FFF,>FFFF
>FFFF,>FF7F,>7F3F,>IF07
>EOF8,>FCFE,>FEFF,>FFFF
>FFFF,>FFFE,>FEFC,>F8E0
Sprite Name = 2C
(Spherical Overlay)
(* SPRITE ATTRIBUTE TABLE *)
Attribute table entry for "Man Walking"

(The Name Byte will be either 00,04, or 08)
BYTE >00
BYTE >00
BYTE >00
BYTE >OF
Y Coordinate
X Coordinate
Name
EC/Color = White
Attribute table entry for "Spherical Overlay"

(The Name Byte will always be 2C)
BYTE >00
BYTE >00
BYTE >2C
BYTE >01
Y Coordinate
X Coordinate
Name
EC/Color = Black
10-5
Attribute table entry for "Rotating Planet"

(The Name Byte will either be 0C,10,14,18
lC,20,24, or 28)
BYTE >00
BYTE >00
BYTE >0C
BYTE >04
END
10.3
Y Coordinate
X Coordinate
Name
EC/C01or = Blue
SPRITE COINCIDENCE
The Sprite Coincidence Flag, located in the Status Register, is set whenever any two sprites
have overlapping pixels. Most applications need to know not only that sprites have coincided,
but which ones in particular are coinciding. A good example of this is the rotating planet sprite
just described.
Since we actually defined two sprites for this shape (Sprite 1 and 2) to be located directly on
top of one another on the screen, the Coincidence bit in the Status Register would be set all
the time. If we wanted to monitor coincidence between the rotating planet and the walking
man sprite, it would be necessary to keep track of their screen position in our program. This
can be done by reading the X and Y coordinates of every Sprite Attribute Table entry and then
comparing them to each other. In the case of the man and planet, if the first two bytes of
attribute entry 1 (sprite O) were the same as the first two bytes of attribute entry 2 (sprite 1 ),
then we would know the man was positioned exactly on top of the planet.
10-6
APPENDIX A
REGISTER VRAM LOOKUP TABLES
Covers Registers 2-6 with special case diagrams for Registers 3 and 4 when in Graphics II
Mode.
R2 * 400(16) = START ADDRESS
R2
START
ADDRESS
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
OF
0000
0400
0800
0C00
1000
1400
1800
lC00
2000
2400
2800
2C00
3000
3400
3800
3C00
A-1
(R3)* 40(16) STARTING ADDRESS
R3
O0
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
START
ADDRESS
0000
0040
0080
00C0
0100
0140
0180
01C0
0200
0240
0280
02C0
0300
0340
0380
03C0
0400
0440
0480
04C0
0500
0540
0580
05C0
0600
0640
0680
06C0
0700
0740
0780
07C0
0800
0840
0880
08C0
0900
0940
0980
09C0
OAO0
OA40
OA80
R3
2B
2C
2D
2E
2F
3O
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
START
ADDRESS
0AC0
0BO0
0B40
0B80
0BC0
0CO0
0C40
0C80
0CC0
0D00
OD40
0D80
0DC0
OEO0
0E40
0E80
0EC0
0FO0
0F40
0F80
OFC0*
1000
1040
1080
10C0
1100
1140
1180
11C0
1200
1240
1280
12C0
1300
1340
1380
13C0
1400
1440
1480
14C0
1500
1540
R3
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
START
START
ADDRESS R3
ADDRESS
81
2040
1580
82
2080
15C0
1600
83
20C0
1640
84
2100
85
2140
1680
16C0
86
2180
1700
87
21C0
1740
88
2200
1780
89
2240
17C0
8A
2280
1800
8B
22C0
1840
8C
2300
1880
8D
2340
18C0
8E
2380
1900
8F
23C0
1940
2400
90
1980
91
2440
19C0
92
2480
1A00
93
24C0
1A40
94
2500
1A80
2540
95
1AC0
96
2580
1B00
97
25C0
1B40
98
2600
1B80
2640
99
1BCO
9A
2680
1C00
9B
26C0
1C40
9C
2700
2740
1C80
9D
1CCO
9E
2780
1D00
9F
27C0
1D40
2800
A0
1D80
A1
2840
1DC0
A2
2880
1E00
A3
28C0
1E40
A4
2900
1E80
2940
A5
1ECO
A6
2980
1FO0
A7
29C0
1F40
A8
2A00
1F80
A9
2A40
1FC0
AA
2A80
2000
2AC0
AB
R3
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
D1
D2
D3
D4
D5
REGISTER 3 ADDRESSING FOR GRAPHICS II MODE
R3
7F
FF
A-2
START
ADDRESS
0000
2000
START
ADDRESS
2BOO
2B40
2B80
2BC0
2C00
2C40
2C80
2CC0
2D00
2D40
2D80
2DCO
2EO0
2E40
2E80
2EC0
2F00
2F40
2F80
2FC0
3000
3040
3080
30C0
3100
3140
3180
31C0
3200
3240
3280
32C0
3300
3340
3380
33C0
3400
3440
3480
34C0
3500
3540
R3
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
START
ADDRESS
3580
35C0
3600
3640
3680
36C0
3700
3740
3780
37C0
~j~800
3840
3880
38C0
3900
3940
3980
39C0
3A00
1A40
3A80
3AC0
3B00
3B40
3B80
3BCD
3C00
3C40
3C80
3CC0
2D00
3D40
3D80
3DC0
3E00
3E40
3E80
3ECO
3F00
3F40
3F80
3FCO
(R4) * 800(16) = START ADDRESS
R4
00
01
02
03
04
05
06
07
REGISTER 4 ADDRESSING FOR GRAPHICS II MODE
START
ADDRESS
R4
03
07
0000
0800
1000
1800
2000
2800
3000
3800
START
ADDRESS
0000
2000
(R5) * 80(16) = START ADDRESS

R5
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
START
ADDRESS
0000
0080
0400
0180
0200
0280
0300
0380
0400
0480
0500
0580
0600
0680
0700
078O
0800
0880
0900
0980
0A00
0A80
0B00
0B80
0C00
0C80
0 D00
0D80
0E00
0E80
0F00
0F80 *
1000
R5
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
START
ADDRESS
1080
1100
1180
1200
1280
1300
1380
1400
1480
1500
1580
1600
1680
1700
178O
1800
1880
1900
198O
1A00
1 A80
1 BOO
1 B80
1 COO
1 C80
1D00
1D80
1 E00
1E80
1 F00
1F80
R5
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
START
ADDRESS
2OOO
2080
2100
2180
2200
2280
2300
2380
2400
2480
2500
2580
2600
2680
2700
2780
2800
2880
2900
2980
2A00
2A80
2B00
2B80
2C00
2C80
2D00
2D80
2E00
2E80
2F00
2F80
R5
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
START
ADDRESS
3000
3080
3100
3180
3200
3280
3300
3380
3400
3480
3500
3580
3600
3680
3700
3780
380O
3880
3900
3980
3A00
3A80
3B00
3B80
3C00
3C80
3D00
3D80
3E00
3E80
3F00
3F80
A-3
STARTING ADDRESS = R6 *<800
A-4
R6
START
ADDRESS
00
01
02
03
04
05
06
07
0000
0800
1000
1800
2000
2800
3000
3800
APPENDIX B
B=
CPU TO VDP ACCESS TIMES
CONDITION
MODE
VDP
DELAY
TIME WAITING FOR

AN ACCESS WINDOW
TOTAL
TIME
0- 1.1 Us
2 -3.1 /~s
Active Display Area
Text
Active Display Area
Graphics
I, II
2/~s
4300 Us after Vertical

Interrupt Signal
All
2 Us
0/~s
Register I
Blank Bit 0
All
0/~s
Active Display Area
Multicolor
2~s
0 - 5.95
0- 1.5~s
2 -8/~s
2 us
2- 3.5 ~s
B-1
APPENDIX C
PATTERN GRAPHICS ADDRESS LOCATION TABLES
GRAPHICS I MODE ADDRESS LOCATION
ADDRESS TYPE
1)
2)
3)
PATTERN
NAME
ADDRESS
COMMENTS
NTB
COLUMN
PATTERN
COLOR
ADDRESS
PATTERN
GENERATOR
ADDRESS
PATTERN NAME TABLE BASE (VDP REG2)

PATTERN POSITION
ROW
COLB
PGB1
NAME
NAME (0-4)
I xxx
PATTERN COLOR TABLE BASE (VDP REG3)

ALWAYS "0" IN BIT 8
FIVE MOST SIGNIFICANT BITS OF NAME
PATTERN GENERATOR TABLE BASE (VDP REG4)
ALL 8 BITS OF NAME
THREE LSBS FORM PATTERN ROW POSITION
GRAPHICS II MODE ADDRESS LOCATION

ADDRESS TYPE
1)
2)
3)
PATTERN
NAME
ADDRESS
COMMENTS
NTB
ROW
COLUMN
PATTERN
COLOR
ADDRESS
xxx
PATTERN COLOR TABLE BASE MSB (VDP REG3)

TWO MSB FROM VERTICAL COUNTER
ALL 8 BITS OF NAME
COLOR TABLE BYTE/LINE
XXX
PATTERN GENERATOR TABLE BASE BIT 5 (VDP REG4

TWO MSB FROM VERTICAL COUNTER
ALL 8 BITS OF NAME
PATTERN GENERATOR BYTE/LINE NUMBER
NAME
PATTERN
GENERATOR
ADDRESS

PATTERN POSITION ROW
PATTERN POSITION COLUMN
NAME
TEXT MODE ADDRESS LOCATION

ADDRESS TYPE
TEXT MODE PATTERN
NAME ADDRESS
TEXT MODE
PATTERN
GENERATOR
ADDRESS
COMMENTS
NTB
TEXT POSITION
PGB
NAME
~ XXX

EQUAL (TEXT POSITION ROW #TIMES 40) PLUS
(TEXT POSITION COLUMN NUMBER)
NAME
BYTE/ROW NUMBER
C-1
SPRITE ADDRESS LOCATION

ADDRESS TYPE
COMMENTS
SPRITE
ATTR I B UTE
ADDRESS
SIZE = 0
SPRITE PATTERN
GENERATOR
SIZE = 1
SPRITE PATTERN
GENERATOR
SAB
SPRITE
JXX
SPGB
NAME
{ XXX
SPGB
NAME(0-5)
XXXXX
SPRITE ATTRIBUTE TABLE BASE (VDP REGS)

SPRITE NUMBER
ATTRIBUTE NUMBER:
00 FOR VERTICAL POSITION
01 FOR HORIZONTAL POSITION
10 FOR NAME
11 FOR TAG (EARLY CLOCK AND COLOR)
SPRITE PATTERN GENERATOR BASE (VDP REG4
NAME ATTRIBUTE OF SPRITE
THREE LSBS GIVE BYTE/ROW NUMBER
SPRITE PATTERN GENERATOR BASE (VDP REG4
SIX MSB OF NAME
0 FOR LSB OF PATTERN, 1 FOR MSB OF PATTERF
SIZE = 1 SPRITE BYTE NUMBER
MULTICOLOR ADDRESS LOCATION

ADDRESS TYPE
4)
5)
C-2
COMMENTS
MULTICOLOR
PATTERN NAME
ADDRESS
NTB
MULTICOLOR
PATTERN
GENERATOR
,ADDRESS
PGB
ROW
COLUMN
NAME
xxx

PATTERN POSITION ROW
PATTERN POSITION COLUMN
NAME FROM NAME FETCH
THREE LSBS FORM BYTE/SQUARE ROW
APPENDIX D
IC PINOUTS FOR TMS9918A/28A/29A AND TMS9118/28/29
D=
TMS9128/9129
XTAL1
XTAL2
AD7 r
AD6 ~"
AD5 E
CPUCLKt
NCt
R-~
~ "] XTAL1
C-"-~[ 2
AD7 3
AD6 4
ADSr~ 5
AD4 6
AD3 r
AD2 E
COMVIDtt
EXTVDP
RESET/SYNC
Vcc
RDO
ADO F
RD I
AD1
ADO
9
10
VsS ~"
RD2
RD3
R/~
VSS
RD4
RD5
MODE__
CSW
11
12
13
AD4
MODE r
cs--~ [
AD3L~ 7
AD2 8
14
.06
cs--~E15
RD7
I-~" E 16
17
CD7
CD6 18
CD5 19
CD7 {"
CDB I-
CDO
CD1
CD5 r
CD4 ["
CD2
CD3
CD4
20
TMS9918A
RAj{- ~ "1XTAL1
39 ] XTAL2
38 ]R-Yt
CASr" 2
AD7r 3
37 ] CPUCLK t
3e
35 "] B-yt
AD6 {" ~
ADSr" 5
34 "1 RE---~~!SYNC
33 "1 VCC
32 "1 RDO
31l RD1
3(] "1 RD2
29 3 RD3
28 "l RD4
27 "IRD5
2E 1 RD6
25 "1 RD7
24 "J CD0
23 ] CD1
22 ] CD2
2~1 "l CD3
AD4r 5
AD3r" 7
AD2r E}
39 "l XTAL2
39 3 CPUCLK t
37 "1 GROMCLK t
3~ "1COMVIDt
35 3 EXTVDpt
34 "1RESET/SYNC
AD1 r ~
ADO r 10
33 "1Vcc
3; "1RD0
31 "IRD1
11
Vss r 12
MODE r 13
14
3C 3RD2
2c- "IRD3
2~ "1 RD4
23 "1RD5
15
16
CD7 {" 17
CD6 r 18
2e "]RD6
2-~ -1RD7
24 -1CDO
2~ -1CD1
2:3CD2
21 "1 CD3
CD5 F 19
CD4 [ 20
TMS9928A/9929A
~--~1" ~ "1XTAL1
~--~[" 2
39 1XTAL2
38 3R-y1"
AD7F 3
AD6{~ 4
37 1 GROMCLKt
5
AD4
6
AD3r 7
AD2 E 8
36 "lyt
35 ] B.yt
34 ] R-~T/SY N C
33 "1Vcc
32 "1 RDO
9
ADO ~10 31 ]RD1
R~ 11
"] RD2
vssr" 12 2g "1RD3
MODE I" 13
CSW r 14
15
"1 RD4
27 "1RD5
16
17
2{~ "]RD6
25 "1RD7
24 ] CDO
CD6 r" 18
CD5 r" 19
CD4 {" 20
22 "1CD2
2! "1 CD3
-E
INT
CD7
23 "} CD1
~Pins 35 to 38 are the only pins which vary for each device.
D-1
NSIRUMENTS

Ti VDP Programmers Guide PDF

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What are the different display modes described in the document?

What are the different display modes described in the document?

How does the document describe communicating between the CPU and VDP?

How does the document describe communicating between the CPU and VDP?

Video

COMMUNICATION BREAKDOWN ......................................

THE DIFFERENT DISPLAY MODES ......................................

PROGRAMMING TIPS ..............................................

REGISTER VRAM LOOKUP TABLES .....................................

VDP Flow of Operation ..............................................

Sprite Mapping ....................................................

VDP Color Assignments .............................................

GENERAL VDP OPERATION

FIGURE 1-1 -- VDP FLOW OF OPERATION

B~C KD ROP PLANE

FIGURE 2-1 -- VDP DISPLAY PLANES

Cyan (Aqua Blue)

FIGURE 3-1 - CPU TO VDP INTERFACE

CPU TO VDP INTERFACE

TABLE 3-1 -- CPU TO VDP DATA TRANSFERS

Read from VRAM

Write to VDP register

Read VDP Status Register

TALKING TO THE VDP

WRITING TO THE VDP REGISTERS

CSR CSW MODE

READING THE VDP STATUS REGISTER

WRITING AND READING VRAM

Transfer lower eight bits of address to MODE HIGH.

Read from VRAM

Transfer lower eight bits of address to MODE HIGH.

CSR CSW MODE

DESCRIPTION OF THE VDP REGISTERS

Register 0 (Contains Two VDP Control Bits)

Bit 6 = M3 (Pattern Mode Bit 3)

Bit 7 = External VDP Plane Enable/Disable

Register I (Contains Eight VDP Control Bits)

Bit 0 = 4/16K Selection

14--BIT VDP ADDRESS

14-BIT VDP ADDRESS

14--BIT VDP ADDRESS

14--BIT VDP ADDRESS

14-BIT VDP ADDRESS

READ-ONLY STATUS REGISTER

FIFTH SPRITE NUMBER

Interrupt Flag (F)

Coincidence Flag (C)

Fifth Sprite Flag (5S) and Number

INITIALIZING THE VDP

SET UP VDP ADDRESS

GET DATA FROM SYSTEM RAM

SEND DATA TO VDP (MODE HIGH)

SEND VDP THE REGISTER NUMBER

FIGURE 6-1 -- REGISTER INITIALIZATION

CHOOSING THE RIGHT MODE

Graphics I Mode Initialization

Graphics I Mode,No External Video

16K,Enable Display, Disable Int.,8x8 Sprites,Mag.Off

Address of Name Table in VRAM = Hex 1400