Doc4180 PDF

Features
80C52 Compatible
8051 Pin and Instruction Compatible

Four 8-bit I/O Ports
Three 16-bit Timer/Counters
256 Bytes Scratch Pad RAM
9 Interrupt Sources with 4 Priority Levels
Dual Data Pointer
Variable Length MOVX for Slow RAM/Peripherals
ISP (In-system Programming) Using Standard VCC Power Supply
Boot ROM Contains Low Level Flash Programming Routines and a Default Serial
Loader
High-speed Architecture
In Standard Mode:
40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
In X2 mode (6 Clocks/machine cycle)
20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
16K/32K Bytes On-chip Flash Program/Data Memory
Byte and Page (128 Bytes) Erase and Write
100K Write Cycles
On-chip 1024 Bytes Expanded RAM (XRAM)
Software Selectable Size (0, 256, 512, 768, 1024 Bytes)
256 Bytes Selected at Reset for TS87C51RB2/RC2 Compatibility
Keyboard Interrupt Interface on Port P1
SPI Interface (Master/Slave Mode)
8-bit Clock Prescaler
Improved X2 Mode with Independent Selection for CPU and Each Peripheral
Programmable Counter Array 5 Channels
High-speed Output
Compare/Capture
Pulse Width Modulator
Watchdog Timer Capabilities
Asynchronous Port Reset
Full Duplex Enhanced UART
Dedicated Baud Rate Generator for UART
Low EMI (Inhibit ALE)
Hardware Watchdog Timer (One-time Enabled with Reset-out)
Power Control Modes
Idle Mode
Power-down Mode
Power-off Flag
Power Supply:
2.7 to 3.6 (3V Version)
2.7 to 5.5V (5V Version)
Temperature Ranges: Commercial (0 to +70C) and Industrial (-40C to +85C)
Packages: PDIL40, PLCC44, VQFP44
8-bit
Microcontroller
with 16K/
32K Bytes Flash
AT89C51RB2
AT89C51RC2
Description
The AT89C51RB2/RC2 is a high-performance Flash version of the 80C51 8-bit microcontrollers. It contains a 16K or 32K Bytes Flash memory block for program and data.
The Flash memory can be programmed either in parallel mode or in serial mode with
the ISP capability or with software. The programming voltage is internally generated
from the standard VCC pin.
Rev. 4180E805110/06
The AT89C51RB2/RC2 retains all features of the 80C52 with 256 Bytes of internal
RAM, a 9-source 4-level interrupt controller and three timer/counters.
In addition, the AT89C51RB2/RC2 has a Programmable Counter Array, an XRAM of
1024 Bytes, a Hardware Watchdog Timer, a Keyboard Interface, an SPI Interface, a
more versatile serial channel that facilitates multiprocessor communication (EUART)
and a speed improvement mechanism (X2 mode).
The Pinout is the standard 40/44 pins of the C52.
The fully static design reduces system power consumption of the AT89C51RB2/RC2 by
allowing it to bring the clock frequency down to any value, even DC, without loss of data.
The AT89C51RB2/RC2 has 2 software-selectable modes of reduced activity and 8-bit
clock prescaler for further reduction in power consumption. In Idle mode, the CPU is frozen while the peripherals and the interrupt system are still operating. In power-down
mode, the RAM is saved and all other functions are inoperative.
The added features of the AT89C51RB2/RC2 make it more powerful for applications
that need pulse width modulation, high speed I/O and counting capabilities such as
alarms, motor control, corded phones, and smart card readers.
Table 1. Memory Size
Part Number
Flash (Bytes)
XRAM (Bytes)
TOTAL RAM
(Bytes)
I/O
AT89C51RB2
16K
1024
1280
32
AT89C51RC2
32K
1024
1280
32
AT89C51IC2
32K
1024
1280
32
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Block Diagram
(2) (2)
XTAL1
XTAL2
(1)
EUART
+
BRG
ALE/ PROG
RAM
256x8
C51
CORE
PSEN
Flash
32Kx8 or
16Kx8
XRAM
1Kx8
Boot
ROM
2Kx8
(1) (1)
PCA
T2
T2EX
PCA
ECI
Vss
VCC
TxD
RxD
Figure 1. Block Diagram
(1)
Timer2
IB-bus
CPU
EA
Timer 0
Timer 1
(2)
Notes:
INT
Ctrl
Parallel I/O Ports & Ext. Bus
Watch Key
Dog Board
SPI
SS
MOSI
SCK
MISO
P3
P2
P1
(1) (1) (1) (1)

P0
INT1
(2) (2)
T1
(2) (2)
INT0
Port 0 Port 1 Port 2 Port 3
RESET
WR
(2)
T0
RD
1. Alternate function of Port 1.

2. Alternate function of Port 3.
3
4180E805110/06
SFR Mapping
The Special Function Registers (SFRs) of the AT89C51RB2/RC2 fall into the following
categories:
C51 core registers: ACC, B, DPH, DPL, PSW, SP
I/O port registers: P0, P1, P2, P3
Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,
RCAP2L, RCAP2H
Serial I/O port registers: SADDR, SADEN, SBUF, SCON
PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH,
CCAPxL (x: 0 to 4)
Power and clock control registers: PCON
Hardware Watchdog Timer registers: WDTRST, WDTPRG
Interrupt system registers: IEN0, IPL0, IPH0, IEN1, IPL1, IPH1
Keyboard Interface registers: KBE, KBF, KBLS
SPI registers: SPCON, SPSTR, SPDAT
BRG (Baud Rate Generator) registers: BRL, BDRCON
Flash register: FCON
Clock Prescaler register: CKRL
Others: AUXR, AUXR1, CKCON0, CKCON1
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Table 2. C51 Core SFRs

Mnemonic
Add
Name
ACC
E0h
Accumulator
F0h
B Register
PSW
D0h
Program Status Word
SP
81h
Stack Pointer
DPL
82h
Data Pointer Low Byte
DPH
83h
Data Pointer High Byte
CY
AC
F0
RS1
RS0
OV
F1
Table 3. System Management SFRs

Mnemonic
Add
Name
PCON
87h
Power Control
SMOD1
SMOD0
POF
GF1
GF0
PD
IDL
AUXR
8Eh
Auxiliary Register 0
DPU
M0
XRS2
XRS1
XRS0
EXTRAM
AO
AUXR1
A2h
Auxiliary Register 1
ENBOOT
GF3
DPS
CKRL
97h
Clock Reload Register
CKRL7
CKRL6
CKRL5
CKRL4
CKRL3
CKRL2
CKRL1
CKRL0
CKCKON0
8Fh
Clock Control Register 0
WDTX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
CKCKON1
AFh
Clock Control Register 1
SPIX2
Table 4. Interrupt SFRs

Mnemonic
Add
Name
IEN0
A8h
Interrupt Enable Control 0
EA
EC
ET2
ES
ET1
EX1
ET0
EX0
IEN1
B1h
Interrupt Enable Control 1
ESPI
EI2C
KBD
IPH0
B7h
Interrupt Priority Control High 0
PPCH
PT2H
PHS
PT1H
PX1H
PT0H
PX0H
IPL0
B8h
Interrupt Priority Control Low 0
PPCL
PT2L
PLS
PT1L
PX1L
PT0L
PX0L
IPH1
B3h
Interrupt Priority Control High 1
SPIH
IE2CH
KBDH
IPL1
B2h
Interrupt Priority Control Low 1
SPIL
IE2CL
KBDL
Table 5. Port SFRs

Mnemonic
Add
Name
P0
80h
8-bit Port 0
P1
90h
8-bit Port 1
P2
A0h
8-bit Port 2
P3
B0h
8-bit Port 3
5
4180E805110/06
Table 6. Timer SFRs

Mnemonic
Add
TCON
88h
TMOD
Name
Timer/Counter 0 and 1 Control
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
89h
Timer/Counter 0 and 1 Modes
GATE1
C/T1#
M11
M01
GATE0
C/T0#
M10
M00
TL0
8Ah
Timer/Counter 0 Low Byte
TH0
8Ch
Timer/Counter 0 High Byte
TL1
8Bh
TH1
8Dh
WDTRST
A6h
Watchdog Timer Reset
WDTPRG
A7h
Watchdog Timer Program
WTO2
WTO1
WTO0
T2CON
C8h
Timer/Counter 2 control
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
T2MOD
C9h
Timer/Counter 2 Mode
T2OE
DCEN
RCAP2H
CBh
Timer/Counter 2 Reload/Capture
High Byte
RCAP2L
CAh
Timer/Counter 2 Reload/Capture
Low Byte
TH2
CDh
TL2
CCh
Table 7. PCA SFRs

Mnemonic
Add Name
CCON
D8h
PCA Timer/Counter Control
CF
CR
CCF4
CCF3
CCF2
CCF1
CCF0
CMOD
D9h
PCA Timer/Counter Mode
CIDL
WDTE
CPS1
CPS0
ECF
CL
E9h
PCA Timer/Counter Low Byte
CH
F9h
PCA Timer/Counter High Byte
CCAPM0 DAh PCA Timer/Counter Mode 0
ECOM0
CAPP0
CAPN0
MAT0
TOG0
PWM0
ECCF0
CCAPM1 DBh PCA Timer/Counter Mode 1
ECOM1
CAPP1
CAPN1
MAT1
TOG1
PWM1
ECCF1
ECOM2
CAPP2
CAPN2
MAT2
TOG2
PWM2
ECCF2
CCAPM3 DDh PCA Timer/Counter Mode 3
ECOM3
CAPP3
CAPN3
MAT3
TOG3
PWM3
ECCF3
CCAPM4 DEh PCA Timer/Counter Mode 4
ECOM4
CAPP4
CAPN4
MAT4
TOG4
PWM4
ECCF4
CCAPM2 DCh PCA Timer/Counter Mode 2
CCAP0H FAh
PCA Compare Capture Module 0 H CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP0H3 CCAP0H2 CCAP0H1 CCAP0H0
CCAP1H FBh
CCAP2H FCh PCA Compare Capture Module 2 H CCAP2H7 CCAP2H6 CCAP2H5 CCAP2H4 CCAP2H3 CCAP2H2 CCAP2H1 CCAP2H0
CCAP3H FDh PCA Compare Capture Module 3 H CCAP3H7 CCAP3H6 CCAP3H5 CCAP3H4 CCAP3H3 CCAP3H2 CCAP3H1 CCAP3H0
CCAP4H FEh
CCAP0L
EAh PCA Compare Capture Module 0 L CCAP0L7 CCAP0L6
CCAP0L5
CCAP0L4 CCAP0L3 CCAP0L2 CCAP0L1
CCAP0L0
CCAP1L
EBh PCA Compare Capture Module 1 L CCAP1L7 CCAP1L6
CCAP1L5
CCAP1L0
CCAP2L
ECh PCA Compare Capture Module 2 L CCAP2L7 CCAP2L6
CCAP2L5
CCAP2L0
CCAP3L
EDh PCA Compare Capture Module 3 L CCAP3L7 CCAP3L6
CCAP3L5
CCAP3L0
CCAP4L
EEh PCA Compare Capture Module 4 L CCAP4L7 CCAP4L6
CCAP4L5
CCAP4L0
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Table 8. Serial I/O Port SFRs
Mnemonic
Add
Name
SCON
98h
Serial Control
SBUF
99h
Serial Data Buffer
SADEN
B9h
Slave Address Mask
SADDR
A9h
Slave Address
BDRCON
9Bh
Baud Rate Control
BRL
9Ah
Baud Rate Reload
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
BRR
TBCK
RBCK
SPD
SRC
Table 9. SPI Controller SFRs

Mnemonic
Add
Name
SPCON
C3h
SPI Control
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
SPSTA
C4h
SPI Status
SPIF
WCOL
SSERR
MODF
SPDAT
C5h
SPI Data
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
Table 10. Keyboard Interface SFRs

Mnemonic
Add
Name
KBLS
9Ch
Keyboard Level Selector
KBLS7
KBLS6
KBLS5
KBLS4
KBLS3
KBLS2
KBLS1
KBLS0
KBE
9Dh
Keyboard Input Enable
KBE7
KBE6
KBE5
KBE4
KBE3
KBE2
KBE1
KBE0
KBF
9Eh
Keyboard Flag Register
KBF7
KBF6
KBF5
KBF4
KBF3
KBF2
KBF1
KBF0
7
4180E805110/06
Table 11 shows all SFRs with their address and their reset value.
Table 11. SFR Mapping
Bit
addressable
0/8
F8h
Non Bit addressable

1/9
2/A
3/B
4/C
5/D
6/E
CH
CCAP0H
CCAP1H
CCAPL2H
CCAPL3H
CCAPL4H
0000 0000
XXXX
XXXX
XXXX
XXXX
XXXX
FFh
B
0000 0000
F0h
E8h
F7h
CL
CCAP0L
CCAP1L
CCAPL2L
CCAPL3L
CCAPL4L
0000 0000
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
EFh
ACC
0000 0000
E0h
E7h
CCON
CMOD
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
00X0 0000
00XX X000
X000 0000
X000 0000
X000 0000
X000 0000
X000 0000
D0h
PSW
0000 0000
FCON (1)
XXXX 0000
C8h
T2CON
0000 0000
T2MOD
XXXX XX00
D8h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
IPL0
SADEN
X000 000
0000 0000
DFh
D7h
RCAP2L
0000 0000
C0h
1.
7/F
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
SPCON
SPSTA
SPDAT
0001 0100
0000 0000
XXXX XXXX
CFh
C7h
BFh
P3
IEN1
IPL1
IPH1
IPH0
1111 1111
XXXXX 000
XXXXX000
XXXX X000
X000 0000
IEN0
SADDR
CKCON1
0000 0000
0000 0000
XXXX XXX0
P2
AUXR1
WDTRST
WDTPRG
1111 1111
XXXXX0X0
XXXX XXXX
XXXX X000
SCON
SBUF
BRL
BDRCON
KBLS
KBE
KBF
0000 0000
XXXX XXXX
0000 0000
XXX0 0000
0000 0000
0000 0000
0000 0000
P1
CKRL
1111 1111
TCON
TMOD
TL0
TL1
TH0
TH1
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
P0
1111 1111
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
0/8
1/9
2/A
3/B
AUXR
XX0X 0000
CKCON0
0000 0000
PCON
00X1 0000
4/C
5/D
6/E
AFh
A7h
9Fh
1111 1111
0000 0000
B7h
97h
8Fh
87h
7/F
FCON access is reserved for the Flash API and ISP software.
Reserved
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Pin Configurations
7
8
P0.5/AD5
33
9
10
P1.7/CEx4/MOSI
37
P0.6/AD6
32
P0.7/AD7
RST
10
36
P0.7/AD7
31
30
EA
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P3.0/RxD
35
34
EA
NIC*
11
12
P3.1/TxD
13
33
ALE/PROG
P3.2/INT0
14
15
32
31
PSEN
16
30
P2.6/A14
17
29
P2.5/A13
24
23
P2.2/A10
XTAL1
19
20
22
21
P2.1/A9
NIC*
P2.7/A15
P3.6/WR
18 19 20 21 22 23 24 25 26 27 28
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VCC
P2.0/A8
P1.4/CEX1
VSS
P0.5/AD5
P2.3/A11
P2.4/A12
17
18
P2.2/A10
P3.7/RD
XTAL2
P2.4/A12
P2.3/A11
P2.1/A9
25
NIC*
P2.0/A8
16
P3.4/T0
P3.5/T1
VSS
P3.6/WR
P3.3/INT1
XTAL1
27
26
XTAL2
P3.5/T1
14
15
P3.4/T0
PLCC44
P3.7/RD
13
29
28
NIC*
PDIL40
P0.6/AD6
P1.0/T2
11
12
39
38
P0.4/AD4
P1.6/CEX3/SCK
7
8
P1.1/T2EX/SS
P3.2/INT0
P3.3/INT1
P1.5/CEX2/MISO
P1.2/ECI
P3.0/RxD
P3.1/TxD
P0.3/AD3
P0.4/AD4
P1.3/CEX0
P1.7CEX4/MOSI
RST
6 5 4 3 2 1 44 43 42 41 40
36
35
34
P0.2/AD2
P0.3/AD3
P0.1/AD1
P0.2/AD2
P0.1/AD1
P1.5/CEX2/MISO
P1.6/CEX3/SCK
37
P0.0/AD0
3
4
VCC
P1.2/ECI
P1.3CEX0
P1.4/CEX1
NIC*
P0.0/AD0
P1.0/T2
VCC
39
38
P1.1/T2EX/SS
40
P1.2/ECI
P1.3/CEX0
P1.0/T2
P1.1/T2EX/SS
P1.4/CEX1
Figure 2. Pin Configurations
44 43 42 41 40 39 38 37 36 35 34
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
3
4
5
6
7
8
VQFP44 1.4
33
32
P0.4/AD4
31
P0.6/AD6
30
P0.7/AD7
29
28
EA
NIC*
27
ALE/PROG
PSEN
26
25
24
10
11
23
P0.5/AD5
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
NIC*
VSS
XTAL1
XTAL2
P3.7/RD
P3.6/WR
12 13 14 15 16 17 18 19 20 21 22
*NIC: No Internal Connection
9
4180E805110/06
Table 12. Pin Description for 40 - 44 Pin Packages

Pin Number
Mnemonic
DIL
LCC
VQFP44 1.4
Type
Name and Function
VSS
20
22
16
Ground: 0V reference
VCC
40
44
38
Power Supply: This is the power supply voltage for normal, idle and power-down
operation
P0.0 - P0.7
39 - 32
43 - 36
37 - 30
I/O
Port 0: Port 0 is an open-drain, bi-directional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. Port 0 must be
polarized to VCC or V SS in order to prevent any parasitic current consumption. Port 0
is also the multiplexed low-order address and data bus during access to external
program and data memory. In this application, it uses strong internal pull-up when
emitting 1s. Port 0 also inputs the code Bytes during Flash programming. External
pull-ups are required during program verification during which P0 outputs the code
Bytes.
P1.0 - P1.7
1-8
2-9
40 - 44
1-3
I/O
Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 1 pins that are externally pulled low will source current
because of the internal pull-ups. Port 1 also receives the low-order address Byte
during memory programming and verification.
Alternate functions for AT89C51RB2/RC2 Port 1 include:
40
41
42
I/O
P1.0: Input/Output
I/O
T2 (P1.0): Timer/Counter 2 external count input/Clockout
I/O
P1.1: Input/Output
T2EX: Timer/Counter 2 Reload/Capture/Direction Control
SS: SPI Slave Select
I/O
I
43
44
P1.2: Input/Output
ECI: External Clock for the PCA
I/O
P1.3: Input/Output
I/O
CEX0: Capture/Compare External I/O for PCA Module 0
I/O
P1.4: Input/Output
I/O
I/O
P1.5: Input/Output
I/O
I/O
MISO: SPI Master Input Slave Output line

When SPI is in master mode, MISO receives data from the slave peripheral. When
SPI is in slave mode, MISO outputs data to the master controller.
I/O
P1.6: Input/Output
I/O
I/O
SCK: SPI Serial Clock

SCK outputs clock to the slave peripheral
10
I/O
P1.7: Input/Output:
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Table 12. Pin Description for 40 - 44 Pin Packages (Continued)
Pin Number
Mnemonic
DIL
LCC
VQFP44 1.4
P1.0 - P1.7
Type
Name and Function
I/O
I/O
MOSI: SPI Master Output Slave Input line

When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI
is in slave mode, MOSI receives data from the master controller.
XTAL1
19
21
15
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
XTAL2
18
20
14
Crystal 2: Output from the inverting oscillator amplifier
21 - 28
24 - 31
18 - 25
I/O
because of the internal pull-ups. Port 2 emits the high - order address Byte during
fetches from external program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses
strong internal pull-ups emitting 1s. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some
Port 2 pins receive the high order address bits during EPROM programming and
verification:
P2.0 - P2.7
P2.0 to P2.5 for 16 KB devices

P2.0 to P2.6 for 32KB devices
P3.0 - P3.7
10 - 17
11,
13 - 19
5,
7 - 13
I/O
10
11
RXD (P3.0): Serial input port
11
13
TXD (P3.1): Serial output port
12
14
INT0 (P3.2): External interrupt 0
13
15
INT1 (P3.3): External interrupt 1
14
16
10
T0 (P3.4): Timer 0 external input
15
17
11
T1 (P3.5): Timer 1 external input
16
18
12
WR (P3.6): External data memory write strobe
17
19
13
RD (P3.7): External data memory read strobe

Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to VSS permits a power-on reset using
only an external capacitor to VCC. This pin is an output when the hardware
watchdog forces a system reset.
RST
10
I/O
ALE/PROG
30
33
27
O (I)
because of the internal pull-ups. Port 3 also serves the special features of the
80C51 family, as listed below.
Address Latch Enable/Program Pulse: Output pulse for latching the low Byte of
the address during an access to external memory. In normal operation, ALE is
emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can
be used for external timing or clocking. Note that one ALE pulse is skipped during
each access to external data memory. This pin is also the program pulse input
(PROG) during Flash programming. ALE can be disabled by setting SFRs AUXR. 0
bit. With this bit set, ALE will be inactive during internal fetches.
11
4180E805110/06
Table 12. Pin Description for 40 - 44 Pin Packages (Continued)

Pin Number
Mnemonic
DIL
LCC
PSEN
29
32
26
Program Strobe Enable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program
memory.
EA
31
35
29
External Access Enable: EA must be externally held low to enable the device to
fetch code from external program memory locations 0000H to FFFFH (RD). If
security level 1 is programmed, EA will be internally latched on Reset.
12
VQFP44 1.4
Type
Name and Function
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Port Types
AT89C51RB2/RC2 I/O ports (P1, P2, P3) implement the quasi-bidirectional output that
is common on the 80C51 and most of its derivatives. This output type can be used as
both an input and output without the need to reconfigure the port. This is possible
because when the port outputs a logic high, it is weakly driven, allowing an external
device to pull the pin low. When the pin is pulled low, it is driven strongly and able to sink
a fairly large current. These features are somewhat similar to an open drain output
except that there are three pull-up transistors in the quasi-bidirectional output that serve
different purposes. One of these pull-ups, called the "weak" pull-up, is turned on whenever the port latch for the pin contains a logic 1. The weak pull-up sources a very small
current that will pull the pin high if it is left floating. A second pull-up, called the "medium"
pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is
also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an
external device, the medium pull-up turns off, and only the weak pull-up remains on. In
order to pull the pin low under these conditions, the external device has to sink enough
current to overpower the medium pull-up and take the voltage on the port pin below its
input threshold.
The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up
low-to-high transitions on a quasi-bidirectional port pin when the port latch changes from
a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for a brief time, two
CPU clocks, in order to pull the port pin high quickly. Then it turns off again.
The DPU bit (bit 7 in AUXR register) allows to disable the permanent weak pull up of all
ports when latch data is logical 0.
The quasi-bidirectional port configuration is shown in Figure 3.
Figure 3. Quasi-Bidirectional Output
2 CPU
Clock Delay
P
Strong
P
Weak
Medium
Pin
Port Latch
Data
DPU
AUXR.7
Input
Data
13
4180E805110/06
Oscillator
To optimize the power consumption and execution time needed for a specific task, an
internal, prescaler feature has been implemented between the oscillator and the CPU
and peripherals.
Registers
Table 13. CKRL Register

CKRL Clock Reload Register (97h)
7
CKRL7
CKRL6
CKRL5
CKRL4
CKRL3
CKRL2
CKRL1
CKRL0
Bit Number
Mnemonic
7:0
CKRL
Description
Clock Reload Register
Prescaler value
Reset Value = 1111 1111b

Not bit addressable
Table 14. PCON Register
PCON Power Control Register (87h)
7
SMOD1
SMOD0
POF
GF1
GF0
PD
IDL
Bit Number
Bit Mnemonic
Description
SMOD1
Serial Port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.
SMOD0
Serial Port Mode bit 0

Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
POF
Power-off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can
also be set by software.
GF1
General-purpose Flag
Cleared by software for general-purpose usage.
Set by software for general-purpose usage.
GF0
Cleared by software for general-purpose usage.
Set by software for general-purpose usage.
PD
Power-down Mode bit

Cleared by hardware when reset occurs.
Set to enter power-down mode.
IDL
Idle Mode bit

Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset Value = 00X1 0000b Not bit addressable
14
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Functional Block
Diagram
Figure 4. Functional Oscillator Block Diagram
Reload
Reset
CKRL
FOSC
Xtal1
Osc
Xtal2
1
:2
8-bit
Prescaler-Divider
1
CLK
PERIPH
X2
0
CKCON0
Peripheral Clock
CLK
CPU
CPU clock
Idle
CKRL = 0xFF?
Prescaler Divider
A hardware RESET puts the prescaler divider in the following state:
CKRL = FFh: FCLK CPU = FCLK PERIPH = F OSC/2 (Standard C51 feature)
Any value between FFh down to 00h can be written by software into CKRL register
in order to divide frequency of the selected oscillator:
CKRL = 00h: minimum frequency

FCLK CPU = FCLK PERIPH = FOSC/1020 (Standard Mode)
FCLK CPU = FCLK PERIPH = FOSC/510 (X2 Mode)
CKRL = FFh: maximum frequency

FCLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode)
FCLK CPU = FCLK PERIPH = FOSC (X2 Mode)
FCLK CPU and FCLK PERIPH

In X2 Mode, for CKRL<>0xFF:
F OSC
F CPU = F CLKPER IPH = ----------------------------------------------
2 ( 255 CKRL )
In X1 Mode, for CKRL<>0xFF then:

F OSC
F CPU = F CLKPER IPH = ----------------------------------------------
4 ( 255 CKRL )
15
4180E805110/06
Enhanced Features
In comparison to the original 80C52, the AT89C51RB2/RC2 implements some new features, which are:
X2 Feature
X2 option
Dual Data Pointer
Extended RAM
Programmable Counter Array (PCA)
Hardware Watchdog
SPI interface
4-level interrupt priority system
power-off flag
ONCE mode
ALE disabling
Some enhanced features are also located in the UART and the timer 2
The AT89C51RB2/RC2 core needs only 6 clock periods per machine cycle. This feature
called X2 provides the following advantages:
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
Save power consumption while keeping same CPU power (oscillator power saving).
Save power consumption by dividing dynamically the operating frequency by 2 in

operating and idle modes.
Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
Description
The clock for the whole circuit and peripherals is first divided by 2 before being used by
the CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
Figure 5 shows the clock generation block diagram. X2 bit is validated on the rising edge
of the XTAL12 to avoid glitches when switching from X2 to X1 mode. Figure 6 shows
the switching mode waveforms.
Figure 5. Clock Generation Diagram
CKRL
2
XTAL1
FXTAL
FOSC
XTAL1:2
0
1
8 bit Prescaler
FCLK CPU
FCLK PERIPH
X2
CKCON0
16
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Figure 6. Mode Switching Waveforms
XTAL1
XTAL1:2
X2 Bit
FOSC
CPU Clock
x1 Mode
X2 Mode
X1 Mode
The X2 bit in the CKCON0 register (see Table 15) allows a switch from 12 clock periods
per instruction to 6 clock periods and vice versa. At reset, the speed is set according to
X2 bit of Hardware Security Byte (HSB). By default, Standard mode is active. Setting the
X2 bit activates the X2 feature (X2 mode).
The T0X2, T1X2, T2X2, UARTX2, PCAX2, and WDX2 bits in the CKCON0 register
(Table 15) and SPIX2 bit in the CKCON1 register (see Table 16) allow a switch from
standard peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods per peripheral clock cycle). These bits are active only in X2
mode.
17
4180E805110/06
Table 15. CKCON0 Register

CKCON0 - Clock Control Register (8Fh)
7
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
Bit
Number
7
Bit
Mnemonic Description
Reserved
Watchdog Clock
WDX2
(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array Clock
PCAX2
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
Enhanced UART Clock (Mode 0 and 2)
SIX2
has no effect).
Timer 2 Clock
T2X2
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Timer 1 Clock
T1X2
has no effect).
Timer0 Clock
T0X2
has no effect).
CPU Clock
X2
Cleared to select 12 clock periods per machine cycle (STD, X1 mode) for CPU
and all the peripherals. Set to select 6 clock periods per machine cycle (X2
mode) and to enable the individual peripheralsX2 bits. Programmed by
hardware after Power-up regarding Hardware Security Byte (HSB), Default
setting, X2 is cleared.
Reset Value = 0000 000HSB. X2b (see Table 65 Hardware Security Byte)
Not bit addressable
18
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Table 16. CKCON1 Register
CKCON1 - Clock Control Register (AFh)
7
SPIX2
Bit
Number
Bit
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SPIX2
SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low,
this bit has no effect).
Clear to select 6 clock periods per peripheral clock cycle.
Reset Value = XXXX XXX0b

Not bit addressable
19
4180E805110/06
Dual Data Pointer

Register (DPTR)
The additional data pointer can be used to speed up code execution and reduce code
size.
The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external
memory, and a single bit called DPS = AUXR1.0 (see Table 17) that allows the program
code to switch between them (see Figure 7).
Figure 7. Use of Dual Pointer
External Data Memory
0
DPS
AUXR1(A2H)
DPTR1
DPTR0
DPH(83H) DPL(82H)
20
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Table 17. AUXR1 register
AUXR1- Auxiliary Register 1(0A2h)
7
ENBOOT
GF3
DPS
Bit
Bit
Number
Reserved
Reserved
ENBOOT
Enable Boot Flash

Cleared to disable boot ROM.
Set to map the boot ROM between F800h - 0FFFFh.
Reserved
GF3
Always Cleared
Reserved
DPS
This bit is a general-purpose user flag.(1)
Data Pointer Selection

Cleared to select DPTR0.
Set to select DPTR1.
Reset Value = XXXX XX0X0b

Not bit addressable
Note:
1. Bit 2 stuck at 0; this allows using INC AUXR1 to toggle DPS without changing GF3.
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a Byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the Byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
21
4180E805110/06
INC is a short (2 Bytes) and fast (12 clocks) way to manipulate the DPS bit in the
AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit
to a particular state, but simply toggles it. In simple routines, such as the block move
example, only the fact that DPS is toggled in the proper sequence matters, not its actual
value. In other words, the block move routine works the same whether DPS is '0' or '1'
on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with
DPS in the opposite state.
22
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Expanded RAM
(XRAM)
The AT89C51RB2/RC2 provides additional bytes of random access memory (RAM)

space for increased data parameter handling and high-level language usage.
AT89C51RB2/RC2 devices have expanded RAM in external data space; maximum size
and location are described in Table 18.
Table 18. Expanded RAM
Address
Part Number
XRAM Size
Start
End
AT89C51RB2/RC2
1024
00h
3FFh
The AT89C51RB2/RC2 has internal data memory that is mapped into four separate
segments.
The four segments are:
1. The Lower 128 Bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
addressable.
2. The Upper 128 Bytes of RAM (addresses 80h to FFh) are indirectly addressable
only.
3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly
addressable only.
4. The expanded RAM Bytes are indirectly accessed by MOVX instructions, and
with the EXTRAM bit cleared in the AUXR register (see Table 18).
The lower 128 Bytes can be accessed by either direct or indirect addressing. The Upper
128 Bytes can be accessed by indirect addressing only. The Upper 128 Bytes occupy
the same address space as the SFR. That means they have the same address, but are
physically separate from SFR space.
Figure 8. Internal and External Data Memory Address
0FFh or 3FFh
0FFh
0FFh
Upper
128 Bytes
Internal
RAM
Indirect Accesses
XRAM
80h
0FFFFh
Special
Function
Register
Direct Accesses
External
Data
Memory
80h
7Fh
Lower
128 Bytes
Internal
RAM
Direct or Indirect
Accesses
00
00
00FFh up to 03FFh
0000
When an instruction accesses an internal location above address 7Fh, the CPU knows
whether the access is to the upper 128 Bytes of data RAM or to SFR space by the
addressing mode used in the instruction.
Instructions that use direct addressing access SFR space. For example:
MOV 0A0H, # data, accesses the SFR at location 0A0h (which is P2).
23
4180E805110/06
Instructions that use indirect addressing access the Upper 128 Bytes of data RAM.
For example: MOV @R0, # data where R0 contains 0A0h, accesses the data Byte
at address 0A0h, rather than P2 (whose address is 0A0h).
The XRAM Bytes can be accessed by indirect addressing, with EXTRAM bit cleared
and MOVX instructions. This part of memory that is physically located on-chip,
logically occupies the first Bytes of external data memory. The bits XRS0 and XRS1
are used to hide a part of the available XRAM as explained in Table 18. This can be
useful if external peripherals are mapped at addresses already used by the internal
XRAM.
With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in
combination with any of the registers R0, R1 of the selected bank or DPTR. An
access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For
example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H,
accesses the XRAM at address 0A0H rather than external memory. An access to
external data memory locations higher than the accessible size of the XRAM will be
performed with the MOVX DPTR instructions in the same way as in the standard
80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and
read timing signals. Accesses to XRAM above 0FFH can only be done by the use of
DPTR.
With EXTRAM = 1, MOVX @RI and MOVX @DPTR will be similar to the standard
80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0
and any output port pins can be used to output higher order address bits. This is to
provide the external paging capability. MOVX @DPTR will generate a sixteen-bit
address. Port2 outputs the high-order eight address bits (the contents of DPH) while
Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ RI and
MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7
(RD).
The stack pointer (SP) may be located anywhere in the 256 Bytes RAM (lower and
upper RAM) internal data memory. The stack may not be located in the XRAM.
The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses
are extended from 6 to 30 clock periods. This is useful to access external slow
peripherals.
24
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Registers
Table 19. AUXR Register

AUXR - Auxiliary Register (8Eh)
7
DPU
M0
XRS1
XRS0
EXTRAM
AO
Bit
Number
Bit
Disable Weak Pull-up
DPU
Cleared to activate the permanent weak pull up when latch data is logical 1
Set to disactive the weak pull-up (reduce power consumption)
Reserved
Pulse Length
M0
Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock
periods (default).
Set to stretch MOVX control: the RD and the WR pulse length is 30 clock
periods.
XRS1
Reserved
XRAM Size
XRS1 XRS0 XRAM size
0
0
256 Bytes (default)
XRS0
512 Bytes
768 Bytes
1024 Bytes
EXTRAM Bit
Cleared to access internal XRAM using movx @ Ri/ @ DPTR.
1
EXTRAM
Set to access external memory.

Programmed by hardware after Power-up regarding Hardware Security Byte
(HSB), default setting, XRAM selected.
AO
ALE Output Bit

Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if
X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC
instruction is used.
Reset Value = XX0X 00HSB. XRAM0b (see Table 65)

Not bit addressable
25
4180E805110/06
Timer 2
The Timer 2 in the AT89C51RB2/RC2 is the standard C52 Timer 2.

It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2
and TL2 are cascaded. It is controlled by T2CON (Table 20) and T2MOD (Table 21)
registers. Timer 2 operation is similar to Timer 0 and Timer 1C/T2 selects FOSC/12 (timer
operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2
allows TL2 to increment by the selected input.
Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These
modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON).
see the Atmel 8-bit Microcontroller Hardware description for the description of Capture
and Baud Rate Generator Modes.
Timer 2 includes the following enhancements:
Auto-reload Mode
Auto-reload mode with up or down counter
Programmable clock-output
The auto-reload mode configures Timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (see the
Atmel C51 Microcontroller Hardware description). If DCEN bit is set, Timer 2 acts as an
Up/down timer/counter as shown in Figure 9. In this mode the T2EX pin controls the
direction of count.
When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the
TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value
in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.
When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the
timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.
The underflow sets TF2 flag and reloads FFFFh into the timer registers.
The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of
the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit
resolution.
26
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Figure 9. Auto-Reload Mode Up/Down Counter (DCEN = 1)
FCLK PERIPH
:6
1
T2
C/T2
TR2
T2CON
T2CON
T2EX:
(DOWN COUNTING RELOAD VALUE)
if DCEN = 1, 1 = UP
FFh
FFh
if DCEN = 1, 0 = DOWN
(8-bit)
(8-bit)
if DCEN = 0, up counting
TOGGLE
T2CON
EXF2
TL2
TH2
(8-bit)
(8-bit)
TF2
TIMER 2
INTERRUPT
T2CON
RCAP2L
(8-bit)
RCAP2H
(8-bit)
(UP COUNTING RELOAD VALUE)
Programmable Clock-out In the clock-out mode, Timer 2 operates as a 50% duty-cycle, programmable clock generator (see Figure 10). The input clock increments TL2 at frequency FCLK PERIPH/2. The
Mode
timer repeatedly counts to overflow from a loaded value. At overflow, the contents of
RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, Timer 2
overflows do not generate interrupts. The formula gives the clock-out frequency as a
function of the system oscillator frequency and the value in the RCAP2H and RCAP2L
registers:
Clock O utFrequency
F CLKPERIPH
= --------------------------------------------------------------------------------------------4 ( 65536 RCAP2H RCAP2L )
For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz

(FCLK PERIPH/216) to 4 MHz (FCLK PERIPH/4). The generated clock signal is brought out to
T2 pin (P1.0).
Timer 2 is programmed for the clock-out mode as follows:
Set T2OE bit in T2MOD register.
Clear C/T2 bit in T2CON register.
Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L
registers.
Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the
reload value or a different one depending on the application.
To start the timer, set TR2 run control bit in T2CON register.
It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not
independent since both functions use the values in the RCAP2H and RCAP2L registers.
27
4180E805110/06
Figure 10. Clock-Out Mode C/T2 = 0

FCLK PERIPH
:6
TR2
T2CON
TL2
(8-bit)
TH2
(8-bit)
OVERFLOW
RCAP2L RCAP2H
(8-bit) (8-bit)
Toggle
T2
D
T2OE
T2MOD
T2EX
EXF2
EXEN2
T2CON
28
T2CON
TIMER 2
INTERRUPT
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Registers
Table 20. T2CON Register

T2CON Timer 2 Control Register (C8h)
7
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Number
Bit
TF2
Timer 2 Overflow Flag

Must be cleared by software.
Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.
EXF2
Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2 = 1.
When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2
interrupt is enabled.
Must be cleared by software. EXF2 doesnt cause an interrupt in Up/down
counter mode (DCEN = 1).
RCLK
Receive Clock Bit

Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
TCLK
Transmit Clock Bit

Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
EXEN2
TR2
Timer 2 External Enable Bit

Cleared to ignore events on T2EX pin for Timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if Timer 2 is not used to clock the serial port.
Timer 2 Run Control Bit
Cleared to turn off Timer 2.
Set to turn on Timer 2.
C/T2#
Timer/Counter 2 Select Bit

Cleared for timer operation (input from internal clock system: FCLK PERIPH).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0
for clock out mode.
CP/RL2#
Timer 2 Capture/Reload Bit

If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload
on Timer 2 overflow.
Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin
if EXEN2 = 1.
Set to capture on negative transitions on T2EX pin if EXEN2 = 1.

Bit addressable
29
4180E805110/06
Table 21. T2MOD Register

T2MOD Timer 2 Mode Control Register (C9h)
7
T2OE
DCEN
Bit
Number
Bit
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
T2OE
Timer 2 Output Enable Bitt

Cleared to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
DCEN
Down Counter Enable Bit

Cleared to disable Timer 2 as up/down counter.
Set to enable Timer 2 as up/down counter.
Reset Value = XXXX XX00b

Not bit addressable
30
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Programmable
Counter Array (PCA)
The PCA provides more timing capabilities with less CPU intervention than the standard
timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for
an array of five compare/capture Modules. Its clock input can be programmed to count
any one of the following signals:
6
Peripheral clock frequency (FCLK PERIPH) 2
Timer 0 overflow
External input on ECI (P1.2)
Peripheral clock frequency (FCLK PERIPH)
Each compare/capture Modules can be programmed in any one of the following modes:
Rising and/or falling edge capture
Software timer
High-speed output
Pulse width modulator
Module 4 can also be programmed as a watchdog timer (see Section "PCA Watchdog
Timer", page 42).
When the compare/capture Modules are programmed in the capture mode, software
timer, or high speed output mode, an interrupt can be generated when the Module executes its function. All five Modules plus the PCA timer overflow share one interrupt
vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O.
These pins are listed below. If one or several bits in the port are not used for the PCA,
they can still be used for standard I/O.
PCA Component
External I/O Pin
16-bit Counter
P1.2/ECI
16-bit Module 0
P1.3/CEX0
16-bit Module 1
P1.4/CEX1
16-bit Module 2
P1.5/CEX2
16-bit Module 3
P1.6/CEX3
The PCA timer is a common time base for all five Modules (see Figure 11). The timer
count source is determined from the CPS1 and CPS0 bits in the CMOD register
(Table 22) and can be programmed to run at:
1/6 the peripheral clock frequency (FCLK PERIPH)
1/2 the peripheral clock frequency (FCLK PERIPH)
The Timer 0 overflow
The input on the ECI pin (P1.2)
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Figure 11. PCA Timer/Counter

To PCA
Modules
FCLK PERIPH/6
overflow
FCLK PERIPH/2
CH
T0 OVF
It
CL
16-bit up Counter
P1.2
CIDL
WDTE
CF
CR
CPS1
CPS0
ECF
CCF2
CCF1 CCF0
CMOD
0xD9
Idle
32
CCF4 CCF3
CCON
0xD8
AT89C51RB2/RC2
4180E805110/06
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Registers
Table 22. CMOD Register

CMOD PCA Counter Mode Register (D9h)
7
CIDL
WDTE
CPS1
CPS0
ECF
Bit
Number
Bit
Counter Idle Control
CIDL
Cleared to program the PCA Counter to continue functioning during idle Mode.
Set to program PCA to be gated off during idle.
Watchdog Timer Enable
WDTE
Cleared to disable Watchdog Timer function on PCA Module 4.

Set to enable Watchdog Timer function on PCA Module 4.
Reserved
Reserved
Reserved
CPS1
PCA Count Pulse Select

CPS1 CPS0 Selected PCA input
0
0
Internal clock FCLK PERIPH/6
CPS0
ECF
Internal clock FLK PERIPH/2
Timer 0 Overflow
External clock at ECI/P1.2 pin (max rate = fCLK PERIPH/ 4)
PCA Enable Counter Overflow Interrupt

Cleared to disable CF bit in CCON to inhibit an interrupt.
Set to enable CF bit in CCON to generate an interrupt.
Reset Value = 00XX X000b

Not bit addressable
The CMOD register includes three additional bits associated with the PCA.
The CIDL bit which allows the PCA to stop during idle mode.
The WDTE bit which enables or disables the watchdog function on Module 4.
The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in
the CCON SFR) to be set when the PCA timer overflows.
The CCON register contains the run control bit for the PCA and the flags for the PCA
timer (CF) and each Module (see Table 23).
Bit CR (CCON. 6) must be set by software to run the PCA. The PCA is shut off by
clearing this bit.
Bit CF: The CF bit (CCON. 7) is set when the PCA counter overflows and an
interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can
only be cleared by software.
Bits 0 through 4 are the flags for the Modules (bit 0 for Module 0, bit 1 for Module 1,
etc. ) and are set by hardware when either a match or a capture occurs. These flags
also can only be cleared by software.
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Table 23. CCON Register

CCON PCA Counter Control Register (D8h)
7
CF
CR
CCF4
CCF3
CCF2
CCF1
CCF0
Bit
Number
Bit
PCA Counter Overflow Flag
CF
CR
Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in
CMOD is set. CF may be set by either hardware or software but can only be
cleared by software.
PCA Counter Run Control Bit
Must be cleared by software to turn the PCA counter off.
Set by software to turn the PCA counter on.
CCF4
Reserved
PCA Module 4 Interrupt Flag
Set by hardware when a match or capture occurs.
CCF3

CCF2

CCF1

CCF0

Reset Value = 000X 0000b

Bit addressable
The watchdog timer function is implemented in Module 4 (see Figure 14).
The PCA interrupt system is shown in Figure 12.
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Figure 12. PCA Interrupt System
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0
CCON
0xD8
PCA Timer/Counter
Module 0
Module 1
To Interrupt
Priority Decoder
Module 2
Module 3
Module 4
CMOD. 0 ECF
ECCFn CCAPMn. 0
IEN0. 6
EC
IEN0. 7
EA
PCA Modules: each one of the five compare/capture Modules has six possible functions. It can perform:
16-bit Capture, positive-edge triggered
16-bit Capture, negative-edge triggered
16-bit Capture, both positive and negative-edge triggered
16-bit Software Timer
16-bit High-speed Output
8-bit Pulse Width Modulator
In addition, Module 4 can be used as a Watchdog Timer.

Each Module in the PCA has a special function register associated with it. These registers are: CCAPM0 for Module 0, CCAPM1 for Module 1, etc. (see Table 24). The
registers contain the bits that control the mode that each Module will operate in.
The ECCF bit (CCAPMn. 0 where n = 0, 1, 2, 3, or 4 depending on the Module)

enables the CCF flag in the CCON SFR to generate an interrupt when a match or
compare occurs in the associated Module.
PWM (CCAPMn. 1) enables the pulse width modulation mode.
The TOG bit (CCAPMn. 2) when set causes the CEX output associated with the
Module to toggle when there is a match between the PCA counter and the Module's
capture/compare register.
The match bit MAT (CCAPMn. 3) when set will cause the CCFn bit in the CCON
register to be set when there is a match between the PCA counter and the Module's
capture/compare register.
The next two bits CAPN (CCAPMn. 4) and CAPP (CCAPMn. 5) determine the edge
that a capture input will be active on. The CAPN bit enables the negative edge, and
the CAPP bit enables the positive edge. If both bits are set both edges will be
enabled and a capture will occur for either transition.
The last bit in the register ECOM (CCAPMn. 6) when set enables the comparator
function.
Table 24 shows the CCAPMn settings for the various PCA functions.
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Table 24. CCAPMn Registers (n = 0-4)

CCAPM0 PCA Module 0 Compare/Capture Control Register (0DAh)
CCAPM1 PCA Module 1 Compare/Capture Control Register (0DBh)
CCAPM2 PCA Module 2 Compare/Capture Control Register (0DCh)
CCAPM3 PCA Module 3 Compare/Capture Control Register (0DDh)
CCAPM4 PCA Module 4 Compare/Capture Control Register (0DEh)
7
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
Bit
Number
Bit
ECOMn
Reserved
Enable Comparator
Cleared to disable the comparator function.
Set to enable the comparator function.
Capture Positive
CAPPn
CAPNn
Cleared to disable positive edge capture.

Set to enable positive edge capture.
Capture Negative
Cleared to disable negative edge capture.
Set to enable negative edge capture.
Match
MATn
TOGn
PWMn
When MATn = 1, a match of the PCA counter with this Module's

compare/capture register causes the CCFn bit in CCON to be set, flagging an
interrupt.
Toggle
When TOGn = 1, a match of the PCA counter with this Module's
compare/capture register causes theCEXn pin to toggle.
Pulse Width Modulation Mode
Cleared to disable the CEXn pin to be used as a pulse width modulated output.
Set to enable the CEXn pin to be used as a pulse width modulated output.
Enable CCF Interrupt
CCF0
Cleared to disable compare/capture flag CCFn in the CCON register to generate

an interrupt.
Set to enable compare/capture flag CCFn in the CCON register to generate an
interrupt.
Reset Value = X000 0000b

Not bit addressable
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Table 25. PCA Module Modes (CCAPMn Registers)
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMm
ECCFn Module Function
No Operation
16-bit capture by a positive-edge

trigger on CEXn
16-bit capture by a negative trigger

on CEXn
16-bit capture by a transition on

CEXn
16-bit Software Timer/Compare

mode.
16-bit High-speed Output
8-bit PWM
Watchdog Timer (Module 4 only)
There are two additional registers associated with each of the PCA Modules. They are
CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a
capture occurs or a compare should occur. When a Module is used in the PWM mode
these registers are used to control the duty cycle of the output (see Table 26 and
Table 27).
Table 26. CCAPnH Registers (n = 0-4)
CCAP0H PCA Module 0 Compare/Capture Control Register High (0FAh)
CCAP1H PCA Module 1 Compare/Capture Control Register High (0FBh)
CCAP2H PCA Module 2 Compare/Capture Control Register High (0FCh)
CCAP3H PCA Module 3 Compare/Capture Control Register High (0FDh)
CCAP4H PCA Module 4 Compare/Capture Control Register High (0FEh)
7
Bit
Number
7-0
Bit
-
PCA Module n Compare/Capture Control

CCAPnH Value

Not bit addressable
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Table 27. CCAPnL Registers (n = 0-4)

CCAP0L PCA Module 0 Compare/Capture Control Register Low (0EAh)
CCAP1L PCA Module 1 Compare/Capture Control Register Low (0EBh)
CCAP2L PCA Module 2 Compare/Capture Control Register Low (0ECh)
CCAP3L PCA Module 3 Compare/Capture Control Register Low (0EDh)
CCAP4L PCA Module 4 Compare/Capture Control Register Low (0EEh)
7
Bit
Number
7-0
Bit
-
PCA Module n Compare/Capture Control

CCAPnL Value

Not bit addressable
Table 28. CH Register
CH PCA Counter Register High (0F9h)
7
Bit
Number
7-0
Bit
-
PCA Counter
CH Value

Not bit addressable
Table 29. CL Register
CL PCA Counter Register Low (0E9h)
7
Bit
Number
7-0
Bit
-
PCA Counter
CL Value

Not bit addressable
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AT89C51RB2/RC2
4180E805110/06
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PCA Capture Mode
To use one of the PCA Modules in the capture mode either one or both of the CCAPM
bits CAPN and CAPP for that Module must be set. The external CEX input for the Module (on port 1) is sampled for a transition. When a valid transition occurs the PCA
hardware loads the value of the PCA counter registers (CH and CL) into the Module's
capture registers (CCAPnL and CCAPnH). If the CCFn bit for the Module in the CCON
SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated
(see Figure 13).
Figure 13. PCA Capture Mode

CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0 CCON

0xD8
PCA IT
PCA Counter/Timer
Cex. n
CH
CL
CCAPnH
CCAPnL
Capture
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4

0xDA to 0xDE
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16-bit Software Timer/

Compare Mode
The PCA Modules can be used as software timers by setting both the ECOM and MAT
bits in the Modules CCAPMn register. The PCA timer will be compared to the Module's
capture registers and when a match occurs, an interrupt will occur if the CCFn (CCON
SFR) and the ECCFn (CCAPMn SFR) bits for the Module are both set (see Figure 14).
Figure 14. PCA Compare Mode and PCA Watchdog Timer

CCON
CF
Write to
CCAPnL
CR
0xD8
Reset
PCA IT
Write to
CCAPnH
1
CCAPnH
0
CCAPnL
Enable
Match
16 bit Comparator
CH
RESET(1)
CL
PCA Counter/Timer
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CIDL
Note:
WDTE
CPS1 CPS0
ECF
CCAPMn, n = 0 to 4
0xDA to 0xDE
CMOD
0xD9
1. Only for Module 4
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,
otherwise an unwanted match could occur. Writing to CCAPnH will set the ECOM bit.
Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesnt
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
40
AT89C51RB2/RC2
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High-speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle
each time a match occurs between the PCA counter and the modules capture registers.
To activate this mode the TOG, MAT, and ECOM bits in the modules CCAPMn SFR
must be set (see Figure 15).
A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.
Figure 15. PCA High-speed Output Mode
CCON
CF
CR
0xD8
Write to
CCAPnL Reset
PCA IT
Write to
CCAPnH
CCAPnH
0
CCAPnL
Enable
16-bit Comparator
CH
Match
CL
CEXn
PCA Counter/Timer
CCAPMn, n = 0 to 4
0xDA to 0xDE
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non-zero value,
otherwise an unwanted match could occur.
Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesnt
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
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Pulse Width Modulator

Mode
All of the PCA Modules can be used as PWM outputs. Figure 16 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the
Modules will have the same frequency of output because they all share the PCA timer.
The duty cycle of each Module is independently variable using the module's capture
register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than the output
will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in
CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in
the module's CCAPMn register must be set to enable the PWM mode.
Figure 16. PCA PWM Mode
CCAPnH
Overflow
CCAPnL
0
CEXn
Enable
8-bit Comparator
1
CL
PCA Counter/Timer
CCAPMn, n = 0 to 4
0xDA to 0xDE
PCA Watchdog Timer
An on-board watchdog timer is available with the PCA to improve the reliability of the
system without increasing chip count. Watchdog timers are useful for systems that are
susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only
PCA Module that can be programmed as a watchdog. However, this Module can still be
used for other modes if the watchdog is not needed. Figure 14 shows a diagram of how
the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just
like the other compare modes, this 16-bit value is compared to the PCA timer value. If a
match is allowed to occur, an internal reset will be generated. This will not cause the
RST pin to be driven high.
In order to hold off the reset, the user has the following three options:
1. Periodically change the compare value so it will never match the PCA timer.
2. Periodically change the PCA timer value so it will never match the compare
values.
3. Disable the watchdog by clearing the WDTE bit before a match occurs and then
re-enable it.
The first two options are more reliable because the watchdog timer is never disabled as
in option #3. If the program counter ever goes astray, a match will eventually occur and
cause an internal reset. The second option is also not recommended if other PCA Modules are being used. Remember, the PCA timer is the time base for all modules;
42
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
changing the time base for other Modules would not be a good idea. Thus, in most applications the first solution is the best option.
This watchdog timer wont generate a reset out on the reset pin.
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Serial I/O Port
The serial I/O port in the AT89C51RB2/RC2 is compatible with the serial I/O port in the
80C52.
It provides both synchronous and asynchronous communication modes. It operates as a
Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes
(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously
and at different baud rates
Serial I/O port includes the following enhancements:
Framing Error Detection
Framing error detection
Automatic address recognition
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2
and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 17).
Figure 17. Framing Error Block Diagram
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
SCON (98h)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)

SM0 to UART mode control (SMOD0 = 0)
SMOD1SMOD0
POF
GF1
GF0
PD
IDL
PCON (87h)
To UART framing error control
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register (See Table 33.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a reset can clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the
last data bit (See Figure 18. and Figure 19.).
Figure 18. UART Timings in Mode 1
RXD
D0
Start
bit
D1
D2
D3
D4
Data byte
D5
D6
D7
Stop
bit
RI
SMOD0=X
FE
SMOD0=1
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4180E805110/06
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Figure 19. UART Timings in Modes 2 and 3
RXD
D0
Start
bit
D1
D2
D3
D4
Data byte
D5
D6
D7
D8
Ninth Stop
bit
bit
RI
SMOD0=0
RI
SMOD0=1
FE
SMOD0=1
Automatic Address
Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor
communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address, the
receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command frames addressed to other devices.
If desired, the user may enable the automatic address recognition feature in mode 1.In
this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when
the received command frame address matches the devices address and is terminated
by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and
a broadcast address.
Note:
Given Address
The multiprocessor communication and automatic address recognition features cannot

be enabled in mode 0 (i. e. setting SM2 bit in SCON register in mode 0 has no effect).
Each device has an individual address that is specified in SADDR register; the SADEN
register is a mask byte that contains dont-care bits (defined by zeros) to form the
devices given address. The dont-care bits provide the flexibility to address one or more
slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111
1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
SADEN1111 1001b
Given1111 0XX1b
Slave C:SADDR1111 0010b
SADEN1111 1101b
Given1111 00X1b
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4180E805110/06
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a dont-care bit; for slaves B and C, bit 0 is a 1.To communicate with slave A only, the master must send an address where bit 0 is clear (e. g.
1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a dont care bit. To communicate with
slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both
set (e. g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set,
bit 1 clear, and bit 2 clear (e. g. 1111 0001b).
Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers
with zeros defined as dont-care bits, e. g. :
SADDR0101 0110b
SADEN1111 1100b
Broadcast =SADDR OR SADEN1111 111Xb
The use of dont-care bits provides flexibility in defining the broadcast address, however
in most applications, a broadcast address is FFh. The following is an example of using
broadcast addresses:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Broadcast1111 1X11b,
Slave B:SADDR1111 0011b
SADEN1111 1001b
Broadcast1111 1X11B,
Slave C:SADDR=1111 0011b
SADEN1111 1101b
Broadcast1111 1111b
For slaves A and B, bit 2 is a dont care bit; for slave C, bit 2 is set. To communicate with
all of the slaves, the master must send an address FFh. To communicate with slaves A
and B, but not slave C, the master can send and address FBh.
Reset Addresses
46
On reset, the SADDR and SADEN registers are initialized to 00h, i. e. the given and
broadcast addresses are XXXX XXXXb (all dont-care bits). This ensures that the serial
port will reply to any address, and so, that it is backwards compatible with the 80C51
microcontrollers that do not support automatic address recognition.
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Registers
Table 30. SADEN Register

SADEN - Slave Address Mask Register (B9h)
7

Not bit addressable
Table 31. SADDR Register
SADDR - Slave Address Register (A9h)
7

Not bit addressable
Baud Rate Selection for

UART for Mode 1 and 3
The Baud Rate Generator for transmit and receive clocks can be selected separately via
the T2CON and BDRCON registers.
Figure 20. Baud Rate Selection
TIMER1
TIMER2
TIMER_BRG_RX
0
/ 16
Rx Clock
RCLK
RBCK
INT_BRG
TIMER1
TIMER2
0
1
TIMER_BRG_TX
0
1
/ 16
Tx Clock
TCLK
INT_BRG
TBCK
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Table 32. Baud Rate Selection Table UART
Internal Baud Rate Generator

(BRG)
TCLK
RCLK
TBCK
RBCK
Clock Source
Clock Source
(T2CON)
(T2CON)
(BDRCON)
(BDRCON)
UART Tx
UART Rx
Timer 1
Timer 1
Timer 2
Timer 1
Timer 1
Timer 2
Timer 2
Timer 2
INT_BRG
Timer 1
INT_BRG
Timer 2
Timer 1
INT_BRG
Timer 2
INT_BRG
INT_BRG
INT_BRG
When the internal Baud Rate Generator is used, the Baud Rates are determined by the
BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode)
in BDRCON register and the value of the SMOD1 bit in PCON register.
Figure 21. Internal Baud Rate

FClk Periph
BRG
(8 bits)
Overflow
0
INT_BRG
1
SPD
BRR
BDRCON.1
BDRCON.4
SMOD1
PCON.7
BRL
(8 bits)
The baud rate for UART is token by formula:

Baud_Rate =
BRL = 256 -
48
2SMOD1 FPER
32 (256 -BRL)
(1-SPD)
2SMOD1 FPER
(1-SPD)
32 Baud_Rate
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Table 33. SCON Register
SCON - Serial Control Register (98h)
7
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Bit
Number
Mnemonic
Description
Framing Error bit (SMOD0=1)
FE
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit.
7
SM0
Serial port Mode bit 0

Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit.
SM1
Serial port Mode bit 1

Mode
SM0 SM1
0
0
Shift Register
0
1
8-bit UART
1
0
9-bit UART
1
1
9-bit UART
Baud Rate
FXTAL /12 (or FXTAL /6 in mode X2)
Variable
FXTAL /64 or FXTAL/32
Variable
Serial port Mode 2 bit / Multiprocessor Communication Enable bit

5
SM2
REN
TB8
Clear to disable multiprocessor communication feature.

Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1.This bit should be cleared in mode 0.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3
RB8
Clear to transmit a logic 0 in the 9th bit.

Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not
used.
TI
Transmit Interrupt flag

Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning
of the stop bit in the other modes.
RI
Receive Interrupt flag

Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 18.
and Figure 19. in the other modes.

Bit addressable
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Table 34. Example of Computed Value When X2=1, SMOD1=1, SPD=1

Baud Rates
FOSC = 16. 384 MHz
FOSC = 24MHz
BRL
Error (%)
BRL
Error (%)
115200
247
1.23
243
0.16
57600
238
1.23
230
0.16
38400
229
1.23
217
0.16
28800
220
1.23
204
0.16
19200
203
0.63
178
0.16
9600
149
0.31
100
0.16
4800
43
1.23
Table 35. Example of Computed Value When X2=0, SMOD1=0, SPD=0

Baud Rates
FOSC = 16. 384 MHz
FOSC = 24MHz
BRL
Error (%)
BRL
Error (%)
4800
247
1.23
243
0.16
2400
238
1.23
230
0.16
1200
220
1.23
202
3.55
600
185
0.16
152
0.16
The baud rate generator can be used for mode 1 or 3 (refer to Figure 20.), but also for
mode 0 for UART, thanks to the bit SRC located in BDRCON register (Table 42.)
UART Registers
Table 36. SADEN Register

SADEN - Slave Address Mask Register for UART (B9h)
7

Table 37. SADDR Register
SADDR - Slave Address Register for UART (A9h)
7
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Table 38. SBUF Register
SBUF - Serial Buffer Register for UART (99h)
7
Reset Value = XXXX XXXXb

Table 39. BRL Register
BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah)
7
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Table 40. T2CON Register

T2CON - Timer 2 Control Register (C8h)
7
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Bit
Number
Mnemonic
TF2
Description
Timer 2 overflow Flag
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
EXF2
Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2
interrupt is enabled.
Must be cleared by software. EXF2 doesnt cause an interrupt in Up/down
counter mode (DCEN = 1)
RCLK
Receive Clock bit for UART

Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
TCLK
Transmit Clock bit for UART

Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
EXEN2
TR2
Timer 2 External Enable bit

Cleared to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if timer 2 is not used to clock the serial port.
Timer 2 Run control bit
Cleared to turn off timer 2.
Set to turn on timer 2.
C/T2#
Timer/Counter 2 select bit

Cleared for timer operation (input from internal clock system: FCLK PERIPH ).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be
0 for clock out mode.
CP/RL2#
Timer 2 Capture/Reload bit

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on
timer 2 overflow.
Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin
if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.

Bit addressable
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PCON - Power Control Register (87h)
7
SMOD1
SMOD0
POF
GF1
GF0
PD
IDL
Bit
Bit
Number
Mnemonic
SMOD1
SMOD0
POF
Power-Off Flag
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set
by software.
GF1
General purpose Flag

Cleared by user for general purpose usage.
Set by user for general purpose usage.
GF0
General purpose Flag

Cleared by user for general purpose usage.
Set by user for general purpose usage.
PD
Power-Down mode bit

IDL
Idle mode bit

Description
Serial port Mode bit 1 for UART
Serial port Mode bit 0 for UART
Reserved
Reset Value = 00X1 0000b

Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset
doesnt affect the value of this bit.
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Table 42. BDRCON Register

BDRCON - Baud Rate Control Register (9Bh)
7
BRR
TBCK
RBCK
SPD
SRC
Bit
Number
Bit
Mnemonic
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
Reserved
BRR
Baud Rate Run Control bit

Cleared to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
TBCK
Transmission Baud rate Generator Selection bit for UART

Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
RBCK
Reception Baud Rate Generator Selection bit for UART

Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
SPD
Description
Baud Rate Speed Control bit for UART

Cleared to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
Baud Rate Source select bit in Mode 0 for UART
SRC
Cleared to select FOSC /12 as the Baud Rate Generator (FCLK PERIPH/6 in X2
mode).
Set to select the internal Baud Rate Generator for UARTs in mode 0.
Reset Value = XXX0 0000b

Not bit addressablef
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Interrupt System
The AT89C51RB2/RC2 has a total of 9 interrupt vectors: two external interrupts (INT0
and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in
Figure 22.
Figure 22. Interrupt Control System

High Priority
Interrupt
IPH, IPL
3
INT0
IE0
0
3
TF0
0
3
INT1
IE1
0
3
Interrupt
Polling
Sequence, Decreasing From
High to Low Priority
TF1
0
3
PCA IT
0
RI
TI
TF2
EXF2
0
3
KBD IT
0
3
SPI IT
Individual Enable
Global Disable
Low Priority
Interrupt
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (Table 45 and Table 47). This register also
contains a global disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (Table 48) and in the
Interrupt Priority High register (Table 46 and Table 47) shows the bit values and priority
levels associated with each combination.
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Registers
A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another

low-priority interrupt. A high-priority interrupt cant be interrupted by any other interrupt
source.
Table 43. Priority Level Bit Values
IPH. x
IPL. x
Interrupt Level Priority
0 (Lowest)
3 (Highest)
If two interrupt requests of different priority levels are received simultaneously, the
request of higher-priority level is serviced. If interrupt requests of the same priority level
are received simultaneously, an internal polling sequence determines which request is
serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
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Table 44. IENO Register
IEN0 - Interrupt Enable Register (A8h)
7
EA
EC
ET2
ES
ET1
EX1
ET0
EX0
Bit
Number
Bit
EA
EC
Enable All Interrupt Bit

Cleared to disable all interrupts.
Set to enable all interrupts.
PCA Interrupt Enable Bit
Cleared to disable.
Set to enable.
ET2
Timer 2 Overflow Interrupt Enable Bit

Cleared to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
ES
Serial Port Enable Bit

Cleared to disable serial port interrupt.
Set to enable serial port interrupt.
ET1

EX1
External Interrupt 1 Enable Bit

Cleared to disable external interrupt 1.
Set to enable external interrupt 1.
ET0

EX0
External Interrupt 0 Enable Bit

Cleared to disable external interrupt 0.
Set to enable external interrupt 0.

Bit addressable
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Table 45. IPL0 Register

IPL0 - Interrupt Priority Register (B8h)
7
PPCL
PT2L
PSL
PT1L
PX1L
PT0L
PX0L
Bit
Number
Bit
Reserved
PPCL
PCA Interrupt Priority Bit

see PPCH for priority level.
PT2L
Timer 2 Overflow Interrupt Priority Bit

see PT2H for priority level.
PSL
Serial Port Priority Bit

see PSH for priority level.
PT1L

PX1L
External Interrupt 1 Priority Bit

see PX1H for priority level.
PT0L

PX0L
External Interrupt 0 Priority Bit

see PX0H for priority level.

Bit addressable
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Table 46. IPH0 Register
IPH0 - Interrupt Priority High Register (B7h)
7
PPCH
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Bit
Number
7
Bit
-
Reserved
PPCH
PCA Interrupt Priority High Bit

PPCHPPCL Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PT2H
Timer 2 Overflow Interrupt Priority High Bit

PT2HPT2L
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PSH
Serial Port Priority High Bit

PSH PSL
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PT1H

PT1HPT1L
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PX1H
External Interrupt 1 Priority High Bit

PX1HPX1L
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PT0H

PT0HPT0L
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PX0H
External Interrupt 0 Priority High Bit

PX0H PX0L Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest

Not bit addressable
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Table 47. IEN1 Register

IEN1 - Interrupt Enable Register (B1h)
7
ESPI
KBD
Bit
Number
Bit
Reserved
Reserved
Reserved
Reserved
Reserved
ESPI
SPI Interrupt Enable Bit

Cleared to disable SPI interrupt.
Set to enable SPI interrupt.
KBD
Reserved
Keyboard Interrupt Enable Bit
Cleared to disable keyboard interrupt.
Set to enable keyboard interrupt.
Reset Value = XXXX X000b

Bit addressable
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Table 48. IPL1 Register
IPL1 - Interrupt Priority Register (B2h)
7
SPIL
KBDL
Bit
Number
Bit
Reserved
Reserved
Reserved
Reserved
Reserved
SPIL
KBDL
SPI Interrupt Priority Bit

see SPIH for priority level.
Reserved
Keyboard Interrupt Priority Bit
see KBDH for priority level.

Bit addressable
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Table 49. IPH1 Register

IPH1 - Interrupt Priority High Register (B3h)
7
SPIH
KBDH
Bit
Number
Bit
Reserved
Reserved
Reserved
Reserved
Reserved
SPIH
KBDH
SPI Interrupt Priority High Bit

SPIHSPIL
Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
Reserved
Keyboard Interrupt Priority High Bit
KB DHKBDL Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest

Not bit addressable
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Interrupt Sources and
Vector Addresses
Table 50. Interrupt Sources and Vector Addresses

Interrupt
Request
Vector
Number
Polling Priority
Interrupt Source
Address
Reset
INT0
IE0
0003h
Timer 0
TF0
000Bh
INT1
IE1
0013h
Timer 1
IF1
001Bh
UART
RI+TI
0023h
Timer 2
TF2+EXF2
002Bh
PCA
CF + CCFn (n = 0-4)
0033h
Keyboard
KBDIT
003Bh
SPI
SPIIT
004Bh
0000h
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Keyboard Interface
The AT89C51RB2/RC2 implements a keyboard interface allowing the connection of a

8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on
both high or low level. These inputs are available as alternate function of P1 and allow to
exit from idle and power-down modes.
The keyboard interfaces with the C51 core through 3 special function registers: KBLS,
the Keyboard Level Selection register (Table 53), KBE, the Keyboard interrupt Enable
register (Table 52), and KBF, the Keyboard Flag register (Table 51).
Interrupt
The keyboard inputs are considered as 8 independent interrupt sources sharing the
same interrupt vector. An interrupt enable bit (KBD in IEN1) allows global enable or disable of the keyboard interrupt (see Figure 23). As detailed in Figure 24 each keyboard
input has the capability to detect a programmable level according to KBLS. x bit value.
Level detection is then reported in interrupt flags KBF. x that can be masked by software
using KBE. x bits.
This structure allows keyboard arrangement from 1 by n to 8 by n matrix and allow
usage of P1 inputs for other purpose.
Figure 23. Keyboard Interface Block Diagram
VCC
P1:x
KBF. x
1
Internal Pull-up
KBE. x
KBLS. x
Figure 24. Keyboard Input Circuitry

P1.0
Input Circuitry
P1.1
Input Circuitry
P1.2
Input Circuitry
P1.3
Input Circuitry
P1.4
Input Circuitry
P1.5
Input Circuitry
P1.6
Input Circuitry
P1.7
Input Circuitry
KBDIT
Power Reduction Mode
64
KBD
IEN1
Keyboard Interface
Interrupt Request
P1 inputs allow exit from idle and power down modes as detailed in Section Powerdown Mode, page 82.
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Registers
Table 51. KBF Register

KBF - Keyboard Flag Register (9Eh)
7
KBF7
KBF6
KBF5
KBF4
KBF3
KBF2
KBF1
KBF0
Bit
Number
Bit
KBF7
Keyboard Line 7 Flag

Set by hardware when the Port line 7 detects a programmed level. It generates a
Keyboard interrupt request if the KBKBIE. 7 bit in KBIE register is set.
KBF6

Keyboard interrupt request if the KBIE. 6 bit in KBIE register is set.
KBF5

KBF4

KBF3

KBF2

KBF1

KBF0


This register is read only access, all flags are automatically cleared by reading the
register.
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Table 52. KBE Register

KBE - Keyboard Input Enable Register (9Dh)
7
KBE7
KBE6
KBE5
KBE4
KBE3
KBE2
KBE1
KBE0
Bit
Number
Bit
KBE7
Keyboard Line 7 Enable Bit

Cleared to enable standard I/O pin.
Set to enable KBF. 7 bit in KBF register to generate an interrupt request.
KBE6

KBE5

KBE4

KBE3

KBE2

KBE1

KBE0

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Table 53. KBLS Register
KBLS - Keyboard Level Selector Register (9Ch)
7
KBLS7
KBLS6
KBLS5
KBLS4
KBLS3
KBLS2
KBLS1
KBLS0
Bit
Number
Bit
KBLS7
Keyboard Line 7 Level Selection Bit

Cleared to enable a low level detection on Port line 7.
Set to enable a high level detection on Port line 7.
KBLS6

KBLS5

KBLS4

KBLS3

KBLS2

KBLS1

KBLS0

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Serial Port Interface

(SPI)
The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial
communication between the MCU and peripheral devices, including other MCUs.
Features
Features of the SPI Module include the following:
Signal Description
Full-duplex, three-wire synchronous transfers
Master or Slave operation
Eight programmable Master clock rates
Serial clock with programmable polarity and phase
Master Mode fault error flag with MCU interrupt capability
Write collision flag protection
Figure 25 shows a typical SPI bus configuration using one Master controller and many
Slave peripherals. The bus is made of three wires connecting all the devices.
Figure 25. SPI Master/Slaves Interconnection
Slave 1
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
VDD
Slave 4
Slave 3
MISO
MOSI
SCK
SS
0
1
2
3
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
PORT
Master
Slave 2
The Master device selects the individual Slave devices by using four pins of a parallel
port to control the four SS pins of the Slave devices.
Master Output Slave Input
(MOSI)
This 1-bit signal is directly connected between the Master Device and a Slave Device.
The MOSI line is used to transfer data in series from the Master to the Slave. Therefore,
it is an output signal from the Master, and an input signal to a Slave. A Byte (8-bit word)
is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
Master Input Slave Output

(MISO)
This 1-bit signal is directly connected between the Slave Device and a Master Device.
The MISO line is used to transfer data in series from the Slave to the Master. Therefore,
it is an output signal from the Slave, and an input signal to the Master. A Byte (8-bit
word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
SPI Serial Clock (SCK)
This signal is used to synchronize the data movement both in and out of the devices
through their MOSI and MISO lines. It is driven by the Master for eight clock cycles
which allows to exchange one Byte on the serial lines.
Slave Select (SS)
Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay
low for any message for a Slave. It is obvious that only one Master (SS high level) can
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drive the network. The Master may select each Slave device by software through port
pins (Figure 26). To prevent bus conflicts on the MISO line, only one slave should be
selected at a time by the Master for a transmission.
In a Master configuration, the SS line can be used in conjunction with the MODF flag in
the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and
SCK (see Error conditions).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin could be used as a general-purpose if the following conditions are met:
The device is configured as a Master and the SSDIS control bit in SPCON is set.
This kind of configuration can be found when only one Master is driving the network
and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in
the SPSTA will never be set(1).
The Device is configured as a Slave with CPHA and SSDIS control bits set (2). This
kind of configuration can happen when the system comprises one Master and one
Slave only. Therefore, the device should always be selected and there is no reason
that the Master uses the SS pin to select the communicating Slave device.
Note:
1. Clearing SSDIS control bit does not clear MODF.

2. Special care should be taken not to set SSDIS control bit when CPHA = 0 because
in this mode, the SS is used to start the transmission.
Baud Rate
In Master mode, the baud rate can be selected from a baud rate generator which is controlled by three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is
selected from one of seven clock rates resulting from the division of the internal clock by
2, 4, 8, 16, 32, 64 or 128.
Table 54 gives the different clock rates selected by SPR2:SPR1:SPR0.
Table 54. SPI Master Baud Rate Selection
SPR2
SPR1
SPR0
Clock Rate
Baud Rate Divisor (BD)
FCLK PERIPH /2
FCLK PERIPH /4
FCLK PERIPH/8
FCLK PERIPH /16
16
FCLK PERIPH /32
32
FCLK PERIPH /64
64
FCLK PERIPH /128
128
Dont Use
No BRG
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Functional Description
Figure 26 shows a detailed structure of the SPI Module.

Figure 26. SPI Module Block Diagram
Internal Bus
SPDAT
FCLK PERIPH
Clock
Divider
/4
/8
/16
/32
/64
/128
Shift Register
7
Receive Data Register
Pin
Control
Logic
Clock
Logic
M
S
Clock
Select
SPR2
MOSI
MISO
SCK
SS
SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPCON
SPI Interrupt Request
SPI
Control
8-bit bus
1-bit signal
SPSTA
SPIF WCOL
Operating Modes
MODF
The Serial Peripheral Interface can be configured in one of the two modes: Master
mode or Slave mode. The configuration and initialization of the SPI Module is made
through one register:
The Serial Peripheral Control register (SPCON)
Once the SPI is configured, the data exchange is made using:
SPCON
The Serial Peripheral STAtus register (SPSTA)
The Serial Peripheral DATa register (SPDAT)
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows
individual selection of a Slave SPI device; Slave devices that are not selected do not
interfere with SPI bus activities.
When the Master device transmits data to the Slave device via the MOSI line, the Slave
device responds by sending data to the Master device via the MISO line. This implies
full-duplex transmission with both data out and data in synchronized with the same clock
(Figure 27).
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Figure 27. Full-Duplex Master-Slave Interconnection
8-bit Shift register
SPI
Clock Generator
MISO
MISO
MOSI
MOSI
SCK
SS
Master MCU
8-bit Shift register
SCK
VDD
SS
VSS
Slave MCU
Master Mode
The SPI operates in Master mode when the Master bit, MSTR (1) , in the SPCON register
is set. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI Module by writing to the Serial Peripheral Data Register
(SPDAT). If the shift register is empty, the Byte is immediately transferred to the shift
register. The Byte begins shifting out on MOSI pin under the control of the serial clock,
SCK. Simultaneously, another Byte shifts in from the Slave on the Masters MISO pin.
The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSTA
becomes set. At the same time that SPIF becomes set, the received Byte from the Slave
is transferred to the receive data register in SPDAT. Software clears SPIF by reading
the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the
SPDAT.
Slave Mode
The SPI operates in Slave mode when the Master bit, MSTR (2), in the SPCON register is
cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave
device must be set to 0. SS must remain low until the transmission is complete.
In a Slave SPI Module, data enters the shift register under the control of the SCK from
the Master SPI Module. After a Byte enters the shift register, it is immediately transferred to the receive data register in SPDAT, and the SPIF bit is set. To prevent an
overflow condition, Slave software must then read the SPDAT before another Byte
enters the shift register (3). A Slave SPI must complete the write to the SPDAT (shift register) at least one bus cycle before the Master SPI starts a transmission. If the write to
the data register is late, the SPI transmits the data already in the shift register from the
previous transmission. The maximum SCK frequency allowed in slave mode is FCLK PERIPH
/4.
Transmission Formats
Software can select any of four combinations of serial clock (SCK) phase and polarity
using two bits in the SPCON: the Clock Polarity (CPOL (4) ) and the Clock Phase
(CPHA4). CPOL defines the default SCK line level in idle state. It has no significant
effect on the transmission format. CPHA defines the edges on which the input data are
sampled and the edges on which the output data are shifted (Figure 28 and Figure 29).
The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device.
1.
The SPI Module should be configured as a Master before it is enabled (SPEN set). Also,
the Master SPI should be configured before the Slave SPI.
2.
3.
The SPI Module should be configured as a Slave before it is enabled (SPEN set).
The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock
speed.
Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = 0).
4.
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Figure 28. Data Transmission Format (CPHA = 0)

1
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
SCK Cycle Number

SPEN (Internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI (from Master)
MISO (from Slave)
MSB
SS (to Slave)
Capture Point
Figure 29. Data Transmission Format (CPHA = 1)

1
MOSI (from Master)
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
MISO (from Slave)
MSB
bit6
bit5
bit4
bit3
bit2
bit1
SCK Cycle Number

SPEN (Internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
LSB
SS (to Slave)
Capture Point
Figure 30. CPHA/SS Timing

MISO/MOSI
Byte 1
Byte 2
Byte 3
Master SS
Slave SS
(CPHA = 0)
Slave SS
(CPHA = 1)
As shown in Figure 28, the first SCK edge is the MSB capture strobe. Therefore, the
Slave must begin driving its data before the first SCK edge, and a falling edge on the SS
pin is used to start the transmission. The SS pin must be toggled high and then low
between each Byte transmitted (Figure 30).
Figure 29 shows an SPI transmission in which CPHA is 1. In this case, the Master
begins driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first
SCK edge as a start transmission signal. The SS pin can remain low between transmissions (Figure 30). This format may be preffered in systems having only one Master and
only one Slave driving the MISO data line.
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Error Conditions
The following flags in the SPSTA signal SPI error conditions:
Mode Fault (MODF)
Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS)
pin is inconsistent with the actual mode of the device. MODF is set to warn that there
may be a multi-master conflict for system control. In this case, the SPI system is
affected in the following ways:
An SPI receiver/error CPU interrupt request is generated
The SPEN bit in SPCON is cleared. This disables the SPI
The MSTR bit in SPCON is cleared
When SS Disable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set
when the SS signal becomes 0.
However, as stated before, for a system with one Master, if the SS pin of the Master
device is pulled low, there is no way that another Master attempts to drive the network.
In this case, to prevent the MODF flag from being set, software can set the SSDIS bit in
the SPCON register and therefore making the SS pin as a general-purpose I/O pin.
Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set,
followed by a write to the SPCON register. SPEN Control bit may be restored to its original set state after the MODF bit has been cleared.
Write Collision (WCOL)
A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is
done during a transmit sequence.
WCOL does not cause an interruption, and the transfer continues uninterrupted.
Clearing the WCOL bit is done through a software sequence of an access to SPSTA
and an access to SPDAT.
Overrun Condition
An overrun condition occurs when the Master device tries to send several data Bytes
and the Slave devise has not cleared the SPIF bit issuing from the previous data Byte
transmitted. In this case, the receiver buffer contains the Byte sent after the SPIF bit was
last cleared. A read of the SPDAT returns this Byte. All others Bytes are lost.
This condition is not detected by the SPI peripheral.
SS Error Flag (SSERR)
A Synchronous Serial Slave Error occurs when SS goes high before the end of a
received data in slave mode. SSERR does not cause in interruption, this bit is cleared
by writing 0 to SPEN bit (reset of the SPI state machine).
Interrupts
Two SPI status flags can generate a CPU interrupt requests:

Table 55. SPI Interrupts
Flag
Request
SPIF (SP data transfer)
SPI Transmitter Interrupt request
MODF (Mode Fault)
SPI Receiver/Error Interrupt Request (if SSDIS = 0)
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer
has been completed. SPIF bit generates transmitter CPU interrupt requests.
Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is
inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error
CPU interrupt requests. When SSDIS is set, no MODF interrupt request is generated.
Figure 31 gives a logical view of the above statements.
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Figure 31. SPI Interrupt Requests Generation

SPIF
SPI Transmitter
CPU Interrupt Request
SPI
MODF
SPI Receiver/error
SSDIS
Registers
There are three registers in the Module that provide control, status and data storage functions. These registers
are describes in the following paragraphs.
Serial Peripheral Control

Register (SPCON)
The Serial Peripheral Control Register does the following:
Selects one of the Master clock rates
Configure the SPI Module as Master or Slave
Selects serial clock polarity and phase
Enables the SPI Module
Frees the SS pin for a general-purpose
Table 56 describes this register and explains the use of each bit
Table 56. SPCON Register
SPCON - Serial Peripheral Control Register (0C3H)
7
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
Bit Number
Bit Mnemonic
SPR2
SPEN
Description
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate.
Serial Peripheral Enable
Cleared to disable the SPI interface.
Set to enable the SPI interface.
SS Disable
Cleared to enable SS in both Master and Slave modes.
SSDIS
MSTR
Set to disable SS in both Master and Slave modes. In Slave mode,

this bit has no effect if CPHA =0. When SSDIS is set, no MODF
interrupt request is generated.
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
Clock Polarity
CPOL
Cleared to have the SCK set to 0 in idle state.

Set to have the SCK set to 1 in idle low.
Clock Phase
CPHA
Cleared to have the data sampled when the SCK leaves the idle
state (see CPOL).
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
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Bit Number
Bit Mnemonic
SPR1
SPR0
Description
SPR2
SPR1
FCLK PERIPH /2
FCLK PERIPH /4
FCLK PERIPH /8
FCLK PERIPH /16
FCLK PERIPH /32
FCLK PERIPH /64
FCLK PERIPH /128
Invalid
SPR0 Serial Peripheral Rate

Not bit addressable
Serial Peripheral Status Register
(SPSTA)
The Serial Peripheral Status Register contains flags to signal the following conditions:
Data transfer complete
Write collision
Inconsistent logic level on SS pin (mode fault error)
Table 57 describes the SPSTA register and explains the use of every bit in the register.
Table 57. SPSTA Register
SPSTA - Serial Peripheral Status and Control register (0C4H)
7
SPIF
WCOL
SSERR
MODF
Bit
Number
Bit
Serial Peripheral Data Transfer Flag
SPIF
Cleared by hardware to indicate data transfer is in progress or has been

approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
Write Collision Flag
WCOL
Cleared by hardware to indicate that no collision has occurred or has been

approved by a clearing sequence.
Set by hardware to indicate that a collision has been detected.
Synchronous Serial Slave Error Flag
SSERR
Set by hardware when SS is deasserted before the end of a received data.

Cleared by disabling the SPI (clearing SPEN bit in SPCON).
Mode Fault
MODF
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or

has been approved by a clearing sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level.
Reserved
Reserved
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Bit
Number
Bit
Reserved
Reserved
Reset Value = 00X0 XXXXb

Not Bit addressable
Serial Peripheral DATa Register
(SPDAT)
The Serial Peripheral Data Register (Table 58) is a read/write buffer for the receive data
register. A write to SPDAT places data directly into the shift register. No transmit buffer is
available in this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content
of the shift register.
Table 58. SPDAT Register
SPDAT - Serial Peripheral Data Register (0C5H)
7
R7
R6
R5
R4
R3
R2
R1
R0
Reset Value = Indeterminate

R7:R0: Receive data bits
SPCON, SPSTA and SPDAT registers may be read and written at any time while there
is no on-going exchange. However, special care should be taken when writing to them
while a transmission is on-going:
76
Do not change SPR2, SPR1 and SPR0
Do not change CPHA and CPOL
Do not change MSTR
Clearing SPEN would immediately disable the peripheral
Writing to the SPDAT will cause an overflow.
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Hardware Watchdog
Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer
Reset (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable
the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location
0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator
is running and there is no way to disable the WDT except through reset (either hardware
reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH
pulse at the RST-pin.
Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR
location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH
and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it
reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will
increment every machine cycle while the oscillator is running. This means the user must
reset the WDT at least every 16383 machine cycle. To reset the WDT the user must
write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter
cannot be read or written. When WDT overflows, it will generate an output RESET pulse
at the RST-pin. The RESET pulse duration is 96 x TCLK PERIPH, where T CLK PERIPH= 1/FCLK
PERIPH. To make the best use of the WDT, it should be serviced in those sections of code
that will periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 27 counter has been added to extend the Time-out
capability, ranking from 16 ms to 2 s @ FOSCA = 12 MHz. To manage this feature, see
WDTPRG register description, Table 59.
Table 59. WDTRST Register
WDTRST - Watchdog Reset Register (0A6h)
7
Reset Value = XXXX XXXXb

Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in
sequence.
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Table 60. WDTPRG Register

WDTPRG - Watchdog Timer Out Register (0A7h)
7
S2
S1
S0
Bit
Number
Bit
S2
WDT Time-out Select Bit 2
S1
S0
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0Selected Time-out
0(214 - 1) machine cycles, 16. 3 ms @ FOSCA = 12 MHz
1(215 - 1) machine cycles, 32.7 ms @ FOSCA = 12 MHz
0 (216 - 1) machine cycles, 65. 5 ms @ FOSCA = 12 MHz
1(217 - 1) machine cycles, 131 ms @ FOSCA = 12 MHz
0(218 - 1) machine cycles, 262 ms @ FOSCA = 12 MHz
1 (219 - 1) machine cycles, 542 ms @ FOSCA = 12 MHz
0(220 - 1) machine cycles, 1.05 s @ FOSCA = 12 MHz
1 (221 - 1) machine cycles, 2.09 s @ FOSCA = 12 MHz
Reset Value = XXXX X000
WDT During Power-down In Power-down mode the oscillator stops, which means the WDT also stops. While in
Power-down mode the user does not need to service the WDT. There are two methods
and Idle
of exiting Power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited
with hardware reset, servicing the WDT should occur as it normally should whenever the
AT89C51RB2/RC2 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the
interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the
device while the interrupt pin is held low, the WDT is not started until the interrupt is
pulled high. It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of power-down,
it is better to reset the WDT just before entering power-down.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
AT89C51RB2/RC2 while in Idle mode, the user should always set up a timer that will
periodically exit Idle, service the WDT, and re-enter Idle mode.
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ONCE Mode (ON
Chip Emulation)
The ONCE mode facilitates testing and debugging of systems using AT89C51RB2/RC2
without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the AT89C51RB2/RC2; the following sequence must be exercised:
Pull ALE low while the device is in reset (RST high) and PSEN is high.
Hold ALE low as RST is deactivated.
While the AT89C51RB2/RC2 is in ONCE mode, an emulator or test CPU can be used to
drive the circuit. Table 61 shows the status of the port pins during ONCE mode.
Normal operation is restored when normal reset is applied.
Table 61. External Pin Status during ONCE Mode
ALE
PSEN
Port 0
Port 1
Port 2
Port 3
XTAL1/2
Weak pull-up
Weak pull-up
Float
Weak pull-up
Weak pull-up
Weak pull-up
Active
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Power Management
Two power reduction modes are implemented in the AT89C51RB2/RC2: the Idle mode
and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be
dynamically divided by 2 using the X2 mode detailed in Section X2 Feature.
Reset
In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an
high level has to be applied on the RST pin. A bad level leads to a wrong initialization of
the internal registers like SFRs, Program Counter and to unpredictable behavior of
the microcontroller. A proper device reset initializes the AT89C51RB2/RC2 and vectors
the CPU to address 0000h. RST input has a pull-down resistor allowing power-on reset
by simply connecting an external capacitor to VDD as shown in Figure 32. A warm reset
can be applied either directly on the RST pin or indirectly by an internal reset source
such as the watchdog timer. Resistor value and input characteristics are discussed in
the Section DC Characteristics of the AT89C51RB2/RC2 datasheet.
Figure 32. Reset Circuitry and Power-On Reset
VDD
From Internal
Reset Source
To CPU Core
and Peripherals
RRST
RST
VDD
RST
VSS
RST input circuitry
Cold Reset
Power-on Reset
2 conditions are required before enabling a CPU start-up:
VDD must reach the specified VDD range
The level on X1 input pin must be outside the specification (VIH, VIL)
If one of these 2 conditions are not met, the microcontroller does not start correctly and
can execute an instruction fetch from anywhere in the program space. An active level
applied on the RST pin must be maintained till both of the above conditions are met. A
reset is active when the level V IH1 is reached and when the pulse width covers the
period of time where VDD and the oscillator are not stabilized. 2 parameters have to be
taken into account to determine the reset pulse width:
VDD rise time,
Oscillator startup time.
To determine the capacitor value to implement, the highest value of these 2 parameters
has to be chosen. Table 1 gives some capacitor values examples for a minimum RRST of
50 K and different oscillator startup and VDD rise times.
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Table 1. Minimum Reset Capacitor Value for a 50 k Pull-down Resistor(1)
VDD Rise Time
Oscillator
Start-Up Time
1 ms
10 ms
100 ms
5 ms
820 nF
1.2 F
12 F
20 ms
2.7 F
3.9 F
12 F
Note:
These values assume VDD starts from 0V to the nominal value. If the time between 2
on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully
discharged, leading to a bad reset sequence.
Warm Reset
To achieve a valid reset, the reset signal must be maintained for at least 2 machine
cycles (24 oscillator clock periods) while the oscillator is running. The number of clock
periods is mode independent (X2 or X1).
Watchdog Reset
As detailed in Section Hardware Watchdog Timer, page 77, the WDT generates a 96clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of
the application in case of external capacitor or power-supply supervisor circuit, a 1 k
resistor must be added as shown Figure 33.
Figure 33. Reset Circuitry for WDT Reset-out Usage
VDD
VDD
RST
RST
VSS
1K
To CPU Core
and Peripherals
RRST
VDD
From WDT
Reset Source
VSS
To Other
On-board
Circuitry
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Reset Recommendation
to Prevent Flash
Corruption
An example of bad initialization situation may occur in an instance where the bit
ENBOOT in AUXR1 register is initialized from the hardware bit BLJB upon reset. Since
this bit allows mapping of the bootloader in the code area, a reset failure can be critical.
If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet
due to a bad reset) the bit ENBOOT in SFRs may be set. If the value of Program
Counter is accidently in the range of the boot memory addresses then a Flash access
(write or erase) may corrupt the Flash on-chip memory.
It is recommended to use an external reset circuitry featuring power supply monitoring to
prevent system malfunction during periods of insufficient power supply voltage (power
supply failure, power supply switched off).
Idle Mode
An instruction that sets PCON.0 indicates that it is the last instruction to be executed
before going into Idle mode. In Idle mode, the internal clock signal is gated off to the
CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during idle. The port pins hold the
logical states they had at the time Idle was activated. ALE and PSEN hold at logic high
level.
There are two ways to terminate the Idle mode. Activation of any enabled interrupt will
cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will
be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normal operation or during idle. For example, an instruction that activates idle can
also set one or both flag bits. When idle is terminated by an interrupt, the interrupt service routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the reset.
Power-down Mode
To save maximum power, a Power-down mode can be invoked by software (see Table
14, PCON register).
In Power-down mode, the oscillator is stopped and the instruction that invoked Powerdown mode is the last instruction executed. The internal RAM and SFRs retain their
value until the Power-down mode is terminated. VCC can be lowered to save further
power. Either a hardware reset or an external interrupt can cause an exit from Powerdown. To properly terminate Power-down, the reset or external interrupt should not be
executed before VCC is restored to its normal operating level and must be held active
long enough for the oscillator to restart and stabilize.
Only external interrupts INT0, INT1 and Keyboard Interrupts are useful to exit from
Power-down. For that, interrupt must be enabled and configured as level or edge sensitive interrupt input. When Keyboard Interrupt occurs after a power down mode, 1024
clocks are necessary to exit to power down mode and enter in operating mode.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as
detailed in Figure 34. When both interrupts are enabled, the oscillator restarts as soon
as one of the two inputs is held low and power down exit will be completed when the first
input will be released. In this case, the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will
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be the one following the instruction that puts the AT89C51RB2/RC2 into Power-down
mode.
Figure 34. Power-down Exit Waveform
INT0
INT1
XTALA
or
XTALB
Active Phase
Power-down Phase
Oscillator Restart Phase
Active Phase
Exit from Power-down by reset redefines all the SFRs, exit from Power-down by external interrupt does no affect the SFRs.
Exit from Power-down by either reset or external interrupt or keyboard interrupt does not
affect the internal RAM content.
Note:
If idle mode is activated with Power-down mode (IDL and PD bits set), the exit sequence
is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and
idle mode is not entered.
Table 62 shows the state of ports during idle and power-down modes.
Table 62. State of Ports
Mode
Program Memory
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Idle
Internal
Port Data(1)
Port Data
Port Data
Port Data
Idle
External
Floating
Port Data
Address
Port Data
Power Down
Internal
Port Data(1)
Port Data
Port Data
Port Data
Power Down
External
Floating
Port Data
Port Data
Port Data
Port 0 can force a 0 level. A "one" will leave port floating.
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Power-off Flag
The Power-off flag allows the user to distinguish between a cold start reset and a
warm start reset.
A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while
VCC is still applied to the device and could be generated by an exit from Power-down.
The Power-off flag (POF) is located in PCON register (Table 63). POF is set by hardware when VCC rises from 0 to its nominal voltage. The POF can be set or cleared by
software allowing the user to determine the type of reset.
PCON - Power Control Register (87h)
7
SMOD1
SMOD0
POF
GF1
GF0
PD
IDL
Bit
Number
Bit
SMOD1
Serial port Mode Bit 1

SMOD0
Serial port Mode Bit 0

Reserved
POF
Power-off Flag
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by
software.
GF1
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
GF0
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
PD
Power-down mode bit

IDL
Idle Mode Bit

Reset Value = 00X1 0000b

Not bit addressable
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Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with
external program or data memory. Nevertheless, during internal code execution, ALE
signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting
AO bit.
The AO bit is located in AUXR register at bit location 0.As soon as AO is set, ALE is no
longer output but remains active during MOVX and MOVC instructions and external
fetches. During ALE disabling, ALE pin is weakly pulled high.
Table 64. AUXR Register
AUXR - Auxiliary Register (8Eh)
7
DPU
M0
XRS1
XRS0
EXTRAM
AO
Bit
Number
Bit
Disable Weak Pull-up
DPU
Cleared to activate the permanent weak pull up when latch data is logic 1
Set to disactive the weak pull-up.
Reserved
Pulse Length
M0
Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock
periods (default).
Set to stretch MOVX control: the RD and the WR pulse length is 30 clock
periods.
XRS1
XRS0
Reserved
XRAM Size
XRS1
0
XRS0
0
XRAM size
256 Bytes (default)
512 Bytes
768 Bytes
1024 Bytes
EXTRAM Bit
Cleared to access internal XRAM using movx @ Ri @ DPTR.
1
EXTRAM
Set to access external memory.

Programmed by hardware after Power-up regarding Hardware Security Byte
(HSB), default setting, XRAM selected.
AO
ALE Output Bit

Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if
X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC
instruction is used.
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Flash EEPROM
Memory
The Flash memory increases EPROM and ROM functionality with in-circuit electrical
erasure and programming. It contains 16K or 32K Bytes of program memory organized
in 128 or 256 pages of 128 Bytes. This memory is both parallel and serial In-system Programmable (ISP). ISP allows devices to alter their own program memory in the actual
end product under software control. A default serial loader (bootloader) program allows
ISP of the Flash.
The programming does not require external dedicated programming voltage. The necessary high programming voltage is generated on-chip using the standard VCC pins of
the microcontroller.
Features
Flash Programming and

Erasure
Flash EEPROM internal program memory.
Boot vector allows user provided Flash loader code to reside anywhere in the Flash
memory space. This configuration provides flexibility to the user.
Default loader in Boot ROM allows programming via the serial port without the need
of a user-provided loader.
Up to 64K Byte external program memory if the internal program memory is

disabled (EA = 0).
Programming and erase voltage with standard 5V or 3V V CC supply.
Read/Programming/Erase:
Byte-wise read without wait state
Byte or page erase and programming (10 ms)
Typical programming time (32K Bytes) in 10 s
Parallel programming with 87C51 compatible hardware interface to programmer
Programmable security for the code in the Flash
100K write cycles
10 years data retention
The 16K or 32K Bytes Flash is programmed by Bytes or by pages of 128 Bytes. It is not
necessary to erase a Byte or a page before programming. The programming of a Byte
or a page includes a self erase before programming.
There are three methods of programming the Flash memory:
86
First, the on-chip ISP bootloader may be invoked which will use low level routines to
program the pages. The interface used for serial downloading of Flash is the UART.
Second, the Flash may be programmed or erased in the end-user application by

calling low-level routines through a common entry point in the Boot ROM.
Third, the Flash may be programmed using the parallel method by using a
conventional EPROM programmer. The parallel programming method used by
these devices is similar to that used by EPROM 87C51 but it is not identical and the
commercially available programmers need to have support for the
AT89C51RB2/RC2. The bootloader and the Application Programming Interface
(API) routines are located in the BOOT ROM.
AT89C51RB2/RC2
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AT89C51RB2/RC2
Flash Registers and
Memory Map
Hardware Register
The AT89C51RB2/RC2 Flash memory uses several registers for its management:
Hardware registers can only be accessed through the parallel programming modes
which are handled by the parallel programmer.
Software registers are in a special page of the Flash memory which can be
accessed through the API or with the parallel programming modes. This page,
called "Extra Flash Memory", is not in the internal Flash program memory
addressing space.
The only hardware register of the AT89C51RB2/RC2 is called Hardware Security Byte
(HSB).
Table 65. Hardware Security Byte (HSB)
7
X2
BLJB
XRAM
LB2
LB1
LB0
Bit
Number
Bit
Mnemonic
X2
Description
X2 Mode
Programmed (0 value) to force X2 mode (6 clocks per instruction) after reset.
Unprogrammed (1 Value) to force X1 mode, Standard Mode, after reset
(Default).
Boot Loader Jump Bit
BLJB
Unprogrammed (1 value) to start the users application on next reset at address

0000h.
Programmed (0 value) to start the boot loader at address F800h on next reset
(Default).
Reserved
Reserved
XRAM
XRAM Config Bit (only programmable by programmer tools)

Programmed to inhibit XRAM after reset.
Unprogrammed, this bit to valid XRAM after reset (Default).
2-0
LB2-0
User Memory Lock Bits (only programmable by programmer tools)

See Table 66.
Boot Loader Jump Bit (BLJB)

One bit of the HSB, the BLJB bit, is used to force the boot address:
Flash Memory Lock Bits
When this bit is programmed (1 value) the boot address is 0000h.
When this bit is unprogrammed (1 value) the boot address is F800h. By default,
this bit is unprogrammed and the ISP is enabled.
The three lock bits provide different levels of protection for the on-chip code and data,
when programmed as shown in Table 66.
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Table 66. Program Lock Bits

Program Lock Bits
Security
Level
LB0
LB1
LB2
No program lock features enabled.
Protection Description
MOVC instruction executed from external program memory is disabled

from fetching code Bytes from internal memory, EA is sampled and
latched on reset, and further parallel programming of the Flash is
disabled. ISP and software programming with API are still allowed.
Same as 2, also verify through parallel programming interface is

disabled.
Same as 3, also external execution is disabled. (Default)
Note:
U: unprogrammed or "one" level.

P: programmed or "zero" level.
X: dont care
WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
These security bits protect the code access through the parallel programming interface.
They are set by default to level 4. The code access through the ISP is still possible and
is controlled by the "software security bits" which are stored in the extra Flash memory
accessed by the ISP firmware.
To load a new application with the parallel programmer, a chip erase must first be done.
This will set the HSB in its inactive state and will erase the Flash memory. The part reference can always be read using Flash parallel programming modes.
Default Values
Software Registers
The default value of the HSB provides parts ready to be programmed with ISP:
BLJB: Programmed force ISP operation.
X2: Unprogrammed to force X1 mode (Standard Mode).
XRAM: Unprogrammed to valid XRAM
LB2-0: Security level four to protect the code from a parallel access with maximum
security.
Several registers are used, in factory and by parallel programmers, to make copies of
hardware registers contents. These values are used by Atmel ISP.
These registers are in the "Extra Flash Memory" part of the Flash memory. This block is
also called "XAF" or eXtra Array Flash. They are accessed in the following ways:
Commands issued by the parallel memory programmer.
Commands issued by the ISP software.
Calls of API issued by the application software.
Several software registers are described in Table 67.
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Table 67. Default Values
Mnemonic
Definition
Default value
Description
SBV
Software Boot Vector
FCh
HSB
Hardware security Byte
BSB
Boot Status Byte
SSB
Software Security Byte
FFh
Copy of the Manufacturer Code
58h
ATMEL
Copy of the Device ID #1: Family Code
D7h
C51 X2, Electrically Erasable
Copy of the Device ID #2: memories
F7h
AT89C51RB2/RC2 32KB
size and type
FBh
AT89C51RB2/RC2 16 KB
Copy of the Device ID #3: name and

revision
EFh
AT89C51RB2/RC2 32KB,
Revision 0
FFh
AT89C51RB2/RC2 16 KB,
Revision 0
101x 1011b
0FFh
After programming the part by ISP, the BSB must be cleared (00h) in order to allow the
application to boot at 0000h.
The content of the Software Security Byte (SSB) is described in Table 67 and Table 69.
To assure code protection from a parallel access, the HSB must also be at the required
level.
Table 68. Software Security Byte
7
LB1
LB0
Bit
Number
Bit
Reserved
Do not clear this bit.
Reserved
Reserved
Reserved
Reserved
Reserved
1-0
LB1-0
User Memory Lock Bits

see Table 69
The two lock bits provide different levels of protection for the on-chip code and data,
when programmed as shown in Table 69.
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Table 69. Program Lock Bits of the SSB

Program Lock Bits
Security
level
LB0
LB1
No program lock features enabled.
ISP programming of the Flash is disabled.
Same as 2, also verify through ISP programming interface is disabled.
Note:
Flash Memory Status
Protection Description
U: unprogrammed or "one" level.

P: programmed or "zero" level.
X: dont care
WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
AT89C51RB2/RC2 parts are delivered in standard with the ISP boot in the Flash memory. After ISP or parallel programming, the possible contents of the Flash memory are
summarized on Figure 35.
Figure 35. Flash Memory Possible Contents

7FFFh T89C51RC2 32KB
3FFFh T89C51RB2 16KB
Virgin
Application
Virgin
or
Application
Application
Dedicated
ISP
Virgin
or
Application
Dedicated
ISP
0000h
Default
Memory Organization
After ISP
After ISP
After Parallel
Programming
After Parallel
Programming
In the AT89C51RB2/RC2, the lowest 16K or 32K of the 64 KB program memory address
space is filled by internal Flash.
When the EA pin is high, the processor fetches instructions from internal program Flash.
Bus expansion for accessing program memory from 16K or 32K upward automatic since
external instruction fetches occur automatically when the program counter exceeds
3FFFh (16K) or 7FFFh (32K). If the EA pin is tied low, all program memory fetches are
from external memory.
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Bootloader Architecture
Introduction
The bootloader manages a communication according to a specific defined protocol to

provide the whole access and service on Flash memory. Furthermore, all accesses and
routines can be called from the user application.
Figure 36. Diagram Context Description
Access via
Specific
Protocol
Bootloader
Flash Memory
Access From
User
Application
Acronyms
ISP: In-system Programming

SBV: Software Boot Vector
BSB: Boot Status Byte
SSB: Software Security Bit
HW : Hardware Byte
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Figure 37. Bootloader Functional Description
Exernal Host with
Specific Protocol
Communication
User
Application
User Call
Management (API )
ISP Communication
Management
Flash Memory
Management
Flash
Memory
On the above diagram, the on-chip bootloader processes are:
ISP Communication Management
The purpose of this process is to manage the communication and its protocol between
the on-chip bootloader and a external device. The on-chip ROM implement a serial protocol (see section Bootloader Protocol). This process translate serial communication
frame (UART) into Flash memory acess (read, write, erase ...).
User Call Management
Several Application Program Interface (API) calls are available for use by an application
program to permit selective erasing and programming of Flash pages. All calls are made
through a common interface (API calls), included in the ROM bootloader. The programming functions are selected by setting up the microcontrollers registers before making a
call to a common entry point (0xFFF0). Results are returned in the registers. The purpose on this process is to translate the registers values into internal Flash Memory
Management.
Flash Memory Management
This process manages low level access to Flash memory (performs read and write
access).
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Bootloader Functionality
Introduction
The bootloader can be activated by two means: Hardware conditions or regular boot
process.
The Hardware conditions (EA = 1, PSEN = 0) during the Reset# falling edge force the
on-chip bootloader execution. This allows an application to be built that will normally
execute the end users code but can be manually forced into default ISP operation.
As PSEN is an output port in normal operating mode (running user application or boorloader code) after reset, it is recommended to release PSEN after falling edge of reset
signal. The hardware conditions are sampled at reset signal falling edge, thus they can
be released at any time when reset input is low.
To ensure correct microcontroller startup, the PSEN pin should not be tied to ground
during power-on (See Figure 38).
Figure 38. Hardware conditions typical sequence during power-on.
VCC
PSEN
RST
The on-chip bootloader boot process is shown in Figure 39.

Purpose
Hardware Conditions
The Hardware Conditions force the bootloader execution whatever BLJB, BSB
and SBV values.
The Boot Loader Jump Bit forces the application execution.
BLJB = 0 => Boot loader execution.
BLJB = 1 => Application execution.
BLJB
The BLJB is a fuse bit in the Hardware Byte.

That can be modified by hardware (programmer) or by software (API).
Note:
The BLJB test is perform by hardware to prevent any program execution.
The Software Boot Vector contains the high address of custumer bootloader
stored in the application.
SBV = FCh (default value) if no custumer bootloader in user Flash.
SBV
Note:
The costumer bootloader is called by JMP [SBV]00h instruction.
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Boot Process
Figure 39. Bootloader process
RESET
If BLJB = 0 then ENBOOT bit (AUXR1) is set

else ENBOOT bit (AUXR1) is cleared
Yes (PSEN = 0, EA = 1, and ALE = 1 or not connected)
Hardware
Hardware
Condition?
FCON = 00h
FCON = F0h
BLJB = 1
ENBOOT = 0
BLJB!= 0
?
BLJB = 0
ENBOOT = 1
F800h
Software
FCON = 00h
?
yes = hardware boot conditions
BSB = 00h
?
PC = 0000h
USER APPLICATION
SBV = FCh
?
USER BOOT LOADER
Atmel BOOT LOADER
PC= [SBV]00h
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ISP Protocol Description
Physical Layer
Frame Description
The UART used to transmit information has the following configuration:
Character: 8-bit data
Parity: none
Stop: 1 bit
Flow control: none
Baud rate: autobaud is performed by the bootloader to compute the baud rate
choosen by the host.
The Serial Protocol is based on the Intel Hex-type records.

Intel Hex records consist of ASCII characters used to represent hexadecimal values and
are summarized below.
Table 70. Intel Hex Type Frame
Record Mark :
Reclen
Load Offset
Record Type
Data or Info
Checksum
1 byte
1 byte
2 bytes
1 bytes
n byte
1 byte
Record Mark:
Reclen:
Load Offset specifies the 16-bit starting load offset of the data Bytes,
therefore this field is used only for
Data Program Record (see Section ISP Commands Summary).
Record Type:
Record Type specifies the command type. This field is used to interpret the
remaining information within the frame. The encoding for all the current
record types is described in Section ISP Commands Summary.
Data/Info:
Reclen specifies the number of Bytes of information or data which follows

the Record Type field of the record.
Load Offset:
Record Mark is the start of frame. This field must contain :.
Data/Info is a variable length field. It consists of zero or more Bytes encoded

as pairs of hexadecimal digits. The meaning of data depends on the Record
Type.
Checksum:
The twos complement of the 8-bit Bytes that result from converting each pair
of ASCII hexadecimal digits to one Byte of binary, and including the Reclen
field to and including the last Byte of the Data/Info field. Therefore, the sum
of all the ASCII pairs in a record after converting to binary, from the Reclen
field to and including the Checksum field, is zero.
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Software Security Bits (SSB)
The SSB protects any Flash access from ISP command.

The command "Program Software Security bit" can only write a higher priority level.
There are three levels of security:
level 0: NO_SECURITY (FFh)
This is the default level.

From level 0, one can write level 1 or level 2.
level 1: WRITE_SECURITY (FEh )
For this level it is impossible to write in the Flash memory, BSB and SBV.
The Bootloader returns P on write access.
From level 1, one can write only level 2.
level 2: RD_WR_SECURITY (FCh
The level 2 forbids all read and write accesses to/from the Flash/EEPROM memory.
The Bootloader returns L on read or write access.
Only a full chip erase in parallel mode (using a programmer) or ISP command can reset
the software security bits.
From level 2, one cannot read and write anything.
Table 71. Software Security Byte Behavior
96
Level 0
Level 1
Level 2
Flash/EEPROM
Any access allowed
Read only access allowed
Any access not allowed
Fuse Bit
Any access allowed
BSB & SBV
Any access allowed
SSB
Any access allowed
Write level 2 allowed
Manufacturer
Info
Bootloader Info
Erase Block
Allowed
Not allowed
Not allowed
Full-chip Erase
Allowed
Allowed
Allowed
Blank Check
Allowed
Allowed
Allowed
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Full Chip Erase
The ISP command "Full Chip Erase" erases all User Flash memory (fills with FFh) and
sets some Bytes used by the bootloader at their default values:
BSB = FFh
SBV = FCh
SSB = FFh and finally erase the Software Security Bits
The Full Chip Erase does not affect the bootloader.

Checksum Error
When a checksum error is detected send X followed with CR&LF.
Flow Description
Overview
An initialization step must be performed after each Reset. After microcontroller reset,
the bootloader waits for an autobaud sequence ( see section autobaud performance).
When the communication is initialized the protocol depends on the record type
requested by the host.
FLIP, a software utility to implement ISP programming with a PC, is available from the
Atmel the web site.
Communication Initialization
The host initializes the communication by sending a U character to help the bootloader
to compute the baudrate (autobaud).
Figure 40. Initialization
Bootloader
Host
Init Communication
"U"
If (not received "U")

Else
Communication Opened
"U"
Performs Autobaud
Sends Back U Character
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Autobaud Performances
The ISP feature allows a wide range of baud rates in the user application. It is also
adaptable to a wide range of oscillator frequencies. This is accomplished by measuring
the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP
f e a tu r e r e q u ir e s th a t a n in itia l c h a ra c te r (a n u p p e rc a s e U ) b e se n t t o t h e
AT89C51RB2/RC2 to establish the baud rate. Table 72 shows the autobaud capability.
Table 72. Autobaud Performances

Frequency (MHz)
Baudrate (bit/s)
1.8432
2.4576
3.6864
7.3728
2400
OK
OK
OK
OK
OK
OK
OK
OK
OK
OK
4800
OK
OK
OK
OK
OK
OK
OK
OK
OK
9600
OK
OK
OK
OK
OK
OK
OK
OK
OK
19200
OK
OK
OK
OK
OK
OK
OK
38400
OK
OK
OK
OK
OK
57600
OK
OK
115200
OK
Baudrate (bit/s)
10
11.0592
12
14.318
14.746
16
20
24
26.6
2400
OK
OK
OK
OK
OK
OK
OK
OK
OK
4800
OK
OK
OK
OK
OK
OK
OK
OK
OK
9600
OK
OK
OK
OK
OK
OK
OK
OK
OK
19200
OK
OK
OK
OK
OK
OK
OK
OK
OK
38400
OK
OK
OK
OK
OK
OK
OK
OK
57600
OK
OK
OK
OK
OK
OK
OK
115200
OK
OK
OK
Frequency (MHz)
Command Data Stream

Protocol
98
All commands are sent using the same flow. Each frame sent by the host is echoed by
the bootloader.
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Figure 41. Command Flow
Host
Bootloader
Sends first character of the

Frame
":"
If (not received ":")
":"
Else
Sends echo and start
reception
Sends frame (made of 2 ASCII

characters per Byte)
Echo analysis
Write/Program Commands
Gets frame, and sends back ec

for each received Byte
This flow is common to the following frames:
Flash/EEPROM Programming Data Frame
EOF or Atmel Frame (only Programming Atmel Frame)
Config Byte Programming Data Frame
Baud Rate Frame
Description
Figure 42. Write/Program Flow
Bootloader
Host
Send Write Command
Write Command
Wait Write Command
OR
Wait Checksum Error
Checksum error
X & CR & LF
Send Checksum error
COMMAND ABORTED
NO_SECURITY
OR
Wait Security Error
P & CR & LF
Send Security error
COMMAND ABORTED
Wait Programming
Wait COMMAND_OK
. & CR & LF
Send COMMAND_OK
COMMAND FINISHED
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Example
Programming Data (write 55h at address 0010h in the Flash)
HOST
: 01 0010 00 55 9A
BOOTLOADER
: 01 0010 00 55 9A . CR LF
Programming Atmel function (write SSB to level 2)

HOST
: 02 0000 03 05 01 F5
BOOTLOADER
: 02 0000 03 05 01 F5. CR LF
Writing Frame (write BSB to 55h)
100
HOST
: 03 0000 03 06 00 55 9F
BOOTLOADER
: 03 0000 03 06 00 55 9F . CR LF
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Blank Check Command
Description
Figure 43. Blank Check Flow
Bootloader
Host
Blank Check Command
Send Blank Check Command
Wait Blank Check Command
OR
Checksum error
X & CR & LF
Wait Checksum Error
Send Checksum error
COMMAND ABORTED
Flash blank
OR
. & CR & LF
Wait COMMAND_OK
Send COMMAND_OK
COMMAND FINISHED
address & CR & LF
Wait Address not

erased
Send first Address

not erased
COMMAND FINISHED
Example
Blank Check ok
HOST
: 05 0000 04 0000 7FFF 01 78
BOOTLOADER
: 05 0000 04 0000 7FFF 01 78 . CR LF
Blank Check ko at address xxxx

HOST
: 05 0000 04 0000 7FFF 01 78
BOOTLOADER
: 05 0000 04 0000 7FFF 01 78 xxxx CR LF
Blank Check with checksum error

HOST
: 05 0000 04 0000 7FFF 01 70
BOOTLOADER
: 05 0000 04 0000 7FFF 01 70 X CR LF CR LF
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Display Data
Description
Figure 44. Display Flow
Bootloader
Host
Send Display Command
Display Command
Wait Display Command
OR
Wait Checksum Error
Checksum error
X & CR & LF
Send Checksum Error
COMMAND ABORTED
RD_WR_SECURITY
OR
Wait Security Error
L & CR & LF
Send Security Error
COMMAND ABORTED
Read Data
All data read
Complete Frame
Wait Display Data
All data read
COMMAND FINISHED
Note:
102
"Address = "
"Reading value"
CR & LF
Send Display Data
All data read
COMMAND FINISHED
The maximum size of block is 400h. To read more than 400h Bytes, the Host must send a new command.
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Example
Display data from address 0000h to 0020h
: 05 0000 04 0000 0020 00 D7
HOST
Read Function
BOOTLOADER
: 05 0000 04 0000 0020 00 D7
BOOTLOADER
0000=-----data------ CR LF
(16 data)
BOOTLOADER
0010=-----data------ CR LF
(16 data)
BOOTLOADER
0020=data CR LF
( 1 data)
This flow is similar for the following frames:
Reading Frame
EOF Frame/Atmel Frame (only reading Atmel Frame)
Description
Figure 45. Read Flow
Bootloader
Host
Read Command
Send Read Command
Wait Read Command
OR
Checksum error
X & CR & LF
Wait Checksum Error
Send Checksum error
COMMAND ABORTED
RD_WR_SECURITY
OR
L & CR & LF
Wait Security Error
Send Security error
COMMAND ABORTED
Read Value
value & . & CR & LF
Wait Value of Data
Send Data Read
COMMAND FINISHED
Example
Read function (read SBV)
HOST
: 02 0000 05 07 02 F0
BOOTLOADER
: 02 0000 05 07 02 F0 Value . CR LF
Atmel Read function (read Bootloader version)

HOST
: 02 0000 01 02 00 FB
BOOTLOADER
: 02 0000 01 02 00 FB Value . CR LF
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ISP Commands Summary
Table 73. ISP Commands Summary

Command
Command Name
Data[0]
Data[1]
Command Effect
Program Nb Data Byte.
00h
Bootloader will accept up to 128 (80h)

data Bytes. The data Bytes should be
128 Byte page Flash boundary.
Program Data
00h
Erase block0 (0000h-1FFFh)
20h
40h
80h
Erase block3 (8000h- BFFFh)
C0h
Erase block4 (C000h- FFFFh)
03h
00h
Hardware Reset
04h
00h
Erase SBV & BSB
00h
Program SSB level 1
01h
Program SSB level 2
00h
Program BSB (value to write in data[2])
01h
Program SBV (value to write in data[2])
Full Chip Erase (This command needs

about 6 sec to be executed)
01h
05h
03h
Write Function
06h
07h
0Ah
02h
Program Osc fuse (value to write in

data[2])
04h
Program BLJB fuse (value to write in

data[2])
08h
Program X2 fuse (value to write in

data[2])
Display Data
Data[0:1] = start address
04h
Display Function
Note: The maximum number of data

that can be read with a single
Data[4] = 00h -> Display data command frame (difference between
start and end address) is 1kbyte.
Data[4] = 01h -> Blank check
Blank Check
Data [2:3] = end address
00h
Manufacturer ID
01h
Device ID #1
02h
Device ID #2
03h
Device ID #3
00h
Read SSB
01h
Read BSB
02h
Read SBV
06h
Read Extra Byte
00h
Read Hardware Byte
00h
Read Device Boot ID1
01h
Read Device Boot ID2
00h
Read Bootloader Version
00h
05h
Read Function
07h
0Bh
0Eh
0Fh
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API Call Description
Several Application Program Interface (API) calls are available for use by an application
program to permit selective erasing and programming of Flash pages. All calls are made
through a common interface, PGM_MTP. The programming functions are selected by
setting up the microcontrollers registers before making a call to PGM_MTP at FFF0h.
Results are returned in the registers.
When several Bytes have to be programmed, it is highly recommended to use the Atmel
API PROGRAM DATA PAGE call. Indeed, this API call writes up to 128 Bytes in a single command.
All routines for software access are provided in the C Flash driver available at Atmels
web site.
The API calls description and arguments are shown in Table 74.
Table 74. API Call Summary

Command
R1
DPTR0
DPTR1
Returned Value
Command Effect
READ MANUF ID
00h
XXh
0000h
XXh
ACC = Manufacturer
Id
Read Manufacturer identifier
READ DEVICE ID1
00h
XXh
0001h
XXh
ACC = Device Id 1
Read Device identifier 1
READ DEVICE ID2
00h
XXh
0002h
XXh
ACC = Device Id 2
READ DEVICE ID3
00h
XXh
0003h
XXh
ACC = Device Id 3
DPH = 00h
ERASE BLOCK
01h
XXh
DPH = 20h
Erase block 0
00h
ACC = DPH
DPH = 40h
PROGRAM DATA
BYTE
02h
Vaue to write
Address of
byte to
program
Erase block 2
XXh
ACC = 0: DONE
DPH = 00h
DPH = 00h
Set SSB level 2
DPL = 01h
05h
XXh
Program up one data byte in the on-chip

flash memory.
Set SSB level 1
DPL = 00h
PROGRAM SSB
Erase block 1
00h
ACC = SSB value
DPH = 00h
Set SSB level 0
DPL = 10h
DPH = 00h
Set SSB level 1
DPL = 11h
PROGRAM BSB
06h
New BSB
value
0000h
XXh
none
Program boot status byte
PROGRAM SBV
06h
New SBV
value
0001h
XXh
none
Program software boot vector
READ SSB
07h
XXh
0000h
XXh
ACC = SSB
Read Software Security Byte
READ BSB
07h
XXh
0001h
XXh
ACC = BSB
Read Boot Status Byte
READ SBV
07h
XXh
0002h
XXh
ACC = SBV
Read Software Boot Vector
09h
Number of
byte to
program
Address of
the first byte
to program in
the Flash
memory
Address in
XRAM of the
first data to
program
ACC = 0: DONE
Remark: number of bytes to program is

limited such as the Flash write remains in a
single 128 bytes page. Hence, when ACC
is 128, valid values of DPL are 00h, or, 80h.
PROGRAM DATA
PAGE
Program up to 128 bytes in user Flash.
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Table 74. API Call Summary (Continued)

Command
R1
PROGRAM X2 FUSE
0Ah
PROGRAM BLJB
FUSE
0Ah
READ HSB
0Bh
READ BOOT ID1
DPTR0
DPTR1
Returned Value
Command Effect
0008h
XXh
none
Program X2 fuse bit with ACC
0004h
XXh
none
Program BLJB fuse bit with ACC
XXh
XXXXh
XXh
ACC = HSB
Read Hardware Byte
0Eh
XXh
DPL = 00h
XXh
ACC = ID1
Read boot ID1
READ BOOT ID2
0Eh
XXh
DPL = 01h
XXh
ACC = ID2
Read boot ID2
READ BOOT VERSION
0Fh
XXh
XXXXh
XXh
ACC = Boot_Version
Read bootloader version
106
A
Fuse value
00h or 01h
Fuse value
00h or 01h
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Electrical Characteristics
Absolute Maximum Ratings
Note:
C = commercial......................................................0C to 70C
I = industrial ........................................................-40C to 85C
Storage Temperature .................................... -65C to + 150C
Voltage on VCC to VSS (standard voltage) .........-0.5V to + 6.5V
Voltage on VCC to VSS (low voltage)..................-0.5V to + 4.5V
Voltage on Any Pin to VSS ..........................-0.5V to VCC + 0.5V
Power Dissipation .............................................................. 1 W
Stresses at or above those listed under Absolute

Maximum Ratings may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Power dissipation value is based on the maximum
allowable die temperature and the thermal resistance of the package.
DC Parameters for
Standard Voltage
TA = -40C to +85C; VSS = 0V;
VCC =2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)
VCC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only)
Symbol
Parameter
Min
VIL
Input Low Voltage
VIH
Input High Voltage except RST, XTAL1
VIH1(9)
Input High Voltage RST, XTAL1
Typ
Max
Unit
Test Conditions
-0.5
0.2 VCC - 0.1
0.2 VCC + 0.9
VCC + 0.5
0.7 VCC
VCC + 0.5
0.3
IOL = 100 A(4)
0.45
IOL = 1.6 mA(4)
1.0
IOL = 3.5 mA(4)
0.45
0.3
IOL = 200 A(4)
0.45
IOL = 3.2 mA(4)
1.0
IOL = 7.0 mA(4)
0.45
VCC = 4.5V to 5.5V
VOL
Output Low Voltage, ports 1, 2, 3, 4 (6)
VCC = 2.7V to 5.5V

IOL = 0.8 mA(4)
VCC = 4.5V to 5.5V
VOL1
Output Low Voltage, port 0, ALE, PSEN (6)
VCC = 2.7V to 5.5V

IOL = 1.6 mA(4)
VCC = 5V 10%
VOH
Output High Voltage, ports 1, 2, 3, 4
VCC - 0.3
IOH = -10 A
VCC - 0.7
IOH = -30 A
VCC - 1.5
IOH = -60 A
0.9 VCC
VCC = 2.7V to 5.5V

IOH = -10 A
107
4180E805110/06
TA = -40C to +85C; VSS = 0V;

VCC =2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)
VCC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only) (Continued)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VCC = 5V 10%
VOH1
Output High Voltage, port 0, ALE, PSEN
VCC - 0.3
IOH = -200 A
VCC - 0.7
IOH = -3.2 mA
VCC - 1.5
IOH = -7.0 mA
0.9 VCC
VCC = 2.7V to 5.5V
RRST
RST Pulldown Resistor
50
200
(5)
250
IOH = -10 A
IIL
Logical 0 Input Current ports 1, 2, 3, 4 and 5
-50
VIN = 0.45V
ILI
Input Leakage Current for P0 only
10
0.45V < VIN < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3, 4
-650
VIN = 2.0V
CIO
Capacitance of I/O Buffer
10
pF
Fc = 3 MHz
TA = 25C
IPD
Power Down Current
150
4.5V < VCC < 5.5V (3)
100
ICCOP
Power Supply Current on normal mode
0.4 x Frequency (MHz) + 5
mA
VCC = 5.5V(1)
ICCIDLE
Power Supply Current on idle mode
mA
VCC = 5.5V(1)
ICCProg
Power Supply Current during flash Write / Erase
mA
VCC = 5.5V(8)
Notes:
108
0.4 x
Frequency
(MHz) + 20
1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with T CLCH, TCHCL = 5 ns (see Figure 49.), VIL =
VSS + 0.5V,
VIH = V CC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure
46).
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH , TCHCL = 5 ns, V IL = VSS + 0.5V, VIH = VCC 0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = V SS (see Figure 47).
3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = V CC; XTAL2 NC.; RST = V SS (see Figure 48).
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typical are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, V OL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
7. For other values, please contact your sales office.
8. Icc Flash Write operation current while an on-chip flash page write is on going.
9. Flash Retention is guaranteed with the same formula for VCC Min down to 0.
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
DC Parameters for Low
Voltage
TA = 0C to +70C; VSS = 0V; VCC = 2.7V to 3.6V; F = 0to 40 MHz
TA = -40C to +85C; VSS = 0V; VCC = 2.7V to 3.6V; F = 0 to 40 MHz
Symbol
Parameter
Min
VIL
Input Low Voltage
VIH
Input High Voltage except RST, XTAL1
VIH1
Input High Voltage, RST, XTAL1
Typ
Max
Unit
-0.5
0.2 VCC - 0.1
0.2 VCC + 0.9
VCC + 0.5
0.7 VCC
VCC + 0.5
0.45
IOL = 0.8 mA(4)
0.45
IOL = 1.6 mA(4)
(6)
Test Conditions
VOL
Output Low Voltage, ports 1, 2, 3, 4
VOL1
Output Low Voltage, port 0, ALE, PSEN
VOH
Output High Voltage, ports 1, 2, 3, 4
0.9 VCC
IOH = -10 A
VOH1
Output High Voltage, port 0, ALE, PSEN
0.9 VCC
IOH = -40 A
(6)
IIL
Logical 0 Input Current ports 1, 2, 3, 4
-50
VIN = 0.45 V
ILI
Input Leakage Current for P0 only
10
0.45V < VIN < VCC
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3,
-650
VIN = 2.0V
250
10
pF
Fc = 3 MHz
TA = 25C
50
VCC = 2.7V to
3.6V(3)
RRST
RST Pulldown Resistor
CIO
Capacitance of I/O Buffer
IPD
Power Down Current
50
200 (5)
10 (5)
ICCOP
Power Supply Current on normal mode
mA
VCC = 3.6 V(1)
ICCIDLE
Power Supply Current on idle mode
mA
VCC = 3.6 V(2)
mA
VCC = 5.5V(8)
ICCProg
Notes:
Power Supply Current during flash Write / Erase
0.4 x
Frequency
(MHz) +
20
1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with T CLCH, TCHCL = 5 ns (see Figure 49.), VIL =
VSS + 0.5V,
VIH = V CC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure
46).
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH , TCHCL = 5 ns, V IL = VSS + 0.5V, VIH = VCC 0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = V SS (see Figure 47).
3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = V CC; XTAL2 NC.; RST = V SS (see Figure 48).
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typical are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
109
4180E805110/06
If IOL exceeds the test condition, V OL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
7. For other values, please contact your sales office.
8. Icc Flash Write operation current while an on-chip flash page write is on going.
Figure 46. ICC Test Condition, Active Mode

VCC
ICC
VCC
VCC
P0
VCC
RST
(NC)
CLOCK
SIGNAL
EA
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 47. ICC Test Condition, Idle Mode

VCC
ICC
VCC
VCC
P0
RST
EA
XTAL2
XTAL1
VSS
(NC)
CLOCK
SIGNAL
Figure 48. ICC Test Condition, Power-down Mode

VCC
ICC
V CC
VCC
P0
RST
(NC)
EA
XTAL2
XTAL1
VSS
Figure 49. Clock Signal Waveform for ICC Tests in Active and Idle Modes
VCC-0.5V
0.45V
TCLCH
TCHCL
TCLCH = TCHCL = 5ns.
110
0.7VCC
0.2VCC -0.1
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
AC Parameters
Explanation of the AC
Symbols
Each timing symbol has 5 characters. The first character is always a T (stands for
time). The other characters, depending on their positions, stand for the name of a signal
or the logical status of that signal. The following is a list of all the characters and what
they stand for.
Example:TAVLL = Time for Address Valid to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.
(Load Capacitance for port 0, ALE and PSEN = 100 pF; Load Capacitance for all other
outputs = 80 pF.)
Table 75 Table 78, and Table 80 give the description of each AC symbols.
Table 77, Table 79 and Table 81 give the AC parameterfor each range.
Table 76, Table 77 and Table 82 gives the frequency derating formula of the AC parameter for each speed range description. To calculate each AC symbols, take the x value
in the correponding column (-M or -L) and use this value in the formula.
Example: TLLIU for -M and 20 MHz, Standard clock.
x = 35 ns
T 50 ns
TCCIV = 4T - x = 165 ns
External Program Memory

Characteristics
Table 75. Symbol Description

Symbol
T
Parameter
Oscillator clock period
TLHLL
ALE pulse width
TAVLL
Address Valid to ALE
TLLAX
Address Hold after ALE
TLLIV
ALE to Valid Instruction In
TLLPL
ALE to PSEN
TPLPH
PSEN Pulse Width
TPLIV
PSEN to Valid Instruction In
TPXIX
Input Instruction Hold after PSEN
TPXIZ
Input Instruction Float after PSEN
TAVIV
Address to Valid Instruction In
TPLAZ
PSEN Low to Address Float
111
4180E805110/06
Table 76. AC Parameters for a Fix Clock

Symbol
-M
-L
Min
Max
Min
Units
Max
25
25
ns
TLHLL
35
35
ns
TAVLL
ns
TLLAX
ns
TLLIV
n 65
65
ns
TLLPL
ns
TPLPH
50
50
ns
TPLIV
30
TPXIX
30
ns
ns
TPXIZ
10
10
ns
TAVIV
80
80
ns
TPLAZ
10
10
ns
Table 77. AC Parameters for a Variable Clock
112
Symbol
Type
Standard
Clock
X2 Clock
X Parameter for M Range
X Parameter for
-L Range
Units
TLHLL
Min
2T-x
T-x
15
15
ns
TAVLL
Min
T-x
0.5 T - x
20
20
ns
TLLAX
Min
T-x
0.5 T - x
20
20
ns
TLLIV
Max
4T-x
2T-x
35
35
ns
TLLPL
Min
T-x
0.5 T - x
15
15
ns
TPLPH
Min
3T-x
1.5 T - x
25
25
ns
TPLIV
Max
3T-x
1.5 T - x
45
45
ns
TPXIX
Min
ns
TPXIZ
Max
T-x
0.5 T - x
15
15
ns
TAVIV
Max
5T-x
2.5 T - x
45
45
ns
TPLAZ
Max
10
10
ns
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
External Program Memory
Read Cycle
12 TCLCL
TLHLL
TLLIV
ALE
TLLPL
TPLPH
PSEN
TLLAX
TAVLL
PORT 0
INSTR IN
TPLIV
TPLAZ
A0-A7
TPXAV
TPXIZ
TPXIX
INSTR IN
A0-A7
INSTR IN
TAVIV
PORT 2
External Data Memory

Characteristics
ADDRESS
OR SFR-P2
ADDRESS A8-A15
ADDRESS A8-A15

Symbol
Parameter
TRLRH
RD Pulse Width
TWLWH
WR Pulse Width
TRLDV
RD to Valid Data In
TRHDX
Data Hold After RD
TRHDZ
Data Float After RD
TLLDV
ALE to Valid Data In
TAVDV
Address to Valid Data In
TLLWL
ALE to WR or RD
TAVWL
Address to WR or RD
TQVWX
Data Valid to WR Transition
TQVWH
Data set-up to WR High
TWHQX
Data Hold After WR
TRLAZ
RD Low to Address Float
TWHLH
RD or WR High to ALE high
113
4180E805110/06

-M
Symbol
Min
TRLRH
125
125
ns
TWLWH
125
125
ns
TRLDV
TRHDX
114
-L
Max
Min
95
0
Max
95
0
Units
ns
ns
TRHDZ
25
25
ns
TLLDV
155
155
ns
TAVDV
160
160
ns
105
ns
TLLWL
45
TAVWL
70
70
ns
TQVWX
ns
TQVWH
155
155
ns
TWHQX
10
10
ns
TRLAZ
ns
TWHLH
105
45
45
45
ns
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Symbol
Type
Standard
Clock
X2 Clock
X Parameter for L Range
Units
TRLRH
Min
6T-x
3T-x
25
25
ns
TWLWH
Min
6T-x
3T-x
25
25
ns
TRLDV
Max
5T-x
2.5 T - x
30
30
ns
TRHDX
Min
ns
TRHDZ
Max
2T-x
T-x
25
25
ns
TLLDV
Max
8T-x
4T -x
45
45
ns
TAVDV
Max
9T-x
4.5 T - x
65
65
ns
TLLWL
Min
3T-x
1.5 T - x
30
30
ns
TLLWL
Max
3T+x
1.5 T + x
30
30
ns
TAVWL
Min
4T-x
2T-x
30
30
ns
TQVWX
Min
T-x
0.5 T - x
20
20
ns
TQVWH
Min
7T-x
3.5 T - x
20
20
ns
TWHQX
Min
T-x
0.5 T - x
15
15
ns
TRLAZ
Max
ns
TWHLH
Min
T-x
0.5 T - x
20
20
ns
TWHLH
Max
T+x
0.5 T + x
20
20
ns
External Data Memory Write

Cycle
TWHLH
ALE
PSEN
TLLWL
TWLWH
WR
TLLAX
PORT 0
A0-A7
TQVWX
TQVWH
TWHQX
DATA OUT
TAVWL
PORT 2
ADDRESS
OR SFR-P2
ADDRESS A8-A15 OR SFR P2
115
4180E805110/06
External Data Memory Read Cycle

TWHLH
TLLDV
ALE
PSEN
TLLWL
TRLRH
RD
TRHDZ
TAVDV
TLLAX
PORT 0
TRHDX
A0-A7
DATA IN
TRLAZ
TAVWL
PORT 2
ADDRESS
OR SFR-P2
Serial Port Timing - Shift

Register Mode
ADDRESS A8-A15 OR SFR P2

Symbol
Parameter
TXLXL
Serial port clock cycle time
TQVHX
Output data set-up to clock rising edge
TXHQX
Output data hold after clock rising edge
TXHDX
Input data hold after clock rising edge
TXHDV
Clock rising edge to input data valid

-M
-L
Symbol
Min
Max
TXLXL
300
300
ns
TQVHX
200
200
ns
TXHQX
30
30
ns
TXHDX
ns
TXHDV
Min
Max
117
Units
117
ns
Table 82. AC Parameters for a Variable Clock
116
Symbol
Type
Standard
Clock
X2 Clock
X Parameter for -L
Range
TXLXL
Min
12 T
6T
TQVHX
Min
10 T - x
5T-x
50
50
ns
TXHQX
Min
2T-x
T-x
20
20
ns
TXHDX
Min
ns
TXHDV
Max
10 T - x
5 T- x
133
133
ns
Units
ns
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Shift Register Timing
Waveforms
INSTRUCTION
ALE
TXLXL
CLOCK
TXHQX
TQVXH
OUTPUT DATA
WRITE to SBUF
INPUT DATA
TXHDX
TXHDV
VALID
VALID
SET TI
VALID
VALID
VALID
VALID
VALID
SET RI
CLEAR RI
External Clock Drive

Waveforms
VALID
VCC-0.5V
0.45V
0.7VCC
0.2VCC-0.1
TCHCL
TCHCX
TCLCH
TCLCX
TCLCL
AC Testing Input/Output
Waveforms
VCC -0.5V
0.2 VCC + 0.9
INPUT/OUTPUT
0.2 VCC - 0.1
0.45 V
AC inputs during testing are driven at VCC - 0.5 for a logic 1 and 0.45V for a logic 0.
Timing measurement are made at VIH min for a logic 1 and VIL max for a logic 0.
Float Waveforms
FLOAT
VOH - 0.1 V
VOL + 0.1 V
VLOAD
VLOAD + 0.1 V
VLOAD - 0.1 V
For timing purposes as port pin is no longer floating when a 100 mV change from load
voltage occurs and begins to float when a 100 mV change from the loaded VOH/V OL level
occurs. IOL/IOH 20mA.
Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
117
4180E805110/06
Figure 50. Internal Clock Signals

INTERNAL
CLOCK
STATE4
STATE5
STATE6
STATE1
STATE2
STATE3
STATE4
STATE5
P1
P1
P1
P1
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
XTAL2
ALE
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
EXTERNAL PROGRAM MEMORY FETCH

PSEN
P0
DATA
SAMPLED
FLOAT
P2 (EXT)
PCL OUT
DATA
SAMPLED
FLOAT
PCL OUT
DATA
SAMPLED
FLOAT
PCL OUT
INDICATES ADDRESS TRANSITIONS
READ CYCLE
RD
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
P0
DPL OR Rt OUT
P2
DATA
SAMPLED
FLOAT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
WRITE CYCLE
WR
P0
PCL OUT (EVEN IF PROGRAM

MEMORY IS INTERNAL)
DPL OR Rt OUT
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
DATA OUT
P2
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PORT OPERATION
OLD DATA NEW DATA
MOV PORT SRC
P0 PINS SAMPLED
P0 PINS SAMPLED
MOV DEST P0
MOV DEST PORT (P1. P2. P3)
(INCLUDES INTO. INT1. TO T1)
SERIAL PORT SHIFT CLOCK
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
TXD (MODE 0)
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however,
ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA = 25C fully loaded) RD and WR propagation
delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC
specifications.
118
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Ordering Information
Table 83. Possible Order Entries
Part Number
Supply Voltage
Temperature Range
Package
Packing
Product Marking
AT89C51RB2-3CSIM
5V
Industrial
PDIL40
Stick
89C51RB2-IM
AT89C51RB2-SLSCM
5V
Commercial
PLCC44
Stick
89C51RB2-CM
AT89C51RB2-SLSIM
5V
Industrial
PLCC44
Stick
89C51RB2-IM
5V
Commercial
VQFP44
Tray
89C51RB2-CM
AT89C51RB2-RLTIM
5V
Industrial
VQFP44
Tray
89C51RB2-IM
AT89C51RB2-SLSIL
3V
Industrial
PLCC44
Stick
89C51RB2-IL
AT89C51RB2-RLTIL
3V
Industrial
VQFP44
Tray
89C51RB2-IL
AT89C51RC2-3CSCM
5V
Commercial
PDIL40
Stick
89C51RC2-CM
AT89C51RC2-3CSIM
5V
Industrial
PDIL40
Stick
89C51RC2-IM
AT89C51RC2-SLSCM
5V
Commercial
PLCC44
Stick
89C51RC2-CM
5V
Industrial
PLCC44
Stick
89C51RC2-IM
AT89C51RC2-RLTCM
5V
Commercial
VQFP44
Tray
89C51RC2-CM
AT89C51RC2-RLTIM
5V
Industrial
VQFP44
Tray
89C51RC2-IM
AT89C51RC2-SLSIL
3V
Industrial
PLCC44
Stick
89C51RC2-IL
AT89C51RC2-RLTIL
3V
Industrial
VQFP44
Tray
89C51RC2-IL
AT89C51RB2-3CSUM
5V
Industrial & Green
PDIL40
Stick
89C51RB2-UM
AT89C51RB2-SLSUM
5V
Industrial & Green
PLCC44
Stick
89C51RB2-UM
5V
Industrial & Green
VQFP44
Tray
89C51RB2-UM
AT89C51RB2-SLSUL
3V
Industrial & Green
PLCC44
Stick
89C51RB2-UL
AT89C51RB2-RLTUL
3V
Industrial & Green
VQFP44
Tray
89C51RB2-UL
AT89C51RB2-RLTUM
5V
Industrial & Green
VQFP44
Tray
89C51RB2-UM
AT89C51RC2-3CSUM
5V
Industrial & Green
PDIL40
Stick
89C51RC2-UM
AT89C51RC2-SLSUM
5V
Industrial & Green
PLCC44
Stick
89C51RC2-UM
5V
Industrial & Green
VQFP44
Tray
89C51RC2-UM
AT89C51RC2-SLSUL
3V
Industrial & Green
PLCC44
Stick
89C51RC2-UL
AT89C51RC2-RLTUL
3V
Industrial & Green
VQFP44
Tray
89C51RC2-UL
AT89C51RB2-RLTCM
Memory Size
16 KBytes
AT89C51RC2-SLSIM
32 KBytes
AT89C51RB2-RLTUM
16 KBytes
AT89C51RC2-RLTUM
32 KBytes
119
4180E805110/06
Package Information
PDIL40
120
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
VQFP44
121
4180E805110/06
PLC44
122
AT89C51RB2/RC2
4180E805110/06
AT89C51RB2/RC2
Datasheet Change
Log
Changes from 4180A08/02 to 4180B-04/03
1. Changed the endurance of Flash to 100, 000 Write/Erase cycles.
Changes from 4180B04/03 to 4180C-12/03
1. Max frequency update for 4.5 to 5.5V range up to 60 MHz (internal code
execution).
Changes from 4180C12/03 - 4180D - 06/05
1. Added Green product ordering information. Page 119.
Changes from 4180D 06/05 to 4180E - 10/06
1. Correction to PDIL40 figure on page 9.
2. Added note on Flash retention formula for VIH1, in Section DC Parameters for
Standard Voltage, page 107.
123
4180E805110/06
Table of Contents
Table of Contents
Features ................................................................................................. 1
Description ............................................................................................ 1
Block Diagram ....................................................................................... 3
SFR Mapping ......................................................................................... 4
Pin Configurations ................................................................................ 9
Port Types ........................................................................................... 13
Oscillator ............................................................................................. 14
Registers ............................................................................................................ 14
Functional Block Diagram .................................................................................. 15
Enhanced Features ............................................................................. 16

X2 Feature.......................................................................................................... 16
Dual Data Pointer Register (DPTR) ................................................... 20

Expanded RAM (XRAM) ...................................................................... 23
Registers ............................................................................................................ 25
Timer 2 ................................................................................................. 26
Auto-reload Mode ............................................................................................... 26
Programmable Clock-out Mode.......................................................................... 27
Registers ............................................................................................................ 29
Programmable Counter Array (PCA) ................................................. 31

Registers ............................................................................................................
PCA Capture Mode ............................................................................................
16-bit Software Timer/ Compare Mode ..............................................................
High-speed Output Mode ...................................................................................
Pulse Width Modulator Mode .............................................................................
PCA Watchdog Timer.........................................................................................
33
39
40
41
42
42
Serial I/O Port ...................................................................................... 44

Framing Error Detection ..................................................................................... 44
Automatic Address Recognition ......................................................................... 45
Registers............................................................................................................. 47
Baud Rate Selection for UART for Mode 1 and 3............................................... 47
UART Registers.................................................................................................. 50
Interrupt System ................................................................................. 55

Registers............................................................................................................. 56
Interrupt Sources and Vector Addresses............................................................ 63
Keyboard Interface ............................................................................. 64

Registers............................................................................................................. 65
Serial Port Interface (SPI) ................................................................... 68

Features.............................................................................................................. 68
Signal Description............................................................................................... 68
Functional Description ........................................................................................ 70
Hardware Watchdog Timer ................................................................ 77

Using the WDT ................................................................................................... 77
WDT During Power-down and Idle ..................................................................... 78
ONCE Mode (ON Chip Emulation) .................................................. 79

Power Management ............................................................................ 80
Reset ..................................................................................................................
Reset Recommendation to Prevent Flash Corruption ........................................
Idle Mode ............................................................................................................
Power-down Mode..............................................................................................
80
82
82
82
Power-off Flag ..................................................................................... 84

Reduced EMI Mode ............................................................................. 85
Flash EEPROM Memory ..................................................................... 86
Features.............................................................................................................. 86
Flash Programming and Erasure ........................................................................ 86
Flash Registers and Memory Map...................................................................... 87
Flash Memory Status.......................................................................................... 90
Memory Organization ......................................................................................... 90
Bootloader Architecture ...................................................................................... 91
ISP Protocol Description..................................................................................... 95
Functional Description ........................................................................................ 96
Flow Description ................................................................................................. 97
API Call Description.......................................................................................... 105
Electrical Characteristics ................................................................. 107

Absolute Maximum Ratings .............................................................................. 107
ii
xxxxA805110/06
DC Parameters for Standard Voltage ............................................................... 107

DC Parameters for Low Voltage ....................................................................... 109
AC Parameters ................................................................................................. 111
Ordering Information ........................................................................ 119

Package Information ........................................................................ 120
PDIL40.............................................................................................................. 120
VQFP44 ............................................................................................................ 121
PLC44............................................................................................................... 122
Datasheet Change Log ..................................................................... 123

Changes from 4180A-08/02 to 4180B-04/03 ....................................................
Changes from 4180B-04/03 to 4180C-12/03....................................................
Changes from 4180C-12/03 - 4180D - 06/05 ...................................................
Changes from 4180D - 06/05 to 4180E - 10/06................................................
123
123
123
123
Table of Contents .................................................................................. i
iii
xxxxA805110/06
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Features

8051 Pin and Instruction Compatible

Figure 1. Block Diagram

Parallel I/O Ports & Ext. Bus

(1) (1) (1) (1)

Port 0 Port 1 Port 2 Port 3

1. Alternate function of Port 1.

C51 core registers: ACC, B, DPH, DPL, PSW, SP

I/O port registers: P0, P1, P2, P3

Serial I/O port registers: SADDR, SADEN, SBUF, SCON

Power and clock control registers: PCON

Hardware Watchdog Timer registers: WDTRST, WDTPRG

Interrupt system registers: IEN0, IPL0, IPH0, IEN1, IPL1, IPH1

Keyboard Interface registers: KBE, KBF, KBLS

SPI registers: SPCON, SPSTR, SPDAT

BRG (Baud Rate Generator) registers: BRL, BDRCON

Flash register: FCON

Clock Prescaler register: CKRL

Others: AUXR, AUXR1, CKCON0, CKCON1

Table 2. C51 Core SFRs

Program Status Word

Data Pointer Low Byte

Data Pointer High Byte

Table 3. System Management SFRs

Clock Reload Register

Clock Control Register 0

Clock Control Register 1

Table 4. Interrupt SFRs

Interrupt Enable Control 0

Interrupt Enable Control 1

Interrupt Priority Control High 0

Interrupt Priority Control Low 0

Interrupt Priority Control High 1

Interrupt Priority Control Low 1

Table 5. Port SFRs

Table 6. Timer SFRs

Timer/Counter 0 and 1 Control

Timer/Counter 0 and 1 Modes

Timer/Counter 0 Low Byte

Timer/Counter 0 High Byte

Timer/Counter 1 Low Byte

Timer/Counter 1 High Byte

Watchdog Timer Reset

Watchdog Timer Program

Timer/Counter 2 High Byte

Timer/Counter 2 Low Byte

Table 7. PCA SFRs

PCA Timer/Counter Control

PCA Timer/Counter Mode

PCA Timer/Counter Low Byte

PCA Timer/Counter High Byte

CCAPM0 DAh PCA Timer/Counter Mode 0

CCAPM1 DBh PCA Timer/Counter Mode 1

CCAPM3 DDh PCA Timer/Counter Mode 3

CCAPM4 DEh PCA Timer/Counter Mode 4

CCAPM2 DCh PCA Timer/Counter Mode 2

EAh PCA Compare Capture Module 0 L CCAP0L7 CCAP0L6

CCAP0L4 CCAP0L3 CCAP0L2 CCAP0L1

EBh PCA Compare Capture Module 1 L CCAP1L7 CCAP1L6