A New Hybrid Cascaded H-Bridge Multilevel Inverter - Performance Analysis

IEEE- International Conference On Advances In Engineering, Science And Management (lCAESM -2012) March 30, 31, 2012
A New Hybrid Cascaded H-Bridge Multilevel

Inverter - Performance Analysis
ISujitha.N and 2Ramani.K
l.P.G. Scholar, 2. Faculty of Electrical and Electronics Engineering,
K.S.Rangasamy College of Technology, Thiruchengode-637215.
Email ID: sujitha.natarajan@gmail.com
Abstract-Cascaded
H-Bridge
multilevel
inverters
synthesize a medium voltage output based on a series

connection of power cells which use standard low
voltage component configurations. This characteristic
allows one to achieve high-quality output voltages and
input currents and also outstanding availability due to
their intrinsic component redundancy. Due to these
features,
the cascaded multilevel inverter has been
recognized as an important alternative in the medium

voltage inverter market. This paper presents a cascaded
H-bridge multilevel boost inverter for electric vehicle
(EV) and hybrid EV (HEV) applications implemented
without the use of inductors. Traditionally, each H
bridge needs a dc power supply. The proposed design
uses a standard three-leg inverter (one leg for each
phase) and an H-bridge in series with each inverter leg
which uses a capacitor as the dc power source. The
Hybrid
Cascaded
H-Bridge
Multilevel
inverter
is
implemented using the Selective Harmonic Elimination

PWM (SHEPWM) technique. The proposed topology
offers an intuitive method for minimizing the total
harmonic distortion (THD) of the output voltage of the
inverter which has been verified using the MATLAB
simulation. A fundamental switching scheme is used to
do modulation control and to produce a five-level phase
voltage.
Keywords:
inverter,
Selective
Cascaded
AC
Drive,
Harmonic
Hybrid
Total
H-bridge
Harmonic
Elimination
multilevel
Distortion,
pulse
width
Modulation (SHEPWM).
I. INTRODUCTION
Numerous industrial applications have begun to
require higher power apparatus in recent years. Some
medium voltage motor drives and utility applications
require medium voltage and megawatt power level.
For a medium voltage grid, it is troublesome to
connect only one power semiconductor switch
directly. The application of ac variable frequency
speed regulations are widely popularised, high power
and medium voltage inverter has known there are
many problems in conventional two level inverter in
the high power recently become a research focus so
far as application[3]. Multilevel voltage-source
inverters provide a cost effective solution in the
medium-voltage energy management market. These

converters have been widely applied to chemical, oil,
and Liquefied Natural Gas (LNG) plants, water
plants, marine propulsion, power generation, energy
transmIssIOn, and power quality devices [4].
Nowadays, there exist three commercial topologies of
multilevel voltage source inverters: Neutral Point
Clamped (NPC) [5], Cascaded H-Bridge (CHB) [4],
and Flying Capacitors (FCs) [6]. Among these
inverter topologies, Cascaded Multilevel Inverter
reaches the higher output voltage and power levels
(13.8 kV, 30 MVA) and the higher reliability due to
its modular topology. Cascaded H-Bridge multilevel
inverters are based on a series connection of several
single-phase inverters. This structure is capable of
reaching medium output voltage levels using only
standard low-voltage mature technology components.
Typically, it is necessary to connect three to ten H
Bridge inverters in series to reach the required output
voltage. These converters also feature a high
modularity degree because each inverter can be seen
as a module with similar circuit topology, control
structure, and modulation [7].
Both REVs and EVs need a traction motor and a
power inverter to drive the traction motor. The
requirements for the power inverter include high peak
power and low continuous power rating. Currently
available power inverter systems for REVs use a dc
dc boost converter to boost the battery voltage for a
traditional three-phase inverter. The dc-dc boost
converter is not required when the motor is running at
low to medium power, and the battery voltage will be
directly applied to the inverter to drive the traction
motor. the motor is running in a high power mode,
The dc-dc boost converter will boost the battery
voltage to a higher voltage when the motor is running
in a high power mode, so that the inverter can
provide higher power to the motor.
A cascaded H-bridge multilevel inverter for EV
and HEV applications is described in this paper.
Traditionally, each H-bridge of a cascaded multilevel
inverter needs a dc power supply. The proposed
cascaded H-bridge multilevel boost inverter uses a
standard three-leg inverter (one leg for each phase)
ISBN: 978-81-909042-2-3 2012 IEEE
46
47
and an H-bridge in series with each inverter leg

which uses a capacitor as the dc power source [12]
[15]. In this topology, the need for large inductor is
eliminated. A fundamental switching scheme is used
to do modulation control and to output five-level
phase voltages.
This scheme does not require any modification
in the carrier or modulating signal. It has advantage
or superiority over other previous works. The
modeling of in this paper highlights the significance
of Five- level Hybrid Cascaded H-Bridge multilevel
inverter.
Output V H.1g<!
de21L---S_S
II. TOPOLOGIES OF MULTILEVEL INVERTER

A basic structure of a cascaded multilevel
inverter is shown in Fig. 1. Each inverter uses a dc
link voltage to generate a modulated voltage at the
output terminals. The total output voltage is obtained
by the sum of each individual output voltage. Each
inverter is able to produce three output voltage levels,
such as, +Vdc, -Vdc, and O. The maximum number of
voltage levels of the phase voltage Lph is given by
Lph = 2Ninv + 1
(1)
where Ninv is the number of inverters.
Fig. 2. Topology of the Single Phase Conventional Cascaded H

Bridge Multilevel Inverter
Each inverter requires an isolated dc voltage

which is usually obtained by an arrangement of three
phase or single-phase rectifiers [8], and a multipulse
transformer which provides the electrical isolation. In
some applications, these dc voltages can be obtained
directly by isolated dc sources, for example,
photovoltaic panels [10] or dc/dc isolated converters
[11]. In another application, like STATCOM, which
does not require the injection of active power, the dc
voltages can be floating, and the control strategy
keeps the dc-link voltage adjusted to the reference.
The topology of the proposed dc-ac Hybrid
cascaded H-bridge multilevel inverter is shown in
Fig. 3. The inverter uses a standard three-leg inverter,
one leg for each phase and an H-bridge with a
capacitor as its dc source in series with each phase
leg.
---'-_
----'
l:1
\dca2
)1 + Vdcb.:l.
/ + V&t1."'
ill
Va2
T . I "I
Vb2
To, I I
n
Fig. 1. Topology of the Three Phase conventional Cascaded H
bridge multilevel Inverter.
Fig.3. Topology of the proposed dc-ac Hybrid cascaded H-bridge

multilevel inverter.
ISBN: 978-81-909042-2-3 2012 IEEE
48
voltage, so that during periods of zero voltage output,

either the switches SI, S4, and S6 are closed or the
switches S2, S3, and Ss are closed, depending on
whether it is necessary to charge or discharge the
capacitor. It is this flexibility in choosing how to
make that output voltage zero that is exploited to
regulate the capacitor voltage.
The goal of using fundamental frequency
switching modulation control is to output a five-level
voltage waveform, with a sinusoidal load current
waveform, as shown in Fig. 5(a). If the capacitor's
voltage is higher than Vde/2, switches Ss and S6 are
controlled to output voltage waveform VI, and the
switches SI, S2, S3, and S4 are controlled to output
voltage waveform V2, shown in Fig. 5(b). The
highlighted part of the waveform in Fig. 5(b) is the
capacitor discharging period, during which the
inverter's output voltage is 0 V.
Fig. 4. Single phase of the proposed dc-ac Hybrid cascaded H

bridge multilevel inverter.
Output Voltage
- -V=Vl+V2
A simplified single phase Hybrid cascaded H

Bridge multilevel inverter topology is shown in Fig.4.
The output voltage VI of this leg of the bottom
inverter (with respect to the ground) is either + Vdel2
(Ss closed) or -Vdel2 (S6 closed). This leg is
connected in series with a full H-bridge, which, in
turn, is supplied by a capacitor voltage. If the
capacitor is kept charged to Vde/2, then the output
voltage of the H-bridge can take on the values +Vde/2
(SI and S4 closed), 0 (SI and S2 closed or S3 and S4
closed), or -Vdel2 (S2 and S3 closed).
An example output waveform from this topology
is shown in Fig.5(a). When the output voltage V =VI
+ V2 is required to be zero, one can either set VI =
+Vdel2 and V2 = -Vdel2 or VI = -Vdel2 and V2 =
+Vde/2. Additional capacitor's voltage regulation
control detail is shown in Fig. 3. To explain how the
capacitor is kept charged, consider the interval 91 :S 9
:S n, the output voltage in Fig. 5(a) is zero, and the
current i > O. If SI and S4 are closed, so that V2 =
+Vde/2 and S6 is closed (so that VI = -Vde/2), then the
capacitor is discharging ie = -i < 0; see Fig. 5(b), and
V = VI + V2 = O. On the other hand, if S2 and S3 are
closed, so that V2 = -Vdel2 and Ss is also closed (so
that VI = +Vdel2), then the capacitor is charging ie = i
> 0; which is mentioned in Fig. 5(c), and V = VI + V2
= O. The case i < 0 is accomplished by simply
reversing the switch positions of the i > 0 case for
charging and discharging of the capacitor.
Consequently,
the
method
consists
of
monitoring the output current and the capacitor
ISBN: 978-81-909042-2-3 2012 IEEE
II/
(a)
49
V2
r--
r---
---;;
2fT
9,
Vl
-
,------
2fT
9,
Fig. 5(c). The highlighted part of the waveform in

Fig. 5(c) is the capacitor charging period, when the
inverter's output voltage is 0 V. Therefore, the
capacitors' voltage can be regulated by alternating
the capacitor's charging and discharging control,
when the inverter output is 0 V.
This method of regulating the capacitor voltage
depends on the voltage and current not being in
phase. That is, one needs positive (or negative)
current when the voltage is passing through zero in
order to charge or discharge the capacitor.
Consequently, the amount of capacitor voltage the
scheme can regulate depends on the phase angle
difference of output voltage and current. In other
words, the highest output ac voltage of the inverter
depends on the displacement power factor of the
load.
TABLE I: SWlTCHING SEQUENCE OF CONVENTlONAL
METHOD
......
Interval
(b)
Vz
fT
9,
......
1fT
'---
ON Switches in
U-Bridge 1
ON Switches in UBridge 2
IT
S"S2
S5,S,
TIT
S"S2
S5,S6
IV
S"S2
S"S,
VI
S3,S.
S6,SS
VII
S3,S.
S"Ss
VIII
S3,S.
S6,SS
-
IX
V1
TABLE 2: SWlTCHING SEQUENCE OF PROPOSED

METHOD
Vdcl2 t--------..,
2fT
9,
ON Switches in HBridge
Interval
fT
(c)
Fig.5. Capacitor voltage regulation with capacitor charging and

discharging. (a) Overall output voltage and load current. (b)
Capacitor discharging.
(c) Capacitor charging.
The capacitor's voltage is lower than Vdc/2, the

switches S5 and S6 are controlled to output voltage
waveform VI, and switches SI, S2, S3, and S4 are
controlled to output voltage waveform V2, shown in
ON switch in three
phase full converter
11
S"S2
S,
TIT
S"S4
S5
IV
S"S2
S5
VI
S"S2
S6
V11
S2,S3
S6
VIII
S"S2
IX
S6
-
III. SIMULAnON RESULTS
ISBN: 978-81-909042-2-3 2012 IEEE
The simulation result comprises of proposed

hybrid cascaded H-Bridge multilevel inverter and its
corresponding voltage waveform. The proposed
inverter is fed to a three phase induction motor and
its characteristics namely speed, torque is noted
down. The three phase voltage waveform with 120
degree phase shift for the five level hybrid cascaded
H-Bridge multilevel inverter is shown in Fig 7. The
speed characteristic is shown in Fig 8. The rated
speed for induction motor is 1430 rpm. Here the
speed curve shows that the motor attains its rated
speed after 4ms. The Torque characteristic is shown
in Fig 9. Initially high torque is attained and latter
settles to a constant value. The speed torque
characteristic is shown in Fig 10. As the speed
increases the torque settles to a constant value. In Fig
11, 12 the torque and speed curves for different
loading conditions are shown.
Q:[
Fig 6. Proposed Simulation Circuit
15 ..----.---r--r----.__-___._-____r
10
5
10
15 '-----'----'---L---'
o
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.(
TIme(ms)
Fig.7.0utput voltage waveform of a hybrid cascaded H-bridge
multilevel inverter
ISBN: 978-81-909042-2-3 2012 IEEE
50

A New Hybrid Cascaded H-Bridge Multilevel Inverter - Performance Analysis

Uploaded by

Copyright:

Available Formats

A New Hybrid Cascaded H-Bridge Multilevel Inverter - Performance Analysis

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

A New Hybrid Cascaded H-Bridge Multilevel Inverter - Performance Analysis

Uploaded by

Copyright:

Available Formats

IEEE- International Conference On Advances In Engineering, Science And Management (lCAESM -2012) March 30, 31, 2012

A New Hybrid Cascaded H-Bridge Multilevel

synthesize a medium voltage output based on a series

the cascaded multilevel inverter has been

recognized as an important alternative in the medium

implemented using the Selective Harmonic Elimination

medium-voltage energy management market. These

ISBN: 978-81-909042-2-3 2012 IEEE

and an H-bridge in series with each inverter leg

II. TOPOLOGIES OF MULTILEVEL INVERTER

Fig. 2. Topology of the Single Phase Conventional Cascaded H

Each inverter requires an isolated dc voltage

Fig.3. Topology of the proposed dc-ac Hybrid cascaded H-bridge

ISBN: 978-81-909042-2-3 2012 IEEE

voltage, so that during periods of zero voltage output,

Fig. 4. Single phase of the proposed dc-ac Hybrid cascaded H

A simplified single phase Hybrid cascaded H

Fig. 5(c). The highlighted part of the waveform in

TABLE 2: SWlTCHING SEQUENCE OF PROPOSED

Fig.5. Capacitor voltage regulation with capacitor charging and

The capacitor's voltage is lower than Vdc/2, the

III. SIMULAnON RESULTS

ISBN: 978-81-909042-2-3 2012 IEEE

The simulation result comprises of proposed

Fig 6. Proposed Simulation Circuit

ISBN: 978-81-909042-2-3 2012 IEEE

You might also like