Front Cover - Mtech Lab FINAL - MANUALSOFT

School of Electrical Engineering
Lab Record
DSP BASED CONTROL OF

ELECTRICAL MACHINES AND DRIVES
LAB
Course: M.Tech - PED - II semester
Session: Winter 2011-12
Name:
Reg. No:
VIT - A PLACE TO LEARN; A CHANCE TO GROW
SCHOOL OF ELECTRICAL ENGINEERING

Bonafide Certificate
Subject
Subject code
Reg. No.
Certified that this is a bonafide record of work done by

___________________________________ of _______________ Semester
M.Tech PED during the Year _______________.
Submitted
for
the
Practical
Examination
held
on
_______________________ at Vellore Institute of Technology University,

Vellore 14.
Date:
Staff In-charge
Internal Examiner
Ex.
No
Date
External Examiner
Title of the Experiment
Page
No
Signature
Addition Using Immediate, Direct and Indirect

Addressing Modes
2
3
4
5
Storing and Moving of a Block of Data

Complement the Data
Multiplication of Two Numbers
Delay Routine
Generation of Pulses Using GPIO
Generation of Sine Wave

PWM Waveform Generation Using Timer Compare
Module
Generation of PWM Pulses using Full Compare Unit
Acquisition of signal from ADC
8
9
10
11
Generation of PWM Pulses Using GP Timers for

Chopper
12
13
14
PWM Pulse Generation for Single Phase Inverter

Generation of Six Pulses With and Without Deadband
Generation of PWM pulses with F28335eZ DSP
PROGRAM STARTUP
Create and Configure Project:
A project stores all the information needed to build an individual program or library.
Filenames of source code and object libraries

Code generation tool options
Include file dependencies
Launching Code Composer Studio:

To launch Code Composer Studio IDE for the first time, click the icon (shown in next topic) on your
desktop. A simulator is automatically configured by default. The configured simulator in our lab is F2407
CC Studio_3.1 as the shortcut in desktop.
Important Icons Used in Code Composer Studio v3.1:

This list of icons is important in helping you to traverse through the Code Composer Studio IDE. These
icons will be referred to throughout this manual.
Used to launch Code Composer Studio

Rebuilds the project
Builds the project incrementally
Halts execution
Toggle breakpoint toolbar button
Run toolbar button
Step into button
Step out of button

Step over button
Creating a Project:
The following procedure allows you to create single or multiple new projects (multiple projects can be open
simultaneously). Each projects filename must be unique.
The information for a project is stored in a single project file (*.pjt).
Step 1: In lab it is installed Code Composer Studio in C:\CCStudio_3.1, create a folder called (project
name) in the C:\CCStudio_3.1\myprojects folder.
Step 2: From the Project menu, choose New. The Project Creation wizard window displays.
Step 3: In the Project Name field, type the name you want for your project.
Step 4: In the Location field, specify the directory where you want to store the project file, Object files
generated by the compiler and assembler are also stored here. You can type the full path in the location field
or click the browse
button and use the choose directory dialog box.
Step 5: In the Project Type field, select a Project Type from the drop-down list. Choose either Executable
(.out) or Library (lib). Executable indicates that the project generates an executable file. Library indicates
that you are building an object library.
Step 6: In the Target field, select the target family that identifies your CPU. This information is necessary
when tools are installed for multiple targets.
Step 7: Click Finish.
A project file called projectname.pjt is created. This file stores all files and project settings used by your
project.
Adding Files to a Project:

You can add several different files or file types to your project. The types are shown in the figure below. To
add files to your project:
Step 1: Select Project Add Files to Project, or right-click on the projects filename in the Project View
window and select Add Files.
Step 2: In the Add Files to Project dialog box, specify a file to add. If the file does not exist in the current
directory, browse to the correct location. Use the Files of Type drop-down list to set the type of files that
appear in the File name field.
Step 3: Click Open to add the specified file to your project. Paths followed for adding files are:
C:\CCStudio_3.1\C2400\cgtools\lib\ directory and add the rts2xx.lib file
C:\CCStudio_3.1\tutorial\dsk2407\volume1\ directory and add load.asm, vectors.asm, volume.cmd

files
Step4: Also create a new file for the program and save as the program name.asm or .c depending on the
program and add it in the project.
Step 5: Add F2407.h file from the desktop to the folder project name created in step 1 of project creation.
Thus the project is now ready for programming and it can be interfaced with the kit by JTAG and .out file is
loaded with this CC Studio and output can be seen through ports of the kit.
ADDITION USING IMMEDIATE, DIRECT AND INDIRECT

ADDRESSING MODES
Exp. No: 1 (a)
Date:
Objective:
To write a program to add numbers using immediate addressing mode
without shift.
Equipments required:
Hardware:
PC
TMS320LF2407A
Power supply adaptor cable
DB25 connector printer cable
Software:
Code composer studio 3.1.
Windows 95/98/NT/XP.
Program:
.def_c_int0
.include f2407.h
.text
_c_int0
LACC #0FDDFh
ADD #0DA0Fh
END B END
;Load the accumulator with data FDDFh

;Add data 0DA0FH with content of the
accumulator
; End of the program
Results:
ACC
CARRY FLAG
Value before execution

0FDDFH
0
Value after execution

0D7EEH
1
Exp. No: 1(b)

Date:
Objective:
To write a program to add numbers using direct addressing mode without
shift .
Hardware:
PC.
TMS320LF2407A.
Power supply adaptor cable.
DB25 connector printer cable.
Software:
Program:
.def_c_int0
.include f2407.h
.text
_c_int0
LDP #100h
SPLK #0003h, 0h
LACC #0F006h
ADD 0h
END B END
; set data page as 100h

; store 0003h in 8000h memory location
; load accumulator with data 0F006h
; add data in memory location 8000h to accumulator
; end of the program
Results:
ACC
0F006H
LOCATION 8000h
0003H
CARRY FLAG
0

0F009H
0003H
0
Exp. No: 1(c)

Date:
Objective:
To write a program to add numbers using indirect addressing mode using *+
operand without shift.
Equipments Required:
Hardware:
PC
TMS320LF2407A.
SOFTWARE:
code composer studio 3.1
windows 95/98/NT/XP.
Program:
.def_c_int0
.include f2407.h
.text
_c_int0
LDP #100h
SPLK #0FDDFh, 10h

; load 8010h memory location with data
0FDDFh
LACC #0DA0Fh
; load accumulator with data 0DA0Fh
LAR AR1, #8010h
; load auxiliary register AR1 with data

8010h
: make AR! As current auxiliary register
;add to accumulator with the contents of data
memory address specified by current
AR(AR1)
1
MAR *, AR1
ADD *+
END B END
Results:
ACC
Carry flag
AR1

0DA0Fh
0
8010h

0D7EEh
1
8011h
Exp. No: 1(d)

Date:
Objective:
To write a program to add numbers using indirect addressing mode using *0+
operand without shift .
Equipment required:
Hardware:
PC
TMS320LF2407A.
Software:
Code composer studio 3.1
Program:
.def_c_int0
.include f2407.h
.text
_c_int0
LDP #100h
SPLK #0FDDFh,10h
LACC #0DA0Fh
LARP 01
LAR AR0, #0003h
LAR AR1, #8010h
ADD *0+

; load 8010h memory with data 0FDDFh
;load accumulator with data 0DA0Fh
;current auxiliary register as 01
; load AR0 with data 0003h
; load AR1 with data 8010h
; add to accumulator with the contents
of data memory address specified
by current AR(AR1)
END B END
Results:
ACC

0DA0Fh

0D7EEh
Carry flag
AR0
AR1
Exp. No: 1(e)

Date:
0
0003h
8010h
1
0003h
8013h
Objective:
To write a program to add numbers using indirect addressing modes using *0+
operand and pointing next auxiliary register along with shift.
Hardware:
PC
TMS320LF2407A
Software:
code composer studio 3.1
windows 95/98/NT/XP.
Program:
.def_c_int0
.include f2407.h
.text
_c_int0
LDP #100h
SPLK #0FDDFh, 8010h
LACC #0DA0Fh
LARP 01
LAR AR0, #0003h
LAR AR1, #8010h
ADD *0+, 8, AR4
; Set data page as 100h

; Load 8010h memory location with
data #0FDDFh
; Load accumulator with data
0DA0Fh
; Current auxiliary register as 01
; Load auxiliary register AR0 with
Data 0003h
; Load auxiliary register AR1 with
8010h
; Add to accumulator with the
contents of data memory address
specified by current AR (AR1).
The data is left Shifted by 8bits
before being added and AR4 is
chosen as Next auxiliary register.
END B END
Results:
ACC

0DA0Fh

0B90Fh
Carry flag
AR0
AR1
ARP
0
0003h
8010h
01
1
0003h
8013h
04
Storing and Moving of a Block of Data

Exp No: 2
Date:
Objective:
To write a program to store 0-127 in 300h-37Fh and move block of data from
300h-37Fh to 380h-3FFh.
Hardware:
PC
TMS320LF2407A
Power supply adapter cable
Software:
Windows 95/98/NT/XP
Code Composer 3.1
Flow chart:
Start
Load count value in AR0 and load AR1 and AR2 values
Make AR1 as current auxiliary register Load the accumulator value in mem. Address pointed by AR1
Add 1 to acc. And decrement count by 1
Count=0
BB
Load the content of AR1 in accumulator,

increment AR1 by 1 and make AR2 as current
auxiliary register
Load accumulator with data in the memory location

pointed by AR2, increment AR2 and make AR0 as
current auxiliary register
Count=0
No
Yes
Program:
END
.def _c_int0
.include f2407.h
.text
_c_int0
LAR AR0, #127
LAR AR1, #300H
LAR AR2, #380h
LACL #00h
Loop: MAR *, AR1
SACL *+, 0, AR0
ADD #1
BANZ Loop
LAR AR0, #127
`
LAR AR1,#300H
LOOP2 :LACL #0
MAR *, AR1
LACL *+, 0, AR2
SACL *+, AR0
BANZ LOOP2
END B END
; Load count value

; Load AR1 with 300h
; Accumulator is loaded with 0
; Make AR1 as current auxiliary register
; Load accumulator lower to the memory address
pointed by AR1, increment AR1 and make AR0 as
current auxiliary register
;Add 1 to the accumulator content
; Branch to loop, decrement count by 1 and end the loop
When Count is 0.
; load the accumulator with 0
; make AR1 as current auxiliary register
; load the content of the memory address pointed by AR1
to Accumulator increment AR1 by 1 and make AR2 as
current Auxiliary register.
; load the content of acc to the memory address pointed
byAR2 and increment AR2 by 1 and make AR0 as
current Auxiliary register
; decrement AR0 by 1 if it is not zero branch to Loop2
Result:
Acc
AR0
AR1
AR2

327Ah
127
300h
380h
Complement the Data

127
0
37Fh
3FFh
Exp No: 3
Date:
Objective:
To write a program to complement the data in memory location 380h-3FFh.
Hardware:
PC
TMS320LF2407A
Software:
Windows 95/98/NT/XP
Code Composer 3.1
Flow chart:
Start
Load Data Page with 7
Load Count Value as 127 and Store 380h value in AR1
Load AR1 register value in LACL and increment AR1 value by 1
Complement the data and store it and decrease count by 1
Count=0
no
yes
END
Program:
.def _c_int0
.include f2407.h
.text
_c_int0
LDP #7
LAR AR0, #127
LAR AR1, #380H
Loop: LACL #00h
MAR *, AR1
LACL *, 0, AR1
CMPL
SACL *+, AR0
BANZ Loop
; Load count value

; Accumulator is loaded with 0
; Make accumulator as current auxiliary register
; Load accumulator lower with AR1 value
; Complement accumulator lower
; Load Store the accumulator lower in AR1 and
increment AR1 By 1 and make AR0 as current auxiliary
register
: decrement count by 1 and if it is not zero then
Branch to loop, else end the loop
END B END
Result:
AR0
AR1
ACC

127
380h
0000h

0
3FFh
FFFF8E80
Multiplication Of Two Numbers

Exp. No: 4
Date:
Objective:
To write a program to multiply two numbers using auxiliary registers as pointer to
different memory address.
Hardware:
PC
TMS320LF2407A
Software:
Algorithm:
1. start
2. Load AR0 with the memory address which contains the data to be multiplied.
3. Load AR1 with the memory address which contains the data to be multiplied.
4. Store the data at location pointed by AR0 into TREG register.
5. Multiply the data
6. Store the data in the accumulator
7. Move the data from accumulator to the required memory location
Program:
.def _c_int0
.include f2407.h
.text
_c_int0
LAR AR0, #200h
MAR *, AR1
LAR AR1, #270h
LTA *, AR0
MPY *, AR3
PAC
LAR AR3, #300h
; Load auxiliary register AR0 with memory

address 200h
; Make AR1 as current auxiliary register
Address 270h
; store the data at location pointed by AR0
into TREG register
; Multiply data at the memory location
pointed by Current auxiliary register With
the content of TREG register.
; Load PREG data in accumulator
SACL *+, AR3

SACH *, AR3
; Store accumulator lower byte at memory

address pointed by AR3 and increment
AR3
; Store accumulator higher byte at memory
address Pointed by AR3.
Results:
ACC
200h
270h
PREG
300h
301h

0FDDFH
10H
2H
032F7H
0C2DBH
0C2DAH
Delay Routine
Exp. No.: 5
Date:
Objective:

0020H
10H
2H
20H
0020H
FFFFH
To write a program to generate a delay routine using RPT instruction.

Hardware:
PC
TMS320LF2407A
Software:
Windows 95/98/NT/XP
Code Composer studio 3.1
Registers Involved:
SCSR1: System control and status register
Algorithm:
1. Start.
2. Configure SCSR1 for required clk prescalar.
3. Call delay.
4. Load the auxiliary register with hex value of required delay.
5. Repeat the delay loop until count becomes zero.
Delay Calculation:
Calculation of delay for 1sec.
With Fclk=10 Mhz and prescalar Fclk*1
Instruction
MAR *
LAR *, _
Machine cycles
1
2
RPT #
NOP
BANZ
4 when true
2 when false
Delay required (sec) = ((Total machine cycles)*(time taken to execute 1

machine cycle))
1sec = [1+2+x (1+500+4)+2]
X = 19801
X = 4D59. Value must be loaded into ARx
Program:-
with
LDP #224
SPLK #0601h, SCSR1
F
Fclk*1 prescalar.
DELAY: MAR *, AR0
LAR AR0, #4D59h
LOOP:
RPT #499
NOP
BANZ LOOP
: Load 224 data page

: Configure SCSR1
: Delay Routine
Result:
Delay is generated using RPT instruction.
Generation of Pulses Using GPIO

Exp. No.: 6
Date:
Objective:
To write a program to generate the pulses on port A using general purpose I/O.
Hardware:
PC
TMS320LF2407A
Software:
Windows 95/98/NT/XP
Registers Involved:
SCSR1: System control and status register
MCRA: Mux Control register A
PADATDIR: PortA data and direction control register
Algorithm:
1. Start
2. Configure SCSR1 for required clk prescalar.
3. Configure MCRA for secondary function of the GPIO pins.
4. Configure PADATDIR in order to make the I/O pins as output pins.
5. Send High Signal on port A
6. Call Delay
7. Send Low signal on port A
8. Call delay
9. Go to step 5
Flow chart:
Start
Set data page 225 and configure

MCRA for secondary function
Send
Send
Configure
High
low signal
PADARDIR
on the port
forA
Wait
Wait
for
forport
11sec
sec
output
Set data page 224 and configure

SCSR1 with require prescalar
Delay Calculation:
Calculation of delay for 1sec.
With Fclk=10 Mhz and prescalar Fclk*1
Instruction
MAR *
LAR *, _
Machine cycles
1
2
RPT #
NOP
BANZ
4 when true
2 when false
Delay required (sec) = ((Total machine cycles)*(time taken to execute 1 machine cycle))
1sec= [1+2+x (1+500+4)+2]
X=19801
X=4D59. Value must be loaded into ARx
Program:.def _c_int0
.include f2407.h
.text
_c_int0
LACC #0h
LDP #224
SPLK #0601h, SCSR1
LDP #225
SPLK #0FF00h, MCRA
LOOP: SPLK #0FF0Fh, PADATDIR
B DELAY
SPLK #0FF00h, PADATDIR
B DELAY
B LOOP
DELAY: MAR *, AR0
LAR AR0, #4D59h
LOOP1: RPT #499
N OP
BANZ LOOP1
Connection Diagram:
Result:

: Configure SCSR1 with F
Fclk*1 prescalar
: Configure port A for
secondary function
: Configure port A as an output
And send High signal on LSB
: Call Delay
: Send low signal on LSB
: Call Delay
: Delay Routine
Pulses are generated on Port A by configuring it as an output port.
GENERARION OF SINE WAVE

EXP.NO: 7
DATE:
Objective:
To write a program to generate Sine Wave of frequency 500Hz using General
Purpose Timer.
Hardware:
PC
TMS320LF2407A
Software:
Windows 95/98/NT/XP
Algorithm:
Step1: Start.
Step2: Initialize General Purpose Timer 1..
Step3: Initialize variables and hardware.
Step4: Turn on timer 1.
Step5: Enable Timer 1 interrupt flag.
Step6: Reset timer 1 interrupt flag.
Step7: Set duty cycle to table value
Step8: Set End of sine wave.
Step9: End
Registers Involved:
T1PR=921
T1PR register is to be loaded as followsPeriod Value = CPUCLK/PRESCALER/DESIRED FREQ = 14*10^6/1/500=28000
CPUCLK=14MHz
PRESCALER=1. This is set by bits 10-8 of T1CON
CMPR1= 460
For 50% duty cycle CMPR1 value will be half of T1PR
GPTCONA = 0x0042
Enable all GP Timer Compare outputs and polarity of GP Timer1 and GP Timer2
compare outputs to active High
T1CON=0x9142
Select Continuous Up counting mode ,set input prescaler to 1,select internal clock, enable
timer operation and program the counter to stop immediately on emulation suspend.
MCRA = T1PWM
Configure all the pins to operate in primary function.
Program:
#include "system.h"
#include "eva.h"
#include "io2407.h"
unsigned int sine[32] = {460, 550, 637, 716, 786, 843, 886, 912,
921, 912, 886, 843, 786, 716, 637, 550, 460, 371,
284, 205, 135, 78, 35, 9, 0, 9, 35, 78, 135, 205, 284, 371 };
unsigned int cosine[32] = {921, 912, 886, 843, 786, 716, 637, 550,
460, 371, 284, 205, 135, 78, 35, 9,0, 9, 35, 78, 135,
205, 284, 371, 460, 550, 637, 716, 786, 843, 886, 912};
/* Initialise General Purpose Timer 1. */
void init_GPT1(void)
{
MCRA |= T1PWM; /* Turn on T1PWM */
T1CON = 0x8142; /* Turn off GPT1 */
GPTCONA |= 0x0042;
T1PR = 921; /* Period = 921 + 1 decimal. 16 kHz */
T1CMPR = 460; /* Duty = 50% */
T1CNT = 0xFFFE; /* Set to -2 */

T1CON = 0x9142; /* Start timer 1 */
}
/* Initialise General Purpose Timer 2 */
void init_GPT2(void)
{
MCRA |= T2PWM; /* Turn on T2PWM */
T2CON = 0x8142; /* Turn off GPT2 */
GPTCONA |= 0x0088; /* Controlled from GPT1 */
T2PR = 921; /* Period = 921 + 1 decimal. 16 kHz */
T2CMPR = 640; /* Duty cycle 50% decimal */
T2CNT = 0xFFFE; /* Set to -2 */
T2CON = 0x9142; /* Start timer 2 */
}
unsigned int x; /* General purpose variable */
void main(void)
{
init_system(); /* Initialize variables and hardware */
init_GPT1(); /* Turn on timer 1 */
init_GPT2(); /* Turn on timer 2 */
EVAIMRA |= T1PINT_FLAG; /* Enable Timer 1 interrupt flag */
x = 0;
for ( ; ; )
{
if ( EVAIFRA & T1PINT_FLAG)
{
EVAIFRA = T1PINT_FLAG; /* Reset timer 1 interrupt flag */
T1CMPR = sine[x]; /* Set duty cycle to table value */
T2CMPR = cosine[x];
if ( x < 31)
x++;
else
x = 0;
}
}
}
Connection Diagram:
To
pin12
Filter Circuit
Graphs:
To pin 17
T1PWM Waveform observed without connecting o/p filter
T1PWM Waveform observed with 1kHz lowpass filter
T2PWM Waveform observed with 1kHz lowpass filter

Result:
Sine wave of 50% duty cycle is generated using General Purpose Timer .
PWM WAVEFORM GENERATION USING TIMER COMPARE MODULE
Exp No: 8
Date:
Objective:
To generate asymmetric PWM pulses of 10kHz of 75% duty cycle under
continuous up count mode & active high condition.
Hardware:
PC
TMS320LF2407A
Software:
Windows 95/98/NT/XP
Code Composer 3.1
Solution:
SPLK #0000 0110 0000 1101b,SCSR1
bit 15
0:
reserved
bit 14
0:
CLKOUT=CPUCLK
bit 13-12
00: IDLE1 selected for low power mode
bit 11-9
011: PLL x1 mode
bit 8
0:
reserved
bit 7
0: disable ADC module clock
bit 6
0: disable SCI module clock
bit 5
0: disable SPI module clock
bit 4
0: disable CAN module clock
bit 3
1: enable EVB module clock
bit 2
1: enable EVA module clock
bit 1
0: reserved
bit 0
1: clear the ILLADR bit
SPLK #0000 0000 0100 0010b,GPTCONA
bit 15
0:
reserved
bit 14
0: T2STAT,read only
bit 13
0: T1STAT,read only
bit 12-11 00: reserved
bit 10-9
00: T2TOADC,00 = no timer2 event starts ADC
bit 8-7
00: T1TOADC,00 = no timer1 event starts ADC
bit 6
1: TCOMPOE,0 = Hi-Z all timers compare outputs
bit 5-4
bit 3-2
bit 1-0
00:
00:
10:
reserved
T2PIN,00 = forced low
T1PIN,10 = active high
SPLK #1001 0001 0100 0010b,T1CON

bit 15-14
10: operation is not affected by emulation suspend
bit 13
0: reserved
bit 12-11
10: continuous up count mode
bit 10-8
001: input clock prescaler,001= x/2
bit 7
0: use own TENABLE bit
bit 6
1: enable TIMER operation
bit 5-4
00: internal clk source select
bit 3-2
00: when counter is 0
bit 1
1: enable TIMER compare operation
bit 0
0: use own period register
Asymmetric PWM:
TxPR=
desired PWM period

104
1=
1=499 =(1F3h)
prescalad clk period
200109
T1CMPR = 499/3 = 166=(A6h) (75% DUTY CYCLE)
Flowchart:
Program:
.def_c_int0
.include f2407.h
.text
_c_int0
NOP
LDP #DP_PF1
SPLK #060CH,SCSR1
LDP #0E1H
SPLK #0FFFFH,MCRA
SPLK #0FFFFH,MCRC
LDP #0E8H
SPLK #0000H,T1CNT
SPLK #01F3H,T1PR
SPLK #00A6H,T1CMPR
EVA & EVB clock module enabled

Port A Configured for primary function
Port C Configured for primary function
Counter initialized
Setting the frequency required
75% duty cycle PWM
SPLK #0042H,GPTCONA
SPLK #9142H,T1CON
LOOP B LOOP
Active high mode

Continuous up count mode
Connection Pin Location:
Waveform :
Results:
Asymmetric PWM pulses of 10KHz of 75% duty cycle is obtained.
Inferences:
For getting 75% duty cycle PWM pulse with active high condition the compare register
should be loaded with one-fourth the period register value.
GENERATION OF PWM PULSES USING FULL COMPARE UNIT
Exp.No: 9
Date:
Objective:
To write a program to generate PWM pulses of frequency 1kHz using full compare units.
Hardware:
PC
TMS320LF2407A
Software:
Windows 95/98/NT/XP
Algorithm:
Step1: Start.
Step2: Configure SCSR1 register as required so as to enable clock for EVA module.
Step3: Configure pins to operate in primary function using MCRA instruction.
Step4: Initialize timer counter value to zero.
Step5: Set up and load ACTR
Step6: Set up and load DBTCON, if dead band is to be used.
Step7: Initialize CMPR1
Step8: Set up and load COMCON without enabling compare operation.
Step9: Set up and load COMCON to enable compare operation.
Step10: Set up and load T1CON to start the operation.
Step11: Rewrite CMPRx with newly determined values.
Step12: end
In the following program up counting mode of the timer 1 has been used.
Registers Involved:
CPUCLK=10MHz
PRESCALER=2. This is set by bits 10-8 of T1CON
T1PR=10000
T1PR register is to be loaded as follows-
TxPR=
desired PWM period

103
1=
1=4999 =(1387)h
9
20010
CMPR1= 2499=(09C3)h
For 50% duty cycle CMPR1 value will be half of T1PR
GPTCONA = 004Ah
T1CON=(9142)h
Select Continuous Up counting mode, set input pre-scalar to 1,select internal clock, enable
MCRA = 0FFFh

ACTRA = 0AAAh
Select action on all compare output pins to be active high.
COMCONA = 4A00h
Disabling Compare operation, reload compares register immediately & disable SVPWM mode
and reload action control register immediately, enable PWM output pins.
COMCONA = CA00h
Enabling Compare operation and all remaining bits remain same as configured as above.
Flowchart:
START
Start
Set Data page to DP_PF1
Set data page to DP_PF1 & enable clock to EVA module

Set data page to DP_PF2 & configure port pins to operate in primary function
Set data page to 0E8h & timer1 counter to 0000h

Configure GPTCONA register
Set T1PR register &
Set compare register unit for 50% duty cycle
Configure compare action control register ACTRA to 0AAAh
Configure Compare Control Register without enabling compare operation i.e, to 04A00h
Configure Compare Control Register with enabling compare operation i.e, to 0CA00h
Configure Timer Control Register

END
Program:
.def _c_int0
.include f2407.h
.text
_c_int0
NOP
LDP #DP_PF1
SPLK #0605H, SCSR1
LDP #DP_PF2
SPLK #0FFFFH, MCRA
LDP #0E8H
SPLK #0000H, T1CNT
SPLK #004AH, GPTCONA
SPLK #1387H, T1PR
SPLK #09C3H, CMPR1
SPLK #0AAAH, ACTRA
SPLK #4A00H, COMCONA
SPLK #0CA00H, COMCONA
SPLK #9142h, T1CON
END
; set data page

; Enabling clock to EVA module
; set data page
; configure pins to operate in
; primary function
; set data page
; set timer1 counter
; Configure GPtimer Control Register
; load timer1 period register with
desired value
; set compare value as required
; configure compare action control
register
; configure compare control register
without enabling compare operation
; configure register with enabling
compare register
;configure timer control register
as required
B END
To check the square wave output on the oscilloscope, the following connections should be made:
Each Compare Unit has two outputs namely PWM1 and PWM2.
If COMPARE unit 1 is used we check the output at pins 9 and 19 (ground) for PWM1 signal and
for another signal namely PWM2 pins 10 and 20(ground) are to be connected to the C.R.O.
Waveform:
Results:
PWM pulses of 50% duty cycle are generated using full compare unit.
Inferences:
If Timer1 period register T1PR value is set to value 4999 and compare unit value is set to 2500
and hence PWM pulses of 50% duty cycle will be generated.
Acquisition of signal from ADC

Exp No.:10
Date:
Objectives:
Write a program to acquire the signal from the ADC and store it in the specified
memory location.
Hardware:
1.
2.
3.
4.
5.
6.
PC
TMS320LF2407A
Resister 17K
Potentiometer 10K
Software:
Windows 95/98/NT/XP
Registers Involved:
SCSR1: System control status register1
SCSR2: System control status register2
ADCTRL1: ADC control register1
MAX_CONV: Maximum number of auto conversion
CHSELSEQ1: ADC input channel select sequencing control register
ADCTRL2: ADC control register2
RESULT0: ADC result register0
Algorithm:
1. Start
2. Configure SCSR1 in order to enable the clock for ADC and select the clock
prescalar.
3. Configure SCSR2 to disable the watchdog timer and to select the mode of
operation.
4. Configure ADCTRL1 in order to decide the acquisition time prescalar and to run
the ADC in start-stop mode.
5. Configure MAX_CONV register for maximum one conversion in one ADC
trigger.
6. Configure CHSELSEQ1 register to select 1 of the 16 multiplexed analog input
ADC channels for an auto-sequenced conversion and to specify the sequence of
conversion.
7. Configure ADCTRL2 to trigger the ADC through software.
8. Give some delay for ADC to finish the conversion.
9. Check whether the conversion is finished or not by monitoring the bit 12 in
ADCTRL2.
10.
If the conversion is finished load the result from RESULT0 register into
the accumulator. Shift the data by 6 and store it into desired memory location.
11. End
Flowchart:
START
Set data page to 224. Initialize

SCSR1 and SCSR2
Set data page to 225. Initialize

ADCTRL1 for start-stop mode
Initialize MAX_CONV for one

conversion
Initialize CHSELSEQ1. To select

channel 0 for conversion
Initialize ADCTRL2 to start

ADC by S/W trigger
B
Wait for ADC to complete the
conversion.
NO
Check if conversion is complete or not
YES
Store the result in
accumulator
B
Load AR0 with specified
memory address
Load accumulator data to memory address

pointed by AR0
Program:.def _c_int0
.include f2407.h
.text
_c_int0
LDP #225
SPLK #0681h, SCSR1
LACL SCSR2
OR #000Bh
AND #000Fh
SACL SCSR2
LDP #225
SPLK #4000h, ADCTRL1
NOP
NOP
SPLK #0000h, MAX_CONV
SPLK #0000h, CHSELSEQ1
NOP
NOP
LOOP1: SPLK #2000h, ADCTRL2
LOOP2: NOP
NOP
NOP
LACL ADCTRL2
XOR #2200h
BCND LOOP3, EQ
B LOOP2
LOOP3: LDP #225
LACL RESULT0
SFR 6
MAR *, AR0
LAR AR0, #300h
SACL *+, 0, AR0
;Fout=1*Fin, enable ADC clk,ILLADR=0

;disable watchdog override, map SARAM on both
Data And program memory
;put ADC into RESET

; takes ADC out of RESET and select start and stop
Mode of conversion
;configure ADC for only 1 conversion
; select channel 0 of ADC for conversion
; put sequencer1 into RESET
;SOC through software trigger
; wait for ADC to complete the conversion
; check whether ADC conversion is completed or not
: load the result into the accumulator

: shift the data in the accumulator by 6 in order to
Truncate the last 6 bits
: make AR0 as current auxiliary register
: load AR0 with required memory location
: store the data of the accumulator into the specified
Memory location
B LOOP1
Result:
The analog signal at ADCIN0 pin of DSP is converted into the equivalent digital value
and the result is stored into specified memory location.
GENERATION OF PWM PULSES USING GP TIMERS FOR

CHOPPER
Exp.No:11
Date:
Objective:
To write a program to generate PWM pulses of frequency 20kHz using GPT timer compare units.
Hardware:
PC
TMS320LF2407A
Resisters 1K
TL250
MOSFET IRF 640
Software:
Windows 95/98/NT/XP
Algorithm:
Step1: Start.
Step4: Initialize T1PR for 20kHz frequency.
Step5: set T1CNT to zero.
Step6: Set T1CMPR for 50%duty cycle.
Step7: Configure GPTCONA for active high pulse.
Step8: Configure T1CON for continuous up count mode
Step9: Wait till the PWM is generated
Step10: repeat the process
Registers Involved:
T1PR
T1PR register is to be loaded as follows-
desired PWM period

50106
1=
1=249
200109
Period Value =249
PRESCALER=2 This is set by bits 10-8 of T2CON
T1CMPR= 125
For 50% duty cycle T1CMPR value will be half of T1PR
GPTCONA = 0042h
Enable all GP Timer Compare outputs and polarity of GP Timer1 compare outputs to active High
T1CON=9142h
Select Continuous Up counting mode, set input pre-scalar to 1,select internal clock, enable timer
operation and program the counter to stop immediately on emulation suspend.
MCRA = 0FFFFh
Start
Set Data page to 224
Initialize SCSR1 for EVA module

Set data page to 225 & configure MCRA to operate in primary function
Set data page to 232

Initialize T1PR for 20kHZ frequency
Set T1CNT to zero
Set T1CMPR for 50% duty cycle

Configure GPTCONA Register for active high pulse
Configure T1CON for continuous up count mode
Wait till PWM is generated
End
Program:
.def _c_int0
.include f2407.h
.text
_c_int0
LDP #224
SPLK #070CH,SCSR1
LDP #0E1H
SPLK #0FFFFH,MCRA
LDP #0E8H
SPLK #0000H,T1CNT
SPLK #249,T1PR
SPLK #125,T1CMPR
SPLK #0042H,GPTCONA
SPLK #9142H,T1CON
LOOP B LOOP
Circuit Diagram:
Pin Diagram:
Connector pin location:
Connection Circuitry:
Output Waveform1:
waveform obtained when connected to the driver circuit TLP250.

Result:
A symmetric PWM pulse of 50kHz of 50% duty cycle is obtained and tested on type A chopper with
R load
PWM PULSE GENERATION FOR SINGLE PHASE INVERTER

Exp. No:12
Date:
Objective
To write a program to generate PWM pulses for a single phase inverter using DSP F2407
and to verify it experimentally.
Equipments Required
Hardware:
PC
TMS320LF2407A
+5V power supply for the DSK, converted to 3.3V for the 2407 CPU
Optocoupler IC : TLP250
Mosfet: IRF540
Bread board, DC power supply and wires
Software:
Windows 95/98/NT/XP
Algorithm
Step1: Start.
Step4: Initialize timer counter value to zero.
Step6: Set up and load DBTCON, to use a dead band of 1s
Step7: Initialize CMPR1
Step8: Set up and load COMCON without enabling compare operation.
Step11: Rewrite CMPRx with newly determined values.
Step12: End
In the following program up counting of timer 1 has been used.
Registers Involved
SCSR1 : 0605h
The clock prescalar is selected as 1 x Fin and the EVA module is enabled.
Fin is the CPU clock frequency = 10 MHz
MCRA = 0FFFh

T1PR=030Dh
T1PR register is to be loaded as followsPeriod Value =CPUCLK/[2*(PRESCALER * DESIRED FREQ) ]= 10*10^6/(2*128 x 50)=781d=030dh
for up down counting mode.

CPUCLK=10MHz
PRESCALER=128 This is set by bits 10-8 of T1CON

T1CON=8F4Ah
Select Continuous Up-Down counting mode ,set input pre-scaler to 128,select internal clock , enable timer
operation and program the counter such that its operation is not affected by emulation suspend.
CMPR1= 0186h
For 50% duty cycle CMPR1 value will be half of T1PR.
CMPR2= 0176h
For a deadband of 240s
GPTCONA = 004Ah
Enable all GP Timer Compare outputs and polarity of GP Timer1 and GP Timer2 compare outputs to active
High.
ACTRA = 0012h
Select action on compare1 output, PWM1 as active high and compare2 output,PWM2 as active low.
COMCONA = CA00h
Program
.def _c_int0
.include f2407.h
.text
_c_int0
NOP
LDP #224
SPLK# 0605H, SCSR1
LDP# 225
SPLK# 0FFFFH, MCRA
LDP# 0E8H
SPLK# 0000H, T1CNT
SPLK# 004AH, GPTCONA
SPLK# 030DH, T1PR
SPLK# 0186H, CMPR1
SPLK# 0176H, CMPR2
SPLK# 0012H, ACTRA
SPLK# 0CA00H, COMCONA
SPLK# 8F4AH, T1CON
END B END
Compare unit 1 output PWM1 and PWM2

To check PWM1 : 9 and 19(ground) pins
To check PWM2 : 10 1nd 20(ground) pins
50Hz pulses
Pulses with dead band(50Hz)
HARDWARE SETUP
Single Phase Inverter

The pulses generated using the DSP LF2407 was given to the MOSFETs of the single phase
inverter through an opto coupler isolator.
The Toshiba TLP 250 which is a GaAlAs LED and an integrated photo detector forming an 8 pin
DIP package is used as an isolator or a gate drive circuit.
Input Threshold Current, If = 5mA (max)
Supply Current, Icc = 11mA(max)
Supply Voltage, Vcc = 10-35 V
Output Current, Io = 1.5A(max)
Switching Time(tpLH/tpHL) = 1.5 ms(max)
Isolation Voltage = 2500 Vrms(min)
Maximum Operating Insulation Voltage = 530 Vpk
Highest permissible Over Voltage = 4000Vpk
Pin Configuration of the Optocoupler (TLP250)
HARDWARE RESULTS
Output of the inverter
Conclusion
This experiment is performed to get PWM output of frequency 50 Hz and 50%
duty cycle which can be used as the switching pulses for a single phase Inverter. The
frequency of the pulses can be varied by adjusting the value of period register, T1PR and
pre scalar values in T1CON and SCSR1 registers. To select the logic level of PWM
output from compare actions, the value in ACTRA is configured. Instead of using a
deadband registers, 2 compare registers are configured to get a deadband of 240 s.
GENERATION OF SIX PWM PULSES WITH AND WITHOUT DEAD BAND

EXP.NO: 13
DATE:
Objective: To write a program to generate six PWM pulses with and without dead band
Hardware:
1.
PC
2.
TMS320LF2407A
3.
4.
Software:
1
Windows 95/98/NT/XP
2
Algorithm:
Step1: Start.
Step4: Initialize timer counter T1CNT value to zero.
Step6: Set up and load DBTCON.
Step7: Set up and load T1PR
Step8: Initialize CMPR1, CMPR2, CMPR3
Step11: Set up and load GPTCONA.
Step12: end
FLOWCHART:
start
set data page to DP_PF1

Set data page to DP_PF1 & enable clock to EVA module
Set data page to DP_PF2 & configure port pins to operate in primary function
Set data page to 0E8h & timer1 counter to 0000h
Configure GPTCONA to 0042h
Set T1pr to 1387h and compare register to 09C4h
Configure compare action control register ACTRA to 0666h
Configure Compare Control Register with enabling compare operation i.e, to 0CA00h
Configure Timer Control Register to 1046h

End
Registers Involved:
T1PR= 1387H
T1PR register is to be loaded as followsPeriod Value = (5000-1) =4999
CPUCLK=10MHz
PRESCALER=1 this is set by bits 10-8 of T1CON
CMPR1, CMPR2, CMPR3= 2500
For 50% duty cycle CMPR1, CMPR2, CMPR3 value will be half of T1PR
GPTCONA = 004Ah
T1CON=1046h
Select Continuous Up counting mode, set input pre-scalar to 1,select internal clock, enable
MCRA = 0FFFh
ACTRA = 0666h
Pin 1,3,5 are active high . Pin 2,4,6 are active low
COMCONA = CA00h
DBTCON = 0FF4h
Enabling (EDBT1, EDBT2, EDBT3). Dead band prescaler = x/32. Dead band time period = 15
Program:
.def _c_int0
.include f2407.h
.text
_c_int0
NOP
LDP #DP_PF1
SPLK #0005H,SCSR1
LDP #DP_PF2
SPLK #0FFFFH,MCRA
LDP #0E8H
SPLK #0000H,T1CNT
SPLK #004A,GPTCONA
SPLK #1387H,T1PR
SPLK #0FF4h,DBTCONA
SPLK #,09C4H,CMPR1
SPLK #,09C4H,CMPR2
SPLK #,09C4H,CMPR3
SPLK #0666H,ACTRA
SPLK #0CA00H,COMCONA
SPLK #1046,T1CON
loop
;set data page

;Enabling clock to EVA module
;set data page
;configure pins to operate in
;primary function
;set data page
;set timer1 counter
;Configure GPtimer Control Register
;load timer1 period register with
;desired value
; Enabling ( EDBT1, EDBT2, EDBT3)
;set compare value for PWM 1 and 2
; set compare value for PWM 3 and 4
; set compare value for PWM 5 and 6
;configure compare action control
;register
;configure register with enabling
;compare register
;configure timer control register
;as required
B loop
To check the square wave output on the oscilloscope, the following connections should be made:
Compare Unit 1 has two outputs namely PWM1 and PWM2.
Waveform:
Without Dead band:
With Dead band:
Results:
PWM pulses of 50% duty cycle are generated using full compare unit.
Inferences:
If Timer1 period register T1PR value is set to value 4999 and compare 1, 2, 3 values is set to
2500 and hence PWM pulses of 50% duty cycle will be generated.
Generation of PWM pulses using F28335eZDSP

Ex.No:14
Date:
Objective: To generate PWM pulses using MATLAB/CCS interface and F28335 kit.
Hardware:
PC
TMS320LF28335A
+5V power supply for the DSK, converted to 3.3V for the 28335 CPU
DB25 connector printer cable and USB.
Software:
Windows 95/98/NT/XP
Algorithm:
Step1: Open MATLAB2009b and check for CCS board info.
Step2: Create a new model in Simulink
Step3: In this model place the block F28335eZdsp from Simulink library. This can be
done as Target support package- supported processors- Texas instruments- C2000Target Preferences- F28335eZdsp
Step4: Now add two ePWM block to this model from Simulink library. This can be done
as Target support package- supported processors- Texas instruments- chip supportC28x3x- ePWM
Step5: Now change the simulation time to inf and go to the configuration parameters
of simulation and change Type as Fixed step and solver as discrete (no continuous
state) and uncheck the Limit data points to last option. Then click apply and OK.
Step6: SAVE the model.
Step7: Start Incremental build.
Simulation diagram in MATLAB:

Following the algorithm steps, the simulation diagram can be developed as shown:
The PWM blocks can be configured as:

Step1: Set the timer period clock value and the count mode as UP count mode.
Step2: Enable ePWM1A and set the compare value and do the same for ePWM1B block
also.
Step3: Now initialise deadband block for ePWM1A block and set the property Poles of
deadband delay as Positive and its period value as 512.
Step4: Repeat the steps1-3 for ePWM2 block also and in step3 change the property Poles
of deadband delay as Negative.
Step5: Save the project and do Incremental build and connect two probes to pin 9-19 and
11-20 of P8 of the F28335eZDSP kit and observe the waveform on DSO.
Result:
The pulses are generated using ePWM blocks and they are observed on the DSO
by connecting it to F28335eZDSP board. These pulses can be used for switching the
single phase inverter.
Output Waveform

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School of Electrical Engineering

DSP BASED CONTROL OF

VIT - A PLACE TO LEARN; A CHANCE TO GROW

SCHOOL OF ELECTRICAL ENGINEERING

Certified that this is a bonafide record of work done by

_______________________ at Vellore Institute of Technology University,

Title of the Experiment

Addition Using Immediate, Direct and Indirect

Storing and Moving of a Block of Data

Generation of Pulses Using GPIO

Generation of Sine Wave

Generation of PWM Pulses Using GP Timers for

PWM Pulse Generation for Single Phase Inverter

Filenames of source code and object libraries

Launching Code Composer Studio:

Important Icons Used in Code Composer Studio v3.1:

Used to launch Code Composer Studio

Step into button

Step out of button

Adding Files to a Project:

C:\CCStudio_3.1\C2400\cgtools\lib\ directory and add the rts2xx.lib file

C:\CCStudio_3.1\tutorial\dsk2407\volume1\ directory and add load.asm, vectors.asm, volume.cmd

ADDITION USING IMMEDIATE, DIRECT AND INDIRECT

;Load the accumulator with data FDDFh

Value before execution

Value after execution

Exp. No: 1(b)

; set data page as 100h

Value after execution

Exp. No: 1(c)

; set data page as 100h

; load accumulator with data 0DA0Fh

LAR AR1, #8010h

; load auxiliary register AR1 with data

Value before execution

Value after execution

Exp. No: 1(d)

; set data page as 100h

Value before execution

Value after execution

Exp. No: 1(e)

; Set data page as 100h

Value before execution

Value after execution

Storing and Moving of a Block of Data

Add 1 to acc. And decrement count by 1

Load the content of AR1 in accumulator,

Load accumulator with data in the memory location

; Load count value

Value before execution

Complement the Data

Value after execution

Load Data Page with 7

Load Count Value as 127 and Store 380h value in AR1

Load AR1 register value in LACL and increment AR1 value by 1

Complement the data and store it and decrease count by 1

; Load count value

Value before execution