74LVC00A: 1. General Description
74LVC00A: 1. General Description
74LVC00A: 1. General Description
1. General description
The 74LVC00A provides four 2-input NAND gates.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall
times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC00AD
40 C to +125 C
SO14
SOT108-1
74LVC00ADB
40 C to +125 C
SSOP14
SOT337-1
74LVC00APW
40 C to +125 C
TSSOP14
SOT402-1
74LVC00ABQ
40 C to +125 C
SOT762-1
74LVC00A
NXP Semiconductors
4. Functional diagram
1
1 1A
2 1B
1Y 3
4 2A
5 2B
2Y 6
9 3A
10 3B
3Y 8
12 4A
13 4B
4Y 11
2
4
5
9
10
12
13
&
&
&
8
A
Y
11
&
B
mna212
Fig 1.
mna211
mna246
Logic symbol
Fig 2.
Fig 3.
5. Pinning information
1A
terminal 1
index area
14 VCC
5.1 Pinning
1B
1Y
12 4A
2A
00
11 4Y
11 4Y
2B
GND (1)
10 3B
10 3B
2Y
13 4B
12 4A
1Y
2A
2B
2Y
3A
1B
13 4B
GND
3Y
3Y
14 VCC
GND
1A
00
3A
001aac939
001aac938
Fig 4.
Fig 5.
Pin description
Symbol
Pin
Description
1A to 4A
1, 4, 9, 12
data input
1B to 4B
2, 5, 10, 13
data input
1Y to 4Y
3, 6, 8,11
data output
GND
ground (0 V)
VCC
14
supply voltage
74LVC00A
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NXP Semiconductors
6. Functional description
Table 3.
Function selection[1]
Input
Output
nA
nB
nY
[1]
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
VI
input voltage
IOK
Conditions
VI < 0 V
[1]
VO
output voltage
IO
output current
VO = 0 V to VCC
ICC
supply current
IGND
ground current
Ptot
Tstg
storage temperature
Tamb = 40 C to +125 C
[1]
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2]
The output voltage ratings may be exceeded if the output current ratings are observed.
[3]
[2]
[3]
Min
Max
Unit
0.5
+6.5
50
mA
0.5
+6.5
50
mA
0.5
VCC + 0.5
50
mA
100
mA
100
mA
500
mW
65
+150
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Typ
Max
Unit
1.65
3.6
1.2
5.5
VCC
40
+125
20
ns/V
10
ns/V
functional
VI
input voltage
VO
output voltage
Tamb
ambient temperature
t/V
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NXP Semiconductors
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
40 C to +85 C
Conditions
Min
HIGH-level
input voltage
VIH
LOW-level
input voltage
VIL
VOH
HIGH-level
output
voltage
LOW-level
output
voltage
VOL
Typ[1]
40 C to +125 C
Max
Min
Unit
Max
VCC = 1.2 V
1.08
1.08
0.65 VCC -
0.65 VCC -
1.7
1.7
2.0
2.0
0.12
VCC = 1.2 V
0.12
0.35 VCC -
0.35 VCC V
0.7
0.7
0.8
0.8
IO = 100 A;
VCC = 1.65 V to 3.6 V
VCC 0.2
VCC 0.3
1.2
1.05
1.8
1.65
2.2
2.05
2.4
2.25
2.2
2.0
IO = 100 A;
VCC = 1.65 V to 3.6 V
0.2
0.3
0.45
0.65
VI = VIH or VIL
VI = VIH or VIL
0.6
0.8
0.4
0.6
0.55
0.8
0.1
20
II
ICC
supply
current
0.1
10
40
ICC
additional
supply
current
500
5000
CI
input
capacitance
VCC = 0 V to 3.6 V;
VI = GND to VCC
4.0
pF
[1]
All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C.
74LVC00A
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tpd
40 C to +85 C
Conditions
Min
Max
Min
Max
12
ns
0.3
3.8
8.4
0.3
9.7
ns
1.0
2.2
4.8
1.0
5.7
ns
[2]
tsk(o)
power dissipation
capacitance
CPD
[1]
40 C to +125 C Unit
Typ[1]
VCC = 2.7 V
1.0
2.3
5.1
1.0
5.9
ns
0.5
2.0
4.3
0.5
5.1
ns
1.0
1.5
ns
[3]
[4]
5.6
pF
8.9
pF
11.8
pF
Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2]
[3]
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4]
11. Waveforms
VI
nA, nB input
VM
GND
tPHL
tPLH
VOH
nY output
VM
mna213
VOL
Fig 6.
74LVC00A
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tW
VI
90 %
negative
pulse
VM
VM
10 %
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
VM
VM
10 %
0V
tW
VCC
PULSE
GENERATOR
VI
VO
DUT
RT
CL
RL
001aaf615
Fig 7.
Table 8.
Supply voltage
Input
Load
VI
tr, tf
CL
RL
1.2 V
VCC
2 ns
30 pF
1 k
1.65 V to 1.95 V
VCC
2 ns
30 pF
1 k
2.3 V to 2.7 V
VCC
2 ns
30 pF
500
2.7 V
2.7 V
2.5 ns
50 pF
500
3.0 V to 3.6 V
2.7 V
2.5 ns
50 pF
500
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NXP Semiconductors
SOT108-1
A
X
c
y
HE
v M A
Z
8
14
Q
A2
(A 3)
A1
pin 1 index
Lp
1
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
D (1)
E (1)
HE
Lp
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.16
0.15
0.010 0.057
inches 0.069
0.004 0.049
0.05
0.244
0.039
0.041
0.228
0.016
0.028
0.024
0.01
0.01
0.028
0.004
0.012
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
Fig 8.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
74LVC00A
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NXP Semiconductors
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
A
X
c
y
HE
v M A
Z
8
14
Q
A2
(A 3)
A1
pin 1 index
Lp
L
7
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
D (1)
E (1)
HE
Lp
Z (1)
mm
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
1.4
0.9
8o
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT337-1
Fig 9.
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-150
74LVC00A
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74LVC00A
NXP Semiconductors
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
c
y
HE
v M A
14
Q
(A 3)
A2
A1
pin 1 index
Lp
L
7
e
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
D (1)
E (2)
HE
Lp
Z (1)
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
9 of 14
74LVC00A
NXP Semiconductors
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT762-1
14 terminals; body 2.5 x 3 x 0.85 mm
A
A1
E
detail X
terminal 1
index area
terminal 1
index area
e1
e
2
y1 C
v M C A B
w M C
Eh
e
14
13
9
Dh
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
max.
A1
0.05
0.00
0.30
0.18
D (1)
Dh
E (1)
Eh
0.2
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
e
0.5
e1
y1
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT762-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
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NXP Semiconductors
13. Abbreviations
Table 9.
Abbreviations
Acronym
Description
CDM
DUT
ESD
ElectroStatic Discharge
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
Revision history
Document ID
Release date
Change notice
Supersedes
74LVC00A v.7
20120425
74LVC00A v.6
74LVC00A v.5
Modifications:
74LVC00A v.6
Modifications:
20120106
The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
Table 4, Table 5, Table 6, Table 7 and Table 8: values added for lower voltage ranges.
74LVC00A v.5
20030904
Product specification
74LVC00A v.4
74LVC00A v.4
20030507
Product specification
74LVC00A v.3
74LVC00A v.3
20020305
Product specification
74LVC00A v.2
74LVC00A v.2
19980428
Product specification
74LVC00A v.1
74LVC00A v.1
19970811
Product specification
74LVC00A
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Product status[3]
Definition
Development
This document contains data from the objective specification for product development.
Qualification
Production
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LVC00A
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15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
74LVC00A
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17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 3
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section Legal information.