General Description: Quad Bistable Transparant Latch
General Description: Quad Bistable Transparant Latch
General Description: Quad Bistable Transparant Latch
1. General description
The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specied in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time prior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched outputs remain stable as long as the LEnn is LOW.
2. Features
s s s s s Complementary Q and Q outputs VCC and GND on the center pins Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s Multiple package options s Specied from 40 C to +80 C and from 40 C to +125 C.
Philips Semiconductors
74HC75
Quad bistable transparant latch
Min
Typ
Max
Unit
VI = GND to VCC
[1]
11 11 3.5 42
ns ns pF pF
CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs.
4. Ordering information
Table 2: Ordering information Package Temperature range 74HC75N 74HC75D 74HC75DB 74HC75PW 40 C to +125 C 40 C to +125 C 40 C to +125 C 40 C to +125 C Name DIP16 SO16 SSOP16 TSSOP16 Description plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT38-4 SOT109-1 SOT338-1 SOT403-1 Type number
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Philips Semiconductors
74HC75
Quad bistable transparant latch
5. Functional diagram
1D
1Q
16
13
LE12
CP L1
1Q
2D
2Q
13
15
2 1D
CP L2
2Q
14
3
2D
3D
3Q
10
3D
3Q 3Q 4Q 4Q LE34 4
10 11 9 8
LE34
CP L3
3Q
11
4D
001aab851
4D
4Q
CP L4
4Q
001aab853
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Philips Semiconductors
74HC75
Quad bistable transparant latch
1D
1Q
LE12
CP LATCH 1
1Q
13
C1 16
1D
2D
2Q
1 15
CP LATCH 2
2Q
3 14
C1 9
3D
3Q
1D
8 10
LE34
CP LATCH 3
3Q
6 11
001aab852
4D
4Q
CP LATCH 4
4Q
001aab854
6. Pinning information
6.1 Pinning
1Q 1D 2D LE34 VCC 3D 4D 4Q
1 2 3 4
16 1Q 15 2Q 14 2Q 13 LE12
75
5 6 7 8
001aab850
12 GND 11 3Q 10 3Q 9 4Q
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Philips Semiconductors
74HC75
Quad bistable transparant latch
7. Functional description
7.1 Function table
Table 4: Function table [1] Input LEnn Data enabled Data latched
[1]
Operating mode
Output nD L H X nQ L H q nQ H L q
H H L
H = HIGH voltage level; L = LOW voltage level; q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW LEnn transition; X = dont care.
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Philips Semiconductors
74HC75
Quad bistable transparant latch
8. Limiting values
Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC, IGND Tstg Ptot Parameter supply voltage input diode current output diode current output source or sink current VCC or GND current storage temperature power dissipation DIP16 package SO16, SSOP16 and TSSOP16 packages
[1] [2]
[1] [2]
Conditions VI < 0.5 V or VI > VCC + 0.5 V VO < 0.5 V or VO > VCC + 0.5 V VO = 0.5 V to VCC + 0.5 V
Min 0.5 65 -
Unit V mA mA mA mA C mW mW
Above 70 C: Ptot derates linearly with 12 mW/K. Above 70 C: Ptot derates linearly with 8 mW/K.
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Philips Semiconductors
74HC75
Quad bistable transparant latch
Tamb = 40 C to +85 C
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Philips Semiconductors
74HC75
Quad bistable transparant latch
Table 7: Static characteristics continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VOL Parameter LOW-level output voltage Conditions VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V ILI ICC input leakage current quiescent supply current VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V ILI ICC input leakage current quiescent supply current VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.33 0.33 1.0 80 V V V V V A A Min Typ Max Unit
Tamb = 40 C to +125 C VIH HIGH-level input voltage 1.5 3.15 4.2 0.1 0.1 0.1 0.4 0.4 1.0 160 V V V V V A A V V V V V 0.5 1.35 1.8 V V V V V V
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Philips Semiconductors
74HC75
Quad bistable transparant latch
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Philips Semiconductors
74HC75
Quad bistable transparant latch
Table 8: Dynamic characteristics continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; unless otherwise specied, see Figure 10. Symbol CPD Parameter power dissipation capacitance per latch propagation delay nD to nQ Conditions VI = GND to VCC
[1]
Min -
Typ 42
Max -
Unit pF
Tamb = 40 C to +85 C tPHL, tPLH see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V propagation delay nD to nQ see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V propagation delay LEnn to nQ see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V propagation delay LEnn to nQ see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tTHL, tTLH output transition time see Figure 6 and 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tW enable pulse width HIGH see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tsu set-up time nD to LEnn see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V th hold time nD to LEnn see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 3 3 3 ns ns ns 75 15 13 ns ns ns 100 20 17 ns ns ns 95 19 16 ns ns ns 155 31 26 ns ns ns 150 30 26 ns ns ns 150 30 26 ns ns ns 140 28 24 ns ns ns
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Philips Semiconductors
74HC75
Quad bistable transparant latch
Table 8: Dynamic characteristics continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; unless otherwise specied, see Figure 10. Symbol tPHL, tPLH Parameter propagation delay nD to nQ Conditions see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V propagation delay nD to nQ see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V propagation delay LEnn to nQ see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V propagation delay LEnn to nQ see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tTHL, tTLH output transition time see Figure 6 and 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tW enable pulse width HIGH see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tsu set-up time nD to LEnn see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V th hold time nD to LEnn see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
[1] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs.
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Min
Typ
Max
Unit
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Philips Semiconductors
74HC75
Quad bistable transparant latch
12. Waveforms
nD input
VM
tPHL nQ output
tPLH
VM
tTHL
tTLH
001aab855
VM = 0.5 VI.
Fig 6. Waveforms showing the data input (nD) to output (nQ) propagation delays and the output transition times
nD input
VM
tPHL nQ output
tPLH
VM
tTHL
tTLH
001aab856
VM = 0.5 VI.
Fig 7. Waveforms showing the data input (nD) to output (nQ) propagation delays and the output transition times
nD input
VM th VM th
tsu
nQ output
Q=D
Q=D
001aab858
The shaded areas indicate when the input is permitted to change for predictable output performance. VM = 0.5 VI.
Fig 8. Waveforms showing the data set-up and hold times for nD input to LEnn input
9397 750 13816 Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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Philips Semiconductors
74HC75
Quad bistable transparant latch
nD input
LEnn input
VM tW tPHL
nQ output
tPLH nQ output VM
tPHL
tTLH
tTHL
001aab857
VM = 0.5 VI.
Fig 9. Waveforms showing the latch enable input (LEnn) pulse width, the latch enable input to outputs (nQ, nQ) propagation delays and the output transition times
VO
Test data is given in Table 9. Denitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance.
Fig 10. Load circuitry for switching times Table 9: Supply VCC 2.0 V 4.5 V 6.0 V 5.0 V Test data Input VI VCC VCC VCC VCC tr, tf 6 ns 6 ns 6 ns 6 ns Load CL 50 pF 50 pF 50 pF 15 pF
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Philips Semiconductors
74HC75
Quad bistable transparant latch
D seating plane
ME
A2
A1
c Z e b1 b 16 9 b2 MH w M (e 1)
pin 1 index E
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
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Philips Semiconductors
74HC75
Quad bistable transparant latch
SOT109-1
A X
c y HE v M A
Z 16 9
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
8 o 0
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Philips Semiconductors
74HC75
Quad bistable transparant latch
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
A X
c y HE v M A
Z 16 9
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 8 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
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Philips Semiconductors
74HC75
Quad bistable transparant latch
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
c y HE v M A
16
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
8
w M detail X
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
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Philips Semiconductors
74HC75
Quad bistable transparant latch
The format of this data sheet has been redesigned to comply with the current presentation and information standard of Philips Semiconductors. Removed type number 74HCT75. Inserted family specication. Product specication Product specication 74HC_HCT75_1 -
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Philips Semiconductors
74HC75
Quad bistable transparant latch
III
Product data
Production
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Denitions
Short-form specication The data in a short-form specication is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values denition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specication is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specied use without further testing or modication.
17. Disclaimers
Life support These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production), relevant changes will be communicated via a Customer Product/Process Change Notication (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specied.
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74HC75
Quad bistable transparant latch
19. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19 Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information . . . . . . . . . . . . . . . . . . . . 19