74HC HCT574

1.
General description
The 74HC574; 74HCT574 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.
The 74HC574; 74HCT574 are octal D-type flip-flops featuring separate D-type inputs for
each flip-flop and 3-state outputs for bus-oriented applications. A clock (CP) and an output
enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their
individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH
CP transition. When OE is LOW the contents of the 8 flip-flops are available at the
outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of
the OE input does not affect the state of the flip-flops.
The 74HC574; 74HCT574 is functionally identical to:
74HC564: but has non-inverting outputs
74HC374; 74HCT374: but has a different pin arrangement
2. Features and benefits
3-state non-inverting outputs for bus oriented applications
8-bit positive, edge-triggered register
Common 3-state output enable input
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information

74HC574; 74HCT574
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 5 25 April 2012 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC574N 40 C to +125 C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HCT574N
74HC574D 40 C to +125 C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74HCT574D
74HC_HCT574 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 25 April 2012 2 of 19
NXP Semiconductors 74HC574; 74HCT574
4. Functional diagram

74HC574DB 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
74HCT574DB
74HC574PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
74HCT574PW
Table 1. Ordering information continued
Type number Package
Temperature range Name Description Version
Fig 1. Functional diagram
mna800
3-STATE
OUTPUTS
FF1
to
FF8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7 12
13
14
15
16
17
18
19 D0
D1
D2
D3
D4
D5
D6
D7
CP
OE
9
11
1
8
7
6
5
4
3
2
Fig 2. Logic diagram
001aah077
D0
CP
OE
Q0
D
CP
Q
FF1
D1
Q1
D
CP
Q
FF2
D2
Q2
D
CP
Q
FF3
D3
Q3
D
CP
Q
FF4
D4
Q4
D
CP
Q
FF5
D5
Q5
D
CP
Q
FF6
D6
Q6
D
CP
Q
FF7
D7
Q7
D
CP
Q
FF8

5. Pinning information
5.1 Pinning

Fig 3. Logic symbol Fig 4. IEC logic symbol
mna798
D0
D1
D2
D3
D4
D5
D6
D7
OE
CP
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
11
1
12
13
14
15
16
17
18
19
9
8
7
6
5
4
3
2
mna446
12
13
14
15
16
17
18
11
C1
1
EN
1D
19
9
8
7
6
5
4
3
2
Fig 5. Pin configuration DIP20 and SO20 Fig 6. Pin configuration SSOP20 and TSSOP20
74HC574
74HCT574
OE V
CC
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
GND CP
001aan290
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19 74HC574
74HCT574
OE V
CC
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
GND CP
001aan291
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
5.2 Pin description

6. Functional description

[1] H = HIGH voltage level;
h = HIGH voltage level one setup time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
l = LOW voltage level one setup time prior to the HIGH-to-LOW CP transition;
Z = high-impedance OFF-state;
= LOW-to-HIGH clock transition.
7. Limiting values

[1] For DIP20 package: P
tot
derates linearly with 12 mW/K above 70 C.
[2] For SO20: P
tot
derates linearly with 8 mW/K above 70 C.
For SSOP20 and TSSOP20 packages: P
tot
derates linearly with 5.5 mW/K above 60 C.
Table 2. Pin description
Symbol Pin Description
OE 1 3-state output enable input (active LOW)
D[0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input
GND 10 ground (0 V)
CP 11 clock input (LOW-to-HIGH, edge triggered)
Q[0:7] 19, 18, 17, 16, 15, 14, 13, 12 3-state flip-flop output
V
CC
20 supply voltage
Table 3. Function table
[1]
Operating mode Input Internal
flip-flop
Output
OE CP Dn Qn
Load and read register L l L L
L h H H
Load register and disable output H l L Z
H h H Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7 V
I
IK
input clamping current V
I
< 0.5 V or V
I
> V
CC
+ 0.5 V - 20 mA
I
OK
output clamping current V
O
< 0.5 V or V
O
> V
CC
+ 0.5 V - 20 mA
I
O
output current V
O
= 0.5 V to (V
CC
+ 0.5 V) - 35 mA
I
CC
supply current - +70 mA
I
GND
ground current - 70 mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation DIP20 package
[1]
- 750 mW
SO20, SSOP20 and TSSOP20 packages
[2]
- 500 mW
8. Recommended operating conditions

9. Static characteristics

Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC574 74HCT574 Unit
Min Typ Max Min Typ Max
V
CC
supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
V
I
input voltage 0 - V
CC
0 - V
CC
V
V
O
output voltage 0 - V
CC
0 - V
CC
V
T
amb
ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate V
CC
= 2.0 V - - 625 - - - ns/V
V
CC
= 4.5 V - 1.67 139 - 1.67 139 ns/V
V
CC
= 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC574
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
V
CC
= 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
V
CC
= 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
V
CC
= 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
V
CC
= 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20 A; V
CC
= 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
I
O
= 20 A; V
CC
= 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
I
O
= 20 A; V
CC
= 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
I
O
= 6.0 mA; V
CC
= 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
I
O
= 7.8 mA; V
CC
= 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20 A; V
CC
= 2.0 V - 0 0.1 - 0.1 - 0.1 V
I
O
= 20 A; V
CC
= 4.5 V - 0 0.1 - 0.1 - 0.1 V
I
O
= 20 A; V
CC
= 6.0 V - 0 0.1 - 0.1 - 0.1 V
I
O
= 6.0 mA; V
CC
= 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
I
O
= 7.8 mA; V
CC
= 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
I
I
input leakage
current
V
I
= V
CC
or GND;
V
CC
= 6.0 V
- - 0.1 - 1.0 - 1.0 A
I
OZ
OFF-state
output current
V
I
= V
IH
or V
IL
;
V
O
= V
CC
or GND;
V
CC
= 6.0 V
- - 0.5 - 5.0 - 10.0 A
I
CC
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
- - 8.0 - 80 - 160 A
C
I
input
capacitance
- 3.5 - pF
74HCT574
V
IH
HIGH-level
input voltage
V
CC
= 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
V
IL
LOW-level
input voltage
V
CC
= 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
I
O
= 20 A 4.4 4.5 - 4.4 - 4.4 - V
I
O
= 6 mA 3.98 4.32 - 3.84 - 3.7 - V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
I
O
= 20 A - 0 0.1 - 0.1 - 0.1 V
I
O
= 6.0 mA - 0.16 0.26 - 0.33 - 0.4 V
I
I
input leakage
current
V
I
= V
CC
or GND;
V
CC
= 5.5 V
- - 0.1 - 1.0 - 1.0 A
I
OZ
OFF-state
output current
V
I
= V
IH
or V
IL
; V
CC
= 5.5 V;
V
O
= V
CC
or GND per input
pin; other inputs at V
CC
or
GND; I
O
= 0 A
- - 0.5 - 5.0 - 10 A
I
CC
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
- - 8.0 - 80 - 160 A
I
CC
additional
supply current
V
I
= V
CC
2.1 V;
other inputs at V
CC
or GND;
V
CC
= 4.5 V to 5.5 V;
I
O
= 0 A
per input pin; Dn inputs - 50 180 - 225 - 245 A
per input pin; OE input - 125 450 - 563 - 613 A
per input pin; CP input - 150 540 - 675 - 735 A
C
I
input
capacitance
- 3.5 - pF
Table 6. Static characteristics continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
10. Dynamic characteristics

Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 10.
For type 74HC574
t
pd
propagation
delay
CP to Qn; see Figure 7
[1]
V
CC
= 2.0 V - 47 150 - 190 - 225 ns
V
CC
= 4.5 V - 17 30 - 35 - 45 ns
V
CC
= 5 V; C
L
= 15 pF - 14 - - - - - ns
V
CC
= 6.0 V - 14 26 - 33 - 38 ns
t
en
enable time OE to Qn; see Figure 9
[2]
V
CC
= 2.0 V - 44 140 - 175 - 210 ns
V
CC
= 4.5 V - 16 28 - 35 - 42 ns
V
CC
= 6.0 V - 13 24 - 30 - 36 ns
t
dis
disable time OE to Qn; see Figure 9
[3]
V
CC
= 2.0 V - 39 125 - 155 - 190 ns
V
CC
= 4.5 V - 14 25 - 31 - 38 ns
V
CC
= 6.0 V - 11 21 - 26 - 32 ns
t
t
transition
time
Qn; see Figure 7
[4]
V
CC
= 2.0 V - 14 60 - 75 - 90 ns
V
CC
= 4.5 V - 5 12 - 15 - 18 ns
V
CC
= 6.0 V - 4 10 - 13 - 15 ns
t
W
pulse width CP HIGH or LOW;
see Figure 8
V
CC
= 2.0 V 80 14 - 100 - 120 - ns
V
CC
= 4.5 V 16 5 - 20 - 24 - ns
V
CC
= 6.0 V 14 4 - 17 - 20 - ns
t
su
set-up time Dn to CP; see Figure 8
V
CC
= 2.0 V 60 6 - 75 - 90 - ns
V
CC
= 4.5 V 12 2 - 15 - 18 - ns
V
CC
= 6.0 V 10 2 - 13 - 15 - ns
t
h
hold time Dn to CP; see Figure 8
V
CC
= 2.0 V 5 0 - 5 - 5 - ns
V
CC
= 4.5 V 5 0 - 5 - 5 - ns
V
CC
= 6.0 V 5 0 - 5 - 5 - ns
f
max
maximum
frequency
CP; see Figure 7
V
CC
= 2.0 V 6.0 37 - 4.8 - 4.0 - MHz
V
CC
= 4.5 V 30 112 - 24 - 20 - MHz
V
CC
= 5 V; C
L
= 15 pF - 123 - - - - - MHz
V
CC
= 6.0 V 35 133 - 28 - 24 - MHz
[1] t
pd
is the same as t
PLH
and t
PHL
.
[2] t
en
is the same as t
PZH
and t
PZL
.
[3] t
dis
is the same as t
PLZ
and t
PHZ
.
[4] t
t
is the same as t
THL
and t
TLH
.
[5] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
= C
PD
V
CC
2
f
i
N + (C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
C
PD
power
dissipation
capacitance
C
L
= 50 pF; f = 1 MHz;
V
I
= GND to V
CC
[5]
- 22 - - - - - pF
For type 74HCT574
t
pd
propagation
delay
CP to Qn; see Figure 7
[1]
V
CC
= 4.5 V - 18 33 - 41 - 50 ns
V
CC
= 5 V; C
L
= 15 pF - 15 - - - - - ns
t
en
enable time OE to Qn; see Figure 9
[2]
V
CC
= 4.5 V - 19 33 - 41 - 50 ns
t
dis
disable time OE to Qn; see Figure 9
[3]
V
CC
= 4.5 V - 16 28 - 35 - 42 ns
t
t
transition
time
Qn; see Figure 7
[4]
V
CC
= 4.5 V - 5 12 - 15 - 18 ns
t
W
pulse width CP HIGH or LOW;
see Figure 8
V
CC
= 4.5 V 16 7 - 20 - 24 - ns
t
su
set-up time Dn to CP; see Figure 8
V
CC
= 4.5 V 12 3 - 15 - 18 - ns
t
h
hold time Dn to CP; see Figure 8
V
CC
= 4.5 V 5 1 - 5 - 5 - ns
f
max
maximum
frequency
CP; see Figure 7
V
CC
= 4.5 V 30 69 - 24 - 20 - MHz
V
CC
= 5 V; C
L
= 15 pF - 76 - - - - - MHz
C
PD
power
dissipation
capacitance
C
L
= 50 pF; f = 1 MHz;
V
I
= GND to V
CC
[5]
- 25 - - - - - pF
Table 7. Dynamic characteristics continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 10.
11. Waveforms

Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 7. Propagation delay input (CP) to output (Qn), output transition time, clock input (CP) pulse width and the
maximum frequency (CP)
001aan292
CP input
1/f
max
t
W
t
THL
t
TLH
t
PHL
t
PLH
V
OH
V
I
GND
V
OL
V
M
V
M
10 %
90 %
Qn output
V
OL
and V
OH
Fig 8. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times
mna803
GND
GND
t
h
t
su
t
h
t
su
V
M
V
M
V
M
V
I
V
OH
V
OL
V
I
Qn output
CP input
Dn input

V
OL
and V
OH
Fig 9. Enable and disable times
001aah078
t
PLZ
t
PHZ
outputs
disabled
outputs
enabled
V
Y
V
X
outputs
enabled
Qn output
LOW-to-OFF
OFF-to-LOW
Qn output
HIGH-to-OFF
OFF-to-HIGH
OE input
V
I
V
OL
V
OH
V
CC
V
M
GND
GND
t
PZL
t
PZH
V
M
V
M
Table 8. Measurement points
Type Input Output
V
M
V
M
V
X
V
Y
74HC574 0.5V
CC
0.5V
CC
0.1V
CC
0.9V
CC
74HCT574 1.3 V 1.3 V 0.1V
CC
0.9V
CC

Test data is given in Table 9.
Definitions test circuit:
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
C
L
= Load capacitance including jig and probe capacitance.
R
L
= Load resistance.
S1 = Test selection switch.
Fig 10. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
V
I
V
O
R
T
R
L
S1
C
L
open
G
Table 9. Test data
Type Input Load S1 position
V
I
t
r
, t
f
C
L
R
L
t
PHL
, t
PLH
t
PZH
, t
PHZ
t
PZL
, t
PLZ
74HC574 V
CC
6 ns 15 pF, 50 pF 1 k open GND V
CC
74HCT574 3 V 6 ns 15 pF, 50 pF 1 k open GND V
CC
12. Package outline

Fig 11. Package outline SOT146-1 (DIP20)
UNIT
A
max.
1 2
b
1
c D E e M
H
L
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT146-1
99-12-27
03-02-13
A
min.
A
max.
b
Z
max.
w M
E
e
1
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
6.40
6.22
3.60
3.05
0.254 2.54 7.62
8.25
7.80
10.0
8.3
2 4.2 0.51 3.2
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
0.25
0.24
0.14
0.12
0.01 0.1 0.3
0.32
0.31
0.39
0.33
0.078 0.17 0.02 0.13
SC-603 MS-001
M
H
c
(e )
1
M
E
A
L
s
e
a
t
i
n
g

p
l
a
n
e
A
1
w M
b
1
e
D
A
2
Z
20
1
11
10
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
(1)
(1) (1)
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

Fig 12. Package outline SOT163-1 (SO20)
UNIT
A
max.
A
1
A
2
A
3
b
p
c D
(1)
E
(1) (1)
e H
E
L L
p
Q
Z
y w v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
1.27
10.65
10.00
1.1
1.0
0.9
0.4
8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT163-1
10
20
w M
b
p
detail X
Z
e
11
1
D
y
0.25
075E04 MS-013
pin 1 index
0.1
0.012
0.004
0.096
0.089
0.019
0.014
0.013
0.009
0.51
0.49
0.30
0.29
0.05
1.4
0.055
0.419
0.394
0.043
0.039
0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
0 5 10 mm
scale
X
A
A
1
A
2
H
E
L
p
Q
E
c
L
v M A
(A )
3
A
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
99-12-27
03-02-19

Fig 13. Package outline SOT339-1 (SSOP20)
UNIT A
1
A
2
A
3
b
p
c D
(1)
E
(1)
e H
E
L L
p
Q
(1)
Z y w v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
0.65
7.9
7.6
0.9
0.7
0.9
0.5
8
0
o
o
0.13 1.25 0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT339-1 MO-150
99-12-27
03-02-19
X
w M
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M A
(A )
3
A
1 10
20 11
y
0.25
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
A
max.
2

Fig 14. Package outline SOT360-1 (TSSOP20)
UNIT A
1
A
2
A
3
b
p
c D
(1)
E
(2) (1)
e H
E
L L
p
Q Z y w v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
0.65
6.6
6.2
0.4
0.3
0.5
0.2
8
0
o
o
0.13 0.1 0.2 1
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT360-1 MO-153
99-12-27
03-02-19
w M
b
p
D
Z
e
0.25
1 10
20 11
pin 1 index
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v M A
X
A
y
0 2.5 5 mm
scale
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
A
max.
1.1
13. Abbreviations

14. Revision history

Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT574 v.5 20120425 Product data sheet - 74HC_HCT574 v.4
Modifications: V
X
and V
Y
measurement points added to Table 8.
74HC_HCT574 v.4 20111219 Product data sheet - 74HC_HCT574 v.3
Modifications: Legal pages updated.
74HC_HCT574 v.3 20101215 Product data sheet - 74HC_HCT574_CNV v.2
74HC_HCT574_CNV v.2 19970827 Product specification - -
15. Legal information
15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term short data sheet is explained in section Definitions.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customers own
risk.
Applications Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customers sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customers applications and
products planned, as well as for the planned application and use of
customers third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customers applications or products, or the application or use by customers
third party customer(s). Customer is responsible for doing all necessary
testing for the customers applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customers third party
customer(s). NXP does not accept any liability in this respect.
Limiting values Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customers general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
Export control This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors specifications such use shall be solely at customers
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors
standard warranty and NXP Semiconductors product specifications.
Translations A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 April 2012
Document identifier: 74HC_HCT574
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section Legal information.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16 Contact information. . . . . . . . . . . . . . . . . . . . . 18
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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