STATE BOARD OF TECHNICAL EDUCATION &

TRAINING::AP, VIJAYAWADA

GOVT.POLYTECHNIC, ADONI

DIPLOMA IN ELECTRONICS & COMMUNICATION ENGG.

III SEMESTER
DIGITAL ELECTRONICS LAB (EC-308)

MANUAL (AS PER C-20 CURRICULUM)

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 LOGIC GATES

1. Objective of the Experiment: To verify the truth tables of AND, OR, NOT NAND, NOR, XOR Gates.

2. APPARATUS REQUIRED

i. Digital IC trainer kit

ii. ICs 74LS00, 74LS02, 74LS04, 74LS08, 74LS32, 74LS86
iii. Breadboard
iv. Connecting wires

3. Circuit Diagram:

Quad 2 input NAND gate(74LS00) Quad 2 input NOR gate(74LS02)

Quad 2 input NOT gate(74LS04) Quad 2 input AND gate(74LS08) Quad 2 input OR gate(74LS32)

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4. Theory
Logic gates are electronic circuits which perform logical functions on one or more inputs to produce one output. There
are seven logic gates. When all the input combinations of a logic gate are written in a series and their corresponding
outputs written along them, then this input/ output combination is called Truth Table. Various gates and their
working is explained here.
AND gate produces an output as 1, when all its inputs are 1; otherwise the output is 0. This gate can have minimum 2 inputs
but output is always one. Its output is 0 when any input is 0.
OR gate produces an output as 1, when any or all its inputs are 1; otherwise the output is 0. This gate can have minimum 2
inputs but output is always one. Its output is 0 when all input are 0.
NOT gate produces the complement of its input. This gate is also called an INVERTER. It always has one input and one output.
Its output is 0 when input is 1 and output is 1 when input is 0.
NAND gate is actually a series of AND gate with NOT gate its output is 1 when any or all inputs are 0, otherwise output is 1.
NOR gate is actually a series of OR gate with NOT gate. Its output is 0 when any or all inputs are 1, otherwise output
is 1.

5. Procedure
i. Connect the trainer kit to ac power supply.
ii. Place the IC ON breadboard
iii. Connect the inputs of any one logic gate to the logic sources and its output to the logic
indicator.
iv. Apply various input combinations and observe output for each one.
v. Verify the truth table for each input/ output combination.
vi. Repeat the process for all other logic gates.
vii. Switch off the ac power supply

6. Observations

AND gate OR gate

S.NO A INPUT B INPUT OUTPUT S.NO A INPUT B INPUT OUTPUT

1 0 1

2 0 1

3 1 0

4 1 1

NAND gate NOR gate

S.NO A INPUT B INPUT OUTPUT S.NO A INPUT B INPUT OUTPUT

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NOT gate

S.NO A INPUT OUTPUT

7. RESULT

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 REALISATION OF AND, OR and NOT GATES USING 2 INPUT NOR GATES

1. Objective of the Experiment: To implement basic gates using NOR gates and verify their truth tables.

2. Apparatus Required: Digital Logic Trainer, NOR Gate IC 7402, connecting wires.
3. Circuit diagram:

4. Theory
The basic logic gates AND, OR and NOT can be combined to realize any other logic circuit. The NOR gate is a
derived gate and is special since it is considered a universal gate. It is a NOT OR gate and the logic symbol is the OR
gate with an invert bubble on its output.

 To realize NOT Gate using NOR Gate both the inputs have been shorted since NOT Gate has only one input.
When binary HIGH signal (1) is given at the input, binary LOW (0) is the output and vice-versa.
 To realize OR Gate using NOR Gate, the output of NOR Gate is connected to NOT Gate.
 To realize AND Gate using NOR Gate, the inputs are complemented using 2 NOR gates
and their outputs are given as inputs to the other NOR gate.

5. Procedure:

a. Make the connections as shown in circuit diagram.

b. Feed the logic signal from the logic input switches.
c. Observe the logic outputs on the logic level LED indicators.
d. Observe the output for all possible input combinations.
e. Verify the corresponding truth table.

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6. OBSERVATIONS : AND gate
A B Y
S.No input input Output

OR gate A B Y
S.No input input Output

NOT Gate:

S.No A Y
input output

7. Results:

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 REALIZATION OF AND, OR, NOT USING 2 INPUT NAND GATE

1. Objective of the Experiment: To implement basic gates using only NAND gates and verify their truth
tables.

2. Apparatus Required: Digital Logic Trainer, NAND Gate IC 7400, connecting wires.

3. Circuit Diagram:

Pin diagram:

4. Theory:
NAND gate is actually a combination of two logic gates: AND gate followed by NOT gate. So its output is complement of the
output of an AND gate. This gate can have minimum two inputs, output is always one. By using only NAND gates, we can realize
all logic functions: AND, OR, NOT, X-OR, X-NOR, NOR. So this gate is also called universal gate.

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 5. Procedure
1. Make the connections as shown in the circuit diagram.
2. Feed the logic signal from the logic input switches.
3. Observe the logic outputs on the logic level LED indicators.
4. Observe the output for all possible input combinations.
5. Verify the corresponding truth table.

6. OBSERVATIONS:
AND Gate

S.No A input B input Y Output

OR Gate

S.No A input B input Y Output

NOT GATE

SL.NO A Input Y output

7.RESULT:

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 EX-OR GATE USING NAND AND NOR GATES

1. Objective of the experiment: To implement the EX-OR gate using NAND and NOR gates.
2. Apparatus required: 7400 IC, 7402 IC, Digital Trainer kit, Patch cards.
3. Circuit Diagram:

Pin diagrams:

NOR 7400 IC: Truth table:

A B Y=AB
0 0 1
0 1 1
1 0 1
1 1 0

NOR 7402 IC: Truth table:

A B Y=A+B
0 0 1
0 1 0
1 0 0
1 1 0

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4. Theory
1. The NAND or NOR Gates can be used to develop any one of the logic gates. It means that one can use only NAND
Gates or only NOR Gates to realize any basic gates. Hence these two gates are called as universal gates.
2. The NOT-AND operation is known as NAND operation. If all inputs are 1 then output produced is 0. NAND gate is
inverted AND gate. Y = 𝐴. ̅̅̅̅̅
𝐵
3. The NOT- OR operation is known as NOR operation. If all the inputs are 0 then the O/P is 1. NOR gate is inverted
OR gate. Y = 𝐴̅̅̅̅̅̅̅̅
+𝐵
4. The NOR gate has two or more input signals but only one output signal.
5. An EX-OR Gate is a gate with two or more inputs and one output. The output is logic 1 only when there are odd
number of 1’s at the input. Y=𝐴̅𝐵 + 𝐴𝐵̅
5. Procedure:
i. Take the digital trainer kit and insert the 7400IC at appropriate position on bread
board.
ii. Connect pin 14 to vcc and pin 7 to ground.
iii. Connect the circuit diagram as shown in figure.
iv. Switch on the trainer kit.
v. Apply various input combinations and observe output for each one.
vi. Verify the truth table of EX-OR gate.
vii. Insert the 7402 IC at appropriate position.
viii. Connect pin 14 to vcc and pin 7 to ground.
ix. Connect the circuit diagram as shown in figure.
x. Switch on the trainer kit.
xi. Apply various input combinations and observe output for each one.
xii. Verify the truth table of EX-OR gate.

6. OBSERVATIONS:
EX-OR Gate using only NAND gates

S.No A input B input Y Output

EX-OR Gate using only NOR gates

S.No A input B input Y Output

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7. Result:

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 HALF ADDER AND FULL ADDER

1. Objective of the experiment: To design and construct the half adder, full adder and verify truth table using logic
gates.

2. Apparatus required: i. Digital IC Trainer Board

ii. Patch chords/connecting wires
iii. IC7408
iv. IC7486
v. IC7432
3. Circuit diagrams:

4. Theory:
1. A Half adder can add two bits at a time.
2. Its outputs are SUM and CARRY.
3. For two bit addition- SUM will be 1, if only one input is 1(X-OR operation).
4. CARRY will be one, when both inputs are 1 (AND operation).
5. So, by using one AND gate and one X-OR gate, a half adder circuit can be constructed.
SUM = 𝐴̅𝐵 + 𝐴𝐵̅
CARRY = AB
5. Procedure:

a. Connect the trainer kit to ac power supply.

b. Connect logic sources to the inputs of the adder.
c. Connect output from SUM and CARRY to logic indicators.
d. Apply various input combinations to the adder.
e. Observe the SUM and CARRY outputs, verify the truth table for each input/ output
combination.
f. Switch off the ac power supply.

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6. OBSERVATIONS:

Half adder

Input Output
A B Sum Carry

Full adder

Input Output
A B C Sum Carry

7. Result:

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 4-Bit MAGNITUDE COMPARATOR

1.Objective of the experiment: To verify the function of 4 bit magnitude comparator(IC 7485).

2. Apparatus required: i. Digital IC Trainer Board

ii. Patch chords/connecting wires
iii. IC7485
3. Circuit diagrams:

4. THEORY:
A digital comparator or magnitude comparator is a hardware electronic device that takes two numbers as input in
binary form and determines whether one number is greater than, less than or equal to the other number.
The 4-bit magnitude comparators perform comparison of straight binary or BCD codes. The two 4- bit numbers are
A=A3A2A1A0 and B3B2B1B0 where A3 and B3 are the most significant bits. Three fully-decoded decisions about two, 4-
bit words (A, B) are made and are externally available at three outputs, one each for equality (A=B), greater than (A>B) and
less than (A<B).
The 4-bit comparator is mostly available in IC form and common type of this IC is 7485. These devices are fully
expandable to any number of bits without external gates. Words of greater length may be compared by connecting
comparators in cascade. The A > B, A < B, and A = B outputs of a stage handling less-significant bits are connected to the
corresponding inputs of the next stage handling more-significant bits. The stage handling the least significant bits must have a
high-level voltage applied to the A = B input.
5.PROCEDURE:

a. Connections are made as per pin diagram

b. Connect Vcc and ground pins of IC at 5V and ground points respectively
c. Connect the inputs A0 B0 A1B1 A2 B2 A3 B3 to the concerned inputs
d. Connect the outputs to LEDs
e. Switch ON the power supply
f. Apply inputs and observe the outputs by supporting of truth table

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6. OBSERVATIONS:

7.RESULT:

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 MULTIPLEXER

1. Objective of the Experiment : To verify truth table of Multiplexer using IC 74153

2. Apparatus Required : Digital Trainer Board,

Patch chords,

IC 74153

3. Block Diagram/ Circuit Diagram:

4. Theory:
1. The multiplexer, shortened to “MUX” or “MPX”, is a combinational logic circuit designed to switch one of several
input lines through to a single common output line by the application of a control signal.
2. Multiplexers are also known as data selectors because they can “select” each input data line.
3. The selection of each input line in a multiplexer is controlled by an additional set of inputs called Select lines.
4. A multiplexer has an even number of 2n data input lines where n is number of “select” inputs
5. Procedure:

i. Fix the IC on the bread board.

ii. Make connection according to the circuit.
iii. Connect select lines and data input lines to toggle switches (either channel A or B).
iv. Connect +5V (Vcc) supply at pin no 16 & GND at pin no 8.
v. Apply various combinations of input according to truth table.
vi. For all input combinations observe the outputs and verify with the truth table.

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6. OBSERVATIONS :
Truth Table:

Selection
Enable Data Input Lines Output
Lines
EA I0A I1A I2A I3A S1 S0 ZA

7. RESULT:

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 BCD TO 7 SEGMENT DECODER7448 IC

1. OBJECTIVE OF THE EXPERIMENT: To verify the truth table of BCD to Seven Segment Decoder.

2. APPARATUS REQUIRED: i) IC 7448

ii) Seven Segment Display,
iii) IKΩ Resistor,
iv) Digital trainer kit,
v) Power supply,
vi) Connecting wires.

3. CIRCUIT DIAGRAM:
IC 7448 DIAGRAM:

4. THEORY:
A Digital Decoder IC, is a device which converts one digital format into another and one of the most commonly
used devices for doing this is called the Binary Coded Decimal (BCD) to 7-Segment Display Decoder.
Typically 7 segment decoder consist of seven individual colored LED’s (called the segments),within one single display
package. In order to produce the required numbers or HEX characters from 0 to 9 and A to F respectively, on the
display the correct combination of LED segments need to be illuminated and BCD to 7-segment Display
Decoders such as the 74LS48.
A standard 7-segment LED display generally has 8 input connections, one for each LED segment and one that acts as
a common terminal or connection for all the internal display segments. Some single displays have also have an
additional input pin to display a decimal point in their lower right or left hand corner.
In electronics there are two important types of 7-segment LED digital display.
1. THE COMMON CATHODE DISPLAY (CCD) – In the common cathode display, all the cathode connections of the
LED’s are joined together to logic “0” or ground. The individual segments are illuminated by application of a “HIGH”,
logic “1” signal to the individual Anode terminals.

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2. THE COMMON ANODE DISPLAY (CAD) – In the common anode display, all the anode connections of the LED’s are
joined together to logic “1” and the individual segments are illuminated by connecting the individual Cathode
terminals to a “LOW”, logic “0” signal.

5. PROCEDURE:

a. Connect 5V and ground to their indicated position on digital trainer kit.

b. Connect BCD inputs A, B, C, D to the pin of IC 74LS48 as shown in logic diagram

c. Connect +5V to Pins 3, 4, 5 of IC 74LS48.

d. Connect pins 13-a, 12-b, 11-c, 10-d, 9-e, 15-f, 14-g of common anode display

respectively.

e. Switch on the power supply.

f. Observe decimal output on common anode display given on the experiment board.

6. OBSERVAITIONS:
TRUTH TABLE:

BCD INPUTS SEGMENT OUTPUTS

DISPLAY
A B C D a b c d e f g

7. RESULTS:

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 IC 74138 DECODER

1. Objective of the Experiment: To Verify the Truth table of IC 74138 Decoder

2. Apparatus Required : IC 74138 ,Digital Trainer Kit with Bread board, Patch card

3. Circuit diagram/Pin Diagram:

4. Theory:
The 74138 circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very
short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of
system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and
the enable time of the memory are usually less than the typical access time of the memory. This means that the effective
system delay introduced by the decoder is negligible.

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5. Procedure:
a. Connections are made as per the logic circuits.
b. Connect VCC and GND (ground) pins of ICs at +5V and ground points of IC Trainer Kit respectively.
c. Connect inputs A, B, C on the IC trainer kit.
d. Connect enable inputs G1, G2A, G2B on the IC trainer kit.
e. Connect the outputs Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 to output LEDs.
f. Switch ON the power supply.
g. Apply G1 is logic High and G2A and G2B are logic low
h. Apply different combination of inputs and observe the outputs.

6. OBSERVATIONS
Truth Table:

Inputs Outputs

G1 G2A G2B A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

7. Results:

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 ENCODER USING IC 74148

1. Objective of the experiment : To verify the function of Encoder using IC 74148 with truth table
2. Apparatus required : IC 74148, Digital Trainer kit, Bread board, Patch cords, power supply
3. Circuit diagram/block diagram :

4. Theory
i. An encoder is a combinational digital logic circuit.
ii. A digital encoder has commonly called as a binary encoder.
iii. It accepts an active level on one of its input represents a digit (decimal or octal) and converts into a coded
output
(binary or BCD).
iv. These encoders is used as a code converters.
v. Encoder has a 2n inputs and n outputs.
5. Procedure:
i. Take the digital trainer kit and insert the 74148IC at appropriate position.
ii. Connect pin no 16 to vcc and pin no 8 to ground.
iii. Connect the circuit diagram as shown in figure.
iv. Switch on the trainer kit.
v. The octal inputs are given at the corresponding pins.
vi. The outputs are verified at the corresponding output pins.

6. Truth Table:

INPUTS OUTPUTS
EI 0 1 2 3 4 5 6 7 A2 A1 A0

7. Results:

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SBTET-AP
 Construct a clocked SR Flip Flop using NAND gates

1. Objective of the experiment: To Design a clocked RS flip flop using NAND gates and Verify its truth table.

2. Apparatus required: 7400 IC, Digital trainer kit, patch cards

3. Circuit diagram/Block diagram:

Fig: 1 Clocked RS flip-flop using NAND gates

4. Theory
i. There are two inputs to the flip-flop defined as R and S.
ii. When inputs R = 0 and S = 0 then O/P remains unchanged.
iii. When inputs R = 0 and S = 1 the flip-flop is switches to the stable state where O/P is 1 i.e. SET.
iv. The input condition is R = 1 and S = 0 the flip-flop is switched to the stable state where output is 0 i.e. RESET.
v. The input condition is R = 1 and S = 1 the flip-flop is switched to the stable state where output is FORBIDDEN

4. Truth table of RS Flip-flop:

INPUTS OUTPUT STATE
CLK S R Q Q
X 0 0 NC NC NO CHANGE
0 1 0 1 RESET
1 0 1 0 SET
1 1 - - FORBIDDEN

5. Procedure:
13. Take the digital trainer kit and insert the 7400IC at appropriate position.
14. Connect pin 14 to vcc and pin 7 to ground.
15. Connect the circuit diagram as shown in figure
16. Give the clock input from pulser,
17. Switch on the trainer kit,
18. Apply various input combinations and observe output for each one.
19. Verify the truth table of RS Flip-flop.

6. Results:
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7. Discussion on result:

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 8. Scheme of evaluation:

WEIGHTAGE WITH MARKS

CATEGORY OF SUBTASK COMPETENCY LEVEL AWARDED
SKILL INDIVIDUALLY

A. Identification of
1. Handling of apparatus IC’s
B. Identification of pins 5
of IC’s
C. Identification of
components in the
trainer kit.
A. Circuit connections
2. Manipulation of B. Handling of
apparatus apparatus 20
C. Testing of IC’s
A. By applying inputs
to the circuit and
observe the outputs 20
3. Precise B. Verifying truth
operations/activities tables
C. Simplify the
expressions

A. Co operation
B. Co-Ordination
4. Values C. Communication 5
D. Sharing
E. Leadership

Total
50

Signature of the staff Signature of the student

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3.8(b) JK FLIP FLOP

WORK SHEET

Name of the student: Date of experiment:

PIN: Branch:
Institution: Experiment No:

1. Title of the Experiment:

2. Objective of the Experiment:

3. Apparatus Required:

4. Circuit diagram:

5. Procedure:

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 6. Readings.
S.No Clock Preset Clear Switch condition LED 1 Status LED 2 Status
input (For J and K inputs) (For Q Output) (For Output)

Interpretation of above Observations in terms of logic values.

S.No Clock Preset Clear Switch condition LED 1 Status LED 2 Status
input (For J and K inputs) (For Q Output) (For Output)

7. Results:

8. Discussion on Results:

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9. Scheme of Evaluation
Category Sub task Weightage with Total
of Skill Competency level
Individually
1.Handling of A. Identifying components
apparatus B. Identifying the PINs of ICs
C. Identifying the connection 5
points on the kit
2.Manipulation A. Handling ICs
of apparatus B. Testing ICs
C. Connecting the circuit 20

3.Precise A. Applying proper logic input

activities signals
B. Observing logic output and 20
interpreting its logic level.
4.Values A. Co-operation
B. Co-ordination
C. Communication 5
D. Sharing
E. Leadership
Total
50

Signature of the staff Signature of the Student

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3.8(c) D AND T FLIP FLOPS

WORK SHEET

Name of the student: Date of experiment:

PIN: Branch:
Institution: Experiment No:

1. Title of the Experiment:

2. Objective of the Experiment:

3. Apparatus Required:

4. Circuit diagram:

5. Procedure:

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6. Readings.

S.No Clock input Switch condition LED 1 Status LED 2 Status

(For D input) (For Q Output) (For Output)
1
2
3

Interpretation of above Observations in terms of logic values.

S.No Clock input D Q

input Output Output
1
2
3

S.No Clock input Switch condition LED 1 Status LED 2 Status

(For T input) (For Q Output) (For Output)
1
2
3

Interpretation of above Observations in terms of logic values.

S.No Clock input T Q

input Output Output
1
2
3

7. Results:

8. Discussion on Results:

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9. Scheme of Evaluation

Category Sub task Weightage with Total

of Skill Competency level
Individually
1.Handling of A. Identifying components
apparatus B. Identifying the PINs of ICs
C. Identifying the connection 5
points on the kit
2.Manipulation A. Handling ICs
of apparatus B. Testing ICs
C. Connecting the circuit 20

3.Precise A. Applying proper logic input

activities signals
B. Observing logic output and 20
interpreting its logic level.
4.Values A. Co-operation
B. Co-ordination
C. Communication 5
D. Sharing
E. Leadership

Total
50

Signature of the staff Signature of the Student

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 Work Sheet Ripple counter

WORK SHEET

Name of the Student: Date of Experiment:

PIN : Branch:
Experiment No:
Institution :

1. Title of the Experiment :

2. Objective of the Experiment:

3. Apparatus Required :

4. Pin Diagram:

5. Logic diagram and waveforms:

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5. Procedure:

6. Truth Table:

clk Q0 Q1 Q2 Q3

7. Results:

8. Discussion on Results:

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9. Scheme of Evaluation:

Sub Task Weightage With

Category of Skill Competency Level Marks Awarded
Individually
A. Identifying the
components in the trainer
1.Handling of kit 5
Apparatus B. Identifying the Pin
configuration of IC
C. Checking the IC
A. Drawing the Logic circuit
2.Manipulation of B. Connecting the Logic
Apparatus circuit 15
C. Applying the clock pulse
A. Observing the output
3.Precision after applying each pulse
Operation Activities B. Obtain the timing 25
waveforms
A. Co operation
B. Co-ordination
4.Values C. Communication 5
D. Sharing
E. Leadership
Total 50

Signature of staff Signature of student

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 WORKSHEET DECADE COUNTER

WORK SHEET

Name of the student: Date of experiment:

PIN: Branch:

Institution: Experiment No:

1. Title of the Experiment:

2. Objective of the Experiment:

3. Apparatus Required:

4. Circuit Diagram:

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5. Procedure

6. Readings:

COUNT TRUTH TABLE:

Inputs Outputs
R1 R2 S1 S2 Q QC Q B QA
H H L X L L L L
H H X L L L L L
X X H H H L L H
X L X L COUNT
L X L X COUNT
L X X L COUNT
X L L X COUNT

COUNT QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0

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 7. Inference and Interpretation:

8. Scheme of Evaluation:

Category of Skill Sub task Weightage with Total

Competency level
Individually
A. Identifying Decade Counter IC
B. Identifying the pins of ICs 5
1.Handling of C. Testing IC whether it is Good or Bad
apparatus D. Inserting the IC on Breadboard of Trainer
Selecting the required patch cords & wires
A. Drawing the Circuit Diagram
B. Making the Connections as per circuit
2.Manipulation of diagram 20
apparatus C. keeping all the data inputs to low
D. Switching ON the Power Supply
E. Varying the inputs to HIGH or LOW as
required.
3.Precise activities A. Applying proper logic input signals
B. Observing logic output and interpreting
logic level. 20
C. Noting the Logic outputs for corresponding
Inputs
A. Co-operation
B. Co-ordination
4.Values C. Communication 5
D. Sharing
E. Leadership
Total
50
Signature of the Staff Signature
of the Student

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WORK SHEET UP/DOWN COUNTER

WORK SHEET

Name of the student : Date of experiment:

PIN : Branch:

Experiment No.
Institution:

1. Title of the Experiment:

2. Objective of the Experiment:

3. Apparatus Required :

4. Pin Diagram & Pin Description:

5. Procedure:

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6. Readings :
Count-UP Mode:
Clock
Q3 Q2 Q1 Q0
pulse
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

Count-Down mode:

Clock
Q3 Q2 Q1 Q0
pulse
0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 1 0 0 0
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0

7. Inference and Interpretation:

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8. Scheme of Evaluation:

CATEGORY SUB TASK WEIGHTAG MARKS

OF SKILL E WITH AWARDE
COMPETEN D
CY LEVEL
INDIVIDUA
LLY
1.Handling of A. Identifying the various ICs
Apparatus B. Identifying the pins of ICs
C. Selecting the correct ICs for 5
various functions
D. Identifying the connection
points on the kit
E. Testing of IC working
condition

2.Manipulation A. Making the connections as per

of Apparatus the circuit diagram
B. Connect the inputs to correct 20
pins of ICs
C. Checking the connections
D. Keeping all the inputs low
E. Varying the inputs HIGH or
LOW as required

3.Precise A. Applying the proper logic input

operations/Acti signals
vities B. Observing the outputs for 20
different inputs
C. Interpret the logic levels for
output corresponding Inputs
4.Values a) Co-operation
b) Co-Ordination
c) Communication 5
d) Sharing
Total 50

Signature of the Staff Signature of the Student

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 WORK SHEET 3.12 SHIFT REGISTER

3.18

Name of the student : Date of experiment:

PIN : Branch:

Experiment No:
Institution:

TITLE OF THE EXPERIMENT:

OBJECTIVE OF THE EXPERIMENT:

APPARATUS REQUIRED:

CIRCUIT DIAGRAM:

SBTET-AP
 PROCEDURE:

TRUTH TABLE:

3.18.18 RESULT:

DISCUSSION ON RESULT:

SBTET-AP
 SCHEME OF EVALUATION:

WEIGHTAGE WITH
CATEGORY OF SKILL SUB TASK COMPETENCY LEVEL TOTAL
INDIVIDUALLY
A. Identify the major parts in the
1.HANDLING OF kit.(like LEDs, switches, Clock)
APPARATUS B. Identify the input and output
pins of IC 5
A. Read IC pin diagram
2.MANIPULATION B. Apparatus handling
OF APPARATUS C. Observations 20
A. IC connections for different
3.PRECISE modes(SISO,SIPO,PISO,PI
OPERTAIONS / PO) of shift register
ACTIVITIES B. Tabulation of values of 20
truth table
A. Cooperation
B. Coordination
4.VALUES C. Communication
5
D. Sharing
E. Leadership
TOTAL
50

Signature of staff Signature of student

SBTET-AP
3.13(a) WORKSHEET SIMULATION OF AND, OR, NOT and EXOR USING NAND GATE

WORK SHEET

Name of the student: Date of experiment:

PIN: Branch:

Institution: Experiment No:

1. Title of the Experiment:

2. Objective of the Experiment:

3. Apparatus Required:

4. Circuit Diagram:

SBTET-AP
5. Procedure

6. Readings:

AND Gate

S.No A input B input Y Output

OR Gate

S.No A input B input Y Output

NOT GATE

SL.NO A Input Y output

SBTET-AP
EXOR GATE

S.No A input B input Y Output

7. Inference and Interpretation:

SBTET-AP
 8. Scheme of Evaluation:

Category of Sub task Weightage with Total

Skill Competency level
Individually
A. Knowing how to invoke ORCAD PSPICE
application S/W 5
1.Handling of B. Opening a new project
apparatus C. Selecting proper project for digital simulation
D. Naming the project and finding the location
to save the project
E. Adding the required libraries to simulate the
project
A. Adding the required parts, input and output
ports to the work space
2.Manipulation B. Wiring the circuit as per the circuit diagram 20
of apparatus C. Apply PSPICE stimulus to all input ports as
the truth table
D. Creating the new simulation profile to the
project

3.Precise A. Running the project and adding input and

activities/operati output traces to the simulation graph
ons B. Observing the output waveforms 20
C. Interpreting the simulation results with truth
tables
D. Repeating same simulation with selection of
proper time periods and ON time of inputs
such that the output is clearly understood
A. Co-operation
B. Co-ordination
4.Values C. Communication 5
D. Sharing
E. Leadership

Signature of the staff Signature of the student

SBTET-AP
3.13(b) WORKSHEET SIMULATION OF AND, OR, NOT and EXOR USING NOR GATE

WORK SHEET

Name of the student: Date of experiment:

PIN: Branch:

Institution: Experiment No:

1. Title of the Experiment:

2. Objective of the Experiment:

3. Apparatus Required:

4. Circuit Diagram:

SBTET-AP
5. Procedure

6. Readings:

AND Gate

S.No A input B input Y Output

OR Gate

S.No A input B input Y Output

NOT GATE

SL.NO A Input Y output

SBTET-AP
EXOR GATE

S.No A input B input Y Output

7. Inference and Interpretation:

SBTET-AP
 8. Scheme of Evaluation:

Weightage with
Category of
Sub task Competency level Total
Skill
Individually
 Knowing how to invoke ORCAD Pspice
application S/W 5
 Opening a new project
 Selecting proper project for digital
1.Handling of
simulation
apparatus
 Naming the project and finding the
location to save the project
 Adding the required libraries to simulate
the project

A. Adding the required parts, input and output

ports to the work space
2.Manipulation B. Wiring the circuit as per the circuit diagram 20
of apparatus C. Apply Pspice stimulus to all input ports as the
truth table
D. Creating the new simulation profile to the
project
A. Running the project and adding input and
output traces to the simulation graph
3.Precise B. Observing the output waveforms 20
activities/ C. Interpreting the simulation results with truth
operations tables
D. Repeating same simulation with selection of
proper time periods and ON time of inputs
such that the output is clearly understood
A. Co-operation
B. Co-ordination
4.Values C. Communication 5
D. Sharing
E. Leadership

Signature of the staff Signature of the student

SBTET-AP
 WORK SHEET HALF ADDER AND FULL ADDER USING SIMULATION USING PSPICE

WORK SHEET

Name of the student: Date of experiment:

PIN: Branch:

Institution: Experiment No:

1. Title of the Experiment:

2. Objective of the Experiment:

3. Apparatus Required:

4. Circuit Diagrams:

Half adder :

Full adder :

SBTET-AP
5. Procedure

6. Truth table:

Half adder:

Input Output

A B Sum Carry

Full adder:

Input Output
A B C Sum Carry

7. Inference and Interpretation:

SBTET-AP
 8. Scheme of Evaluation:

Category of Sub task Weightage with Total

Skill Competency level
Individually
A. Knowing how to invoke ORCAD Pspice
application S/W 5
1.Handling of B. Opening project and saving the project in
software appropriate location.
C. Selecting proper project for digital
simulation.
D. Adding the relevant libraries to simulate the
project

A. Adding the required parts,input and output

ports in the workspace.
2.Manipulation B. Wiring the circuit as per the circuit diagram. 20
of software C. Customising the label names of all the inputs
and ouputs of logic gates.
D. Creating the new simulation profile to the
project

3.Precise A. Running the project and adding input and

activities/operati output traces to the simulation graph
ons B. Observing the output waveforms 20
C. Interpreting the simulation results with truth
tables
D. Repeating same simulation with selection of
proper time periods and ON time of inputs
such that the output is clearly understood
A. Co-operation
B. Co-ordination
4.Values C. Communication 5
D. Sharing
E. Leadership

Signature of the staff Signature of the student

SBTET-AP
 WORKSHEET 3.15 SIMULATION OF MULTIPLEXER

WORK SHEET
Name of the student: Date of experiment:

PIN: Branch:

Institution: Experiment No:

1. Title of the Experiment:

2. Objective of the Experiment:

3. Apparatus Required:

4. Circuit Diagram:

SBTET-AP
5. Procedure

6. Readings:

MULTIPLEXER:

Selection
Enable Data Input Lines Output
Lines
EA I0A I1A I2A I3A S1 S0 ZA

7. Inference and Interpretation:

SBTET-AP
 8. Scheme of Evaluation:

Category of Sub task Weightage with Total

Skill Competency level
Individually
A. Knowing how to invoke ORCAD Pspice
application S/W 5
1.Handling of B. Opening a new project
apparatus C. Selecting proper project for digital simulation
D. Naming the project and finding the location
to save the project
E. Adding the required libraries to simulate the
project
A. Adding the required parts, input and output
ports to the work space
2.Manipulation B. Wiring the circuit as per the circuit diagram 20
of apparatus C. Apply Pspice stimulus to all input ports as the
truth table
D. Creating the new simulation profile to the
project

3.Precise A. Running the project and adding input and

activities/operati output traces to the simulation graph
ons B. Observing the output waveforms 20
C. Interpreting the simulation results with truth
tables
D. Repeating same simulation with selection of
proper time periods and ON time of inputs
such that the output is clearly understood
A. Co-operation
B. Co-ordination
4.Values C. Communication 5
D. Sharing
E. Leadership

Signature of the staff Signature of the student