Compensators for the Buck Converter:

Design and Analysis

Portland State University
Department of Electrical and Computer Engineering
Portland, Oregon, USA
December 30, 2009

Abstract
This paper discusses the design of a compensator for the buck DC switching
converter. Three dierent compensators are designed and analyzed based on
phase and gain margins. Op-amp implementations for each compensator are
derived and tested with an example converter. The performance of the converters is examined based on transient response and rejection of steady-state error
due to a step change in the input voltage.

Introduction
The buck converter is perhaps the simplest DC converter topology, yet one of
the most useful. It is widely used in industry, it is a clear and simple example
that is helpful in understanding the principles of switching converters, and it can
be used to derive more complicated topologies. In light of this general usefulness,
it is instructive to consider how one can use control systems to regulate the
operation of such a converter. This serves not only to illustrate how switching
converters can be controlled, but also results in a practical circuit for use in
power supplies, voltage regulators, and so forth.
Since it is desirable to design an eective compensator for the buck converter,
this paper will consider the various properties of three dierent compensation
schemes. The rst section will present a basic discussion of the buck converter,
its open-loop and uncompensated closed-loop behavior, and introduce an example converter that will be used for all the designs. The next section will present
a basic attempt to counteract some of the undesirable properties of the buck
converter with a proportional-integral compensator. The third section will detail a somewhat more sophisticated attempt to improve performance by use of
a lead compensator. The last compensator discussed will be the combination of
the lead and proportional-integral compensators to obtain the benets of both.
1

Each section will present the design of the compensator for the example converter given in the rst section, derive an op-amp circuit to implement it, and
evaluate the performance of the compensated system through simulation. The
conclusion will summarize the results and compare the various designs.

The Uncompensated Buck Converter

The basic buck converter topology is shown in Figure 1. The function of
this converter is transform a higher input DC voltage, , into a lower output
DC voltage, . The conversion ratio, in steady-state, is = , where
is the duty ratio of the switch. Thus, the output voltage is determined
by both the input voltage and the switching duty cycle. In addition, nonideal eects, most notably the discontinuous conduction mode, make the output
voltage dependent on the load current. For this paper, however, the controlled
variable is considered to be the duty cycle, with variations in the input voltage
considered to be disturbances, and the load current assumed to be constant, with
the converter operating in the continuous conduction mode. The response of a
buck converter operating in steady-state to a step change in the input voltage
is shown in Figure 2. In open-loop, the converter exhibits large overshoot, large
steady-state error, and excessive oscillations.

Figure 1: The ideal buck converter

Reference [1], Chapter 8 gives the small-signal averaged transfer function for
the operation of the buck converter in the continuous conduction mode. This
is the model that will be used in the following analysis. The model basically
consists of two transfer functions, one which models the inuence of the duty
cycle on the output, (), and one which models the inuence of the input
voltage on the output, (). For the purposes of this paper, the rst will be
considered the control input, while the second is a source of disturbances. The
general forms of the these transfer functions are the same.
0

() =
1+

)2 and

(1)

Figure 2: Response of open-loop buck converter to input voltage step

0

() =
1+

)2 ,

where
0 = , 0

1
= , 0 =
,

(2)

and =

To correct the undesirable behavior demonstrated in response to a change in

the input voltage, the buck converter can be placed in a control loop, as shown
in Figure 3, where () is the gain of the output sensor, () is the transfer
function of the compensator, and the 1 factor is the transfer function of the
pulse-width modulator used to drive the transistor that implements the ideal
switch shown above. Usually, () and 1 will be simple gains. One method
in classical control theory to analyze systems and design controllers, and the
method that will be used here, is by using the loop gain. For the control loop
shown in Figure 3, the loop gain is
() =

() ()()

(3)

This paper will use an example converter to illustrate the design and eectiveness of the various compensators. Namely, the converter will have an input
3

Figure 3: Buck converter control loop

voltage = 28 V, an output voltage = 15 V, and a load of = 3 . The
capacitor and the inductor values will be = 500 F and = 50 H, respectively. The peak-to-peak amplitude, , of the sawtooth driving the modulator
will be 4 V, the sensor gain will be = 13 and the switching frequency = 100
kHz. The designs will be evaluated based on their gain and phase margins, and
on how the converter responds to a input voltage step from 28 V to 40 V and
back to 28 V. To have a basis of comparison for the compensated converter, the
behavior of the buck in an uncompensated conguration must be examined.
Using the control-to-output transfer function given earlier, these values can
be used to derive a more concrete expression for the loop gain. Since the loop
is as yet uncompensated, () = 1.
(
)
() ()()

0
() =
=
( )2

1 +
+
0
0
As can be seen, the uncompensated loop gain of the buck converter is a standard
second-order system of the form

() =
1+

where

)2 ,

0
28
=
= 2.33

(3) (4)

1
1
0 =
=
= 2000 10 rad/s 0 = 1 kHz, and

(50 ) (500 )
=

(4)

=3

500
= 3 10 = 9.49 19.5 dB
50

A Bode plot of this loop gain is shown in Figure 4. The phase margin can
be determined directly from the plot. In the asymptotic approximation, the
closed-loop buck converter has a phase margin of 0 . Since the phase asymptote
reaches but does not cross 180 , the gain margin can be said to be innite.
Thus, without any compensator, the buck converter has an innite gain margin
but a 0 phase margin. Such a system is stable but will exhibit oscillations
and other behavior that is generally considered undesirable. A plot of the step
response of the converter in this conguration is shown in Figure 5. As can be
seen, the oscillations in the output voltage present in the open-loop case are still
present, though reduced in amplitude by the application of feedback, and there
is still a steady-state error to a change in input voltage. Both of these issues
will be addressed in the compensator designs that follow.

Proportional-Integral Compensation
A simple but fairly eective way to improve the characteristics of the buck
converter is to use a dominant-pole or integral compensator. This is simply a
compensator with a single pole at = 0 and a gain.
() =

(5)

Although the plain integral compensator could be used for this purpose, it
is dicult to obtain good performance using this type of compensator. It is
more usual to use a proportional-integral or PI compensator, as discussed in
Chapter 7 of [2] This is essentially the same as the integral compensator, but
with a zero introduced at some higher frequency. The transfer function of the
PI compensator is
(
)
0 1 +
() =
(6)

As can be seen from the plot in Figure 6, this compensator provides a high gain
at low frequencies, which falls o at 20 dB per decade and then levels out at
the zero frequency, . The phase is initially 90 , which increases by a rate of
45 per decade starting at 10 to a maximum of 0 at 10 . The benet obtained
by using a PI compensator is that the large low-frequency gain will eliminate
steady-state error to step disturbances. In general, however, this cannot be
attained while still having acceptable gain and phase margins using a simple PI
compensator. The design shown here will concentrate on low-frequency gain at
the expense of gain and phase margins, although these are still a consideration.
The unity-gain crossover frequency should be placed before the major phase
0
= 100
downturn in the compensated loop. The design here will use = 10
and place the unity-gain crossover at this same frequency, to avoid too much
interaction in the phase responses while still providing higher gains.
5

Figure 4: Uncompensated loop gain

The loop gain of the buck converter with the PI compensator is shown in
Figure 7, which can be expressed as
() = 0 0 (
1+

1+

)2 )

(7)

Figure 5: Step response of uncompensated buck converter

Using the expressions given on the Bode plot, the value of 0 can be calculated.
To nd the low-frequency gain, one can simply use the gain expression at the
new crossover frequency.
0 0
= 0 dB = 1
2
0 0 = 2
2 (100 Hz)
2.33
0 = 270

0 =

Since only 0 and are needed to specify the compensator, the design is
complete. The phase margin of this design is the amount by which the phase
at the crossover frequency is above 180 . This can be found by evaluating the
gain asymptote at .
( )

= 180 + 45 log
0
(
)
100 Hz

= 180 + 45 log
1 kHz
= 135
This is actually a surprisingly high phase margin, which is only due to the
asymptotic approximation. Due to the Q of the original circuit, the gain will
7

Figure 6: PI compensator transfer function

rise above 0 dB and cross again after the phase downturn, so the actual phase
margin is close to 0 . The gain margin, as in the uncompensated case, is actually
innite, since the phase never actually crosses 180 , although the asymptote
reaches it. Thus, the PI compensated system has essentially the same gain and
phase margins as the uncompensated system, and will show similarly undesirable
transient characteristics. The presence of higher low-frequency gain, however,

Figure 7: Loop gain with PI compensator

will eliminate the steady-state error seen in the uncompensated case.
To be able to simulate the behavior of the compensated buck converter, a
control circuit must be derived to implement the PI compensator. Such a circuit

is shown in Figure 8. This circuit implements the transfer function

(
)
2 2 + 1
() =
1
2

(8)

In this circuit, the second resistor and the capacitor set the zero frequency,
while the rst resistor in combination with these values sets the gain of the
compensator. If a value of 2 = 100 k is assumed, then the capacitor value
must be
1
1
2 (100 Hz) =
=
2
(100 k)
1
=
= 15 nF
2 (100 Hz) (100 k)
Likewise, the value of 1 to set the gain to the proper value can be found from
this value for C.
1
1
270 =
0 =
1
1 (15 nF)
1
1 = 240 k
1 =
270 (15 nF)
The reference voltage on the non-inverting input of the opamp for this circuit
can be simply 5 V, since there is no direct connection to the output.

Figure 8: Op-amp circuit implementation of PI compensator

The simulated response of the buck with this PI compensator to a step disturbance is shown in Figure 9. As would be expected from the phase margin,
the system displays large oscillations in the output voltage, although not nearly
as large as those of the open-loop converter. The presence of the pole at = 0,
however, which is the main purpose of using such a compensator, is quite effective in removing steady-state error. Thus, although some of the transient
characteristics are undesirable, the PI compensator is eective in regulating the
output to the proper voltage. A method to improve the transient characteristics
is examined in the design of the next compensator.
10

Figure 9: Step response of PI-compensated buck converter

Lead Compensation
A more sophisticated way to improve the performance of the buck converter
is with a lead compensator. The transfer function of this compensator is
)
(
1 +
) ,
() = 0 (
(9)
1 +
where < . As can be seen from the plot of the transfer function shown in
Figure 10, the lead compensator provides both a phase boost that is adjustable
based on the pole and zero frequencies, and a gain boost at higher frequencies
that will result in a higher crossover frequency for the lead-compensated buck
converter. Since the one of the most undesirable features of the uncompensated
buck is its low phase margin, the phase boost should be chosen to improve
the phase margin to an acceptable value. The new crossover frequency can be
chosen arbitrarily. The design shown here will be to obtain a 45 phase margin
and a crossover frequency of 5 kHz for the loop gain with a lead compensator.

11

Figure 10: Lead compensator transfer function

When the compensator is placed in the loop, the loop gain of the buck converter system becomes
(
)
1 +
() = 0 0 (
(10)
)(
( )2 )

1 +
1 +
+
0
0

12

Figure 11: Loop gain with lead compensator

The asymptotic Bode plot of this loop gain is shown in Figure 11. The expressions shown can be used to place the pole and zero frequencies of the compensator to obtain the desired phase margin and unity-gain crossover. As can be
seen, the phase margin of the system is equal to the phase of the lead compen-

13

sator at the new crossover frequency, .

= Compensator phase at = 45 log

45 = 45 log

= 101

= 10
Also, will necessarily be the geometric mean of the pole and the zero frequency. Since the phase margin condition gives a relationship between the pole
and zero frequencies, this can be used to solve for both.

5 kHz = 102
5 kHz
=
10
= 1.58 kHz and = 15.8 kHz
These relationships result in the pole and zero frequencies for the lead compensator. To complete the design, the required low-frequency gain 0 of the
compensator to place the unity-gain point at the appropriate frequency must be
determined. This can be found by equating the values of the gain asymptotes
at .
( )2

0
0 0
=

Substituting the values of 0 and 0 for the example converter, and the values
of and as previously calculated, the gain 0 of the compensator is
0 =

0 =

1
2.33

1
0

)2

1.58 kHz
1 kHz

)2

5 kHz
1.58 kHz

0 = 3.4
The resulting compensated system has a phase margin of 45 , as designed for.
The gain margin can be found by evaluating the gain at the point the phase
crosses 180 . This occurs at 10 .
= Gain below 0 dB at 10

14

Gain =

(5 kHz)

5 kHz
=
=
2
2
100 (15.8 kHz)
(10 )
Gain = 0.00317 50 dB
= 50 dB

Since the general desirable gain margin for a stable system is 10 dB, this is quite
acceptable. In reality, since the phase only approaches 180 , the gain margin
of the system will actually be innite, as in the previous two cases. In any case,
this compensated system has very good phase and gain margins.
With all of the parameters of the lead compensator determined, what remains
is to implement the compensator using an op-amp circuit and simulate the
closed-loop converter to evaluate its performance. A general circuit that can
be used to implement any lead or lag compensator is shown in Figure 12. The
transfer function of this circuit is
)
(
2 1 1 + 1
(11)
() =
1 2 2 + 1
The resistor ratio sets the low frequency gain, and the two resistor-capacitor
pairs set the pole and zero frequencies. Two standard valued resistors that give
nearly the required gain are 1 = 100 k and 2 = 330 k. From these values,
the capacitor values to set the pole and zero can be calculated.
=

1
1
2 (1.58 kHz) =
1 1
(100 k) 1

1 =

1
1 = 1.0 nF
2 (1.58 kHz) (100 k)

1
1
2 (15.8 kHz) =
2 2
(330 k) 2

2 =

1
2 = 33 pF
2 (15.8 kHz) (330 k)

It it also necessary to derive a value for the reference voltage on the non-inverting
input of the op-amp. The sensed voltage from the output will be 5 V in steadystate as before, and the control voltage should be 2.14 V. Using these in combination with the resistor values for the lead compensator, the reference voltage
can be found.
2
1
=
+

1 + 2
1 + 2
=

330 k
100 k
(5 V) +
(2.14 V) = 4.33 V
100 k + 330 k
100 k + 330 k

15

Figure 12: Op-amp circuit implementation of lead compensator

Using these values in the PECS simulator, the response of the lead-compensated
buck converter to a step in the input voltage was simulated as before. The results of the simulation are shown in Figure 13. The lead compensator is quite
eective in increasing the phase margin of the system. The oscillatory behavior
evident in the output voltage of the uncompensated converter is not present,
and the magnitude of the steady-state error due to the step is reduced, though
not eliminated. Thus, the system with the lead compensator is very stable, but
will still exhibit steady-state errors to a step disturbance. To x this problem,
the system type number must be increased by adding a pole at = 0. This is
the approach taken in the design of the next and nal compensator.

Combined Lead and PI Compensation

Although both the PI compensator and the lead compensator were able to
improve some aspects of the buck converter, neither was able to completely
eliminate its undesirable properties. The lead compensator provided a good
transient response, but had a steady-state error to step disturbances, since the
compensated loop gain had a type number of 0. The PI compensator had a
type number of 1 and thus was able to eliminate steady-state error in response
to a step, but had undesirable transient characteristics. By combining the two
compensators, one can use the advantages of each to design a more eective
compensator. The transfer function for such a combined lead and PI compensator is
(
)(
)
0 1 + 1
1 + 2
(
)
() =
,
(12)
1 +
where 2 is the zero introduced by the lead compensator and thus 2 < .
Also, to separate the eects of the lead and PI portions of the compensator, it

16

Figure 13: Step response of lead-compensated buck converter

will be assumed here that 1 < 2 . An asymptotic Bode plot of the transfer
function of this compensator is shown in Figure 14. When 2 at a frequency
10 times or more greater than 1 , the design is separated into two essentially
independent pieces, the design of a PI compensator at low frequencies and the
design of a lead compensator at high frequencies.
A plot of the loop gain of the example converter with a combined lead and
PI compensator is shown in Figure 15. To determine the design, the two zeros
and the pole must be placed. For the phase response of the two compensator
portions to have no interaction, 1 must be two decades below 2 . For a faster
response, it would be good that 2 be as large as possible, but 2 should not
be too large. The value used here is 2 = 2 kHz, and thus 1 = 20 Hz. As
determined in the design of the lead compensator, to get a phase margin of 45 ,
= 102 , which means that = 20 kHz. With the pole and zeros placed,
the only factor that remains to determine is the gain. Since it is desirable to
have a large gain at low frequencies, the combined compensator will be designed
to have the gain factor 0 0 be 1000. This gives a value of
0 0 = 1000 0 =

17

1000
0 = 430
2.33

Figure 14: Lead and PI compensator transfer function

NextSection

The gain and phase margins can be found by evaluating the asymptotes at
the respective crossover frequencies. The unity-gain crossover frequency is =

18

Figure 15: Loop gain with lead and PI compensator

2 = 6.32 kHz. The phase at this frequency is given by

)
(
)
(
20 kHz

180 = 45 log
180 = 135
() = 45 log
2
2 kHz

The phase margin is thus

= 180 + () = 180 135 = 45
19

which is no surprise, since this is what was designed for. A gain margin value
could be calculated as before, using 10 as the 180 crossover frequency,
but as previously discussed, the actual gain margin will be innite. Thus, the
combined compensator has a 45 phase margin, an innite gain margin, and
a pole at = 0. This system should be very stable, exhibit good transient
response, and completely compensate for step disturbances with no steady-state
error.
The circuit implementation for the lead and PI compensator is simply a lead
circuit as shown in Figure 12 cascaded with a PI circuit as shown in Figure 8.
The same expressions given before can be used to nd the new component values.
The overall gain of the compensator must be 430. For simplicity, the gain of
the lead section will be set to 4.3 and the gain of the PI section set to 100. A
resistor pair that gives the required gain for the lead section is 1 = 27 k
and 2 = 120 k. Using these values, the capacitor values to place the pole
and the second zero are simply
2 =

1
1
2 (2 kHz) =
1 1
(27 k) 1

1 =
=

1
1 = 3.0 nF
(27 k) (22 kHz)

1
1
2 (20 kHz) =
2 2
(120 k) 2
1
2 = 68 pF
(120 k) (220 kHz)

2 =

The PI section must provide a gain of 100 and place 1 at 20 Hz. If 2

is assumed to be 100 k, then the values of the capacitor and the remaining
resistor can be found.
=

1
1
2 (20 Hz) =
2
(100 k)

1
= 82 nF
2 (20 Hz) (100 k)

0 =

1
1
100 =
1
1 (82 nF)

1 =

1
1 = 120 k
100 (82 nF)

These values can be used in PECS to simulate the response of the converter. A
reference voltage of 5 V can be used, as with the PI compensator.

20

The simulated response of the combined compensator to the same step disturbance is shown in Figure 16. The nature of the improvement is evident. Just
as with the PI compensator, the initial disturbance is fully compensated for and
the output voltage returns to the set-point value. This is due to the high-low
frequency gain, which tends to cause such disturbances to be rejected. As with
the lead compensator, the voltage transitions smoothly and with no oscillations,
since the phase margin of the system is within the acceptable range. By combining these benets, this circuit represents a fairly good method of controlling
the output of a buck converter

Figure 16: Step response of lead- and PI-compensated buck converter

Conclusion
This paper has discussed the design of three dierent compensators for the
buck switching converter, and evaluated their performance based on phase margins and the response to an input voltage step. The rst design was a PI
compensator, which provided good voltage regulation but poor transient performance. The second design was a lead compensator, which by increasing the
phase margin of the system yielded very good transient response, but which
still demonstrated a steady-state error to a step. By combining these two approaches, the nal lead and PI compensator provides an excellent regulator for
the buck converter, which keeps the output voltage at the set value despite large

21

changes in the input voltage. These results could be applied to the construction
of a practical compensator for an operating buck converter, or as an example of
how to design controllers for other switching converter topologies.

References
[1] Robert W. Erickson and Dragan Maksimovic. Fundamentals of Power Electronics. Springer Science+Business Media, LLC, second edition, 2001.
[2] Raymond T. Stefani, Bahram Shahian, Clement J. Savant, and Gene H.
Hostetter. Design of Feedback Control Systems. Oxford University Press,
fourth edition, 2002.

22

23
Figure 17: PECS schematic of PI-compensated buck converter

24
Figure 18: PECS schematic of lead-compensated buck converter

25
Figure 19: PECS schematic of lead - and PI-compensated buck converter