Iccag
Iccag
Advanced Geometries
User Guide
Version J-2014.09-SP2, December 2014
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Contents
1.
2.
3.
Customer Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xiii
Overview
Double-Patterning Concepts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2
Licensing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-4
Library Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-4
1-6
1-7
1-10
2-2
2-3
2-8
Placement
Placement Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2
3-2
3-2
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5.
6.
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3-4
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3-4
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Routing
Routing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2
4-3
4-4
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4-5
4-5
4-6
4-6
4-7
4-7
4-8
4-8
4-9
4-9
4-10
Chip Finishing
Redundant Via Insertion for Advanced-Node Designs . . . . . . . . . . . . . . . . . . . . . . .
5-2
5-2
5-3
6-2
6-2
6-3
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Contents
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A-4
Chapter 1: Contents
Contents
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Preface
This preface includes the following sections:
Customer Support
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Audience
This user guide is for design engineers who use IC Compiler to implement advanced-node
designs.
To use IC Compiler, you need to be skilled in physical design and design synthesis and be
familiar with the following:
Related Publications
For additional information about the IC Compiler tool, see the documentation on the
Synopsys SolvNet online support site at the following address:
https://solvnet.synopsys.com/DocsOnWeb
You might also want to see the documentation for the following related Synopsys products:
Milkyway Environment
IC Validator
StarRC
Preface
About This User Guide
Version J-2014.09-SP2
Release Notes
Information about new features, enhancements, changes, known limitations, and resolved
Synopsys Technical Action Requests (STARs) is available in the IC Compiler Release Notes
on the SolvNet site.
To see the IC Compiler Release Notes,
1. Go to the SolvNet Download Center located at the following address:
https://solvnet.synopsys.com/DownloadCenter
2. Select IC Compiler, and then select a release in the list that appears.
Preface 1: Preface
Chapter
About This User Guide
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Conventions
The following conventions are used in Synopsys documentation.
Convention
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Preface
About This User Guide
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Customer Support
Customer support is available through SolvNet online customer support and through
contacting the Synopsys Technical Support Center.
Accessing SolvNet
The SolvNet site includes a knowledge base of technical articles and answers to frequently
asked questions about Synopsys tools. The SolvNet site also gives you access to a wide
range of Synopsys online services including software downloads, documentation, and
technical support.
To access the SolvNet site, go to the following address:
https://solvnet.synopsys.com
If prompted, enter your user name and password. If you do not have a Synopsys user name
and password, follow the instructions to sign up for an account.
If you need help using the SolvNet site, click HELP in the top-right menu bar.
Open a support case to your local support center online by signing in to the SolvNet site
at https://solvnet.synopsys.com, clicking Support, and then clicking Open A Support
Case.
Preface 1: Preface
Chapter
Customer Support
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1
Overview
The IC Compiler advanced geometry (IC Compiler-AG) mode supports advanced design
rules and considers double-patterning requirements throughout the design planning and
implementation flows for the 20-nm process node and below.
The commands used to perform the design planning and implementation tasks in advanced
geometry mode are the same as those used in the other IC Compiler packages. For detailed
information about these commands, see the IC Compiler Design Planning User Guide and
the IC Compiler Implementation User Guide, as well as the command man pages.
To learn about the advanced-node support enabled by the advanced geometry mode, see
Double-Patterning Concepts
Licensing Requirements
Library Requirements
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Double-Patterning Concepts
At the 20-nm process node and below, printing the required geometries is extremely difficult
with the existing photolithography tools. To address this issue, a new technique, double
patterning, is used to partition the layout mask into two separate masks, each of which has
an increased manufacturing pitch to enable higher resolution and better printability, as
shown in Figure 1-1.
Figure 1-1
Double-Patterning Example
To use double patterning, you must be able to decompose the layout into two masks, each
of which meets the double-patterning spacing requirements. In the double-patterning design
flow, the masks are identified by a color, as shown in Figure 1-1. A double-patterning
violation occurs if your layout contains a region with an odd number of neighboring shapes
where the distance between each pair of shapes is smaller than the double-patterning
minimum spacing. This type of violation, which is called an odd cycle, is shown in Figure 1-2.
Chapter 1: Overview
Double-Patterning Concepts
1-2
Figure 1-2
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Odd-Cycle Violation
If the spacing between any pair in the loop is greater than the double-patterning minimum
spacing, no violation occurs and the layout can be decomposed. For example, in Figure 1-3,
if the spacing, x, between segments B and C is greater than the double-patterning minimum
spacing, there is no odd cycle and the layout can be decomposed.
Figure 1-3
No Odd-Cycle Violation
The IC Compiler advanced geometry mode ensures that the generated layout is conducive
to double patterning by considering the double-patterning spacing requirements during
placement and routing and preventing odd cycles.
In general, double patterning is performed only on the bottom (lowest) metal layers, which
are referred to as double-patterning layers. The metal shapes on the double-patterning
layers must meet the double-patterning spacing requirements, whether they are routing
shapes or metal within the standard cells and macros. The metal shapes on other layers do
not need to meet the stricter double-patterning spacing requirements.
Chapter 1: Overview
Double-Patterning Concepts
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Licensing Requirements
The IC Compiler advanced geometry mode requires the Galaxy-AdvRules license key.
When you run multicore processes in advanced geometry mode, the tool requires one
Galaxy-AdvRules license key for every four cores.
To perform In-Design double-patterning verification using IC Validator, you must also have
the ICValidator2 license package for IC Validator.
Library Requirements
The IC Compiler advanced geometry mode has the following library requirements (in
addition to the standard IC Compiler library requirements):
doublePatternEndToEndMinSpacing
doublePatternEndToSideMinSpacing (or
doublePatternEndToSideMinSpacingTbl)
doublePatternSideToSideMinSpacing
doublePatternCornerMinSpacing
For information about defining the routing design rules in the technology file, see the
IC Compiler Technology File and Routing Rules Reference Manual.
Chapter 1: Overview
Licensing Requirements
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For example, to read the electromigration constraints from a TLUPlus file named
em.tluplus, use the following command:
icc_shell> read_signal_em_constraints -tluplus em.tluplus
Correct-by-construction
In a correct-by-construction standard cell library, the cells have sufficient spacing to
the cell boundaries to ensure that double-patterning violations do not occur during
placement, and the libraries can be used as-is.
When you use correct-by-construction libraries, you follow the uncolored design flow
and the tool determines the appropriate mask settings for the pins and net shapes.
Precolored
In a precolored standard cell library, the metal shapes inside the cells are assigned a
double-patterning mask constraint, which is often referred to as a color. During
placement and routing, the tool must consider these mask constraints to ensure that
double-patterning violations do not occur.
For information about setting double-patterning mask constraints on standard cells
and hard macros, see Library Preparation.
When you use precolored libraries, you follow the precolored design flow and the tool
uses the double-patterning mask constraints to determine the appropriate mask
settings for the pins and net shapes.
Before starting place and route, you must determine which type of standard cell library
you are using, as this affects the design flow.
See Also
Chapter 1: Overview
Library Requirements
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Attribute value
Description
same_mask
This constraint means that the mask color is not yet been determined.
Shapes with this attribute must be at least the double-patterning minimum
spacing distance from any other colored metal shape.
mask1_hard
This constraint means that the shape has the mask1 color. Shapes with this
attribute must be at least the double-patterning minimum spacing distance
from other mask1-colored metal shapes.
mask1_soft
The mask1_hard attribute value is usually set on macro pins, while the
mask1_soft attribute value is usually set on nets.
mask2_hard
mask2_soft
This constraint means that the shape has the mask2 color. Shapes with this
attribute must be at least the double-patterning minimum spacing distance
from other mask2-colored metal shapes.
The mask2_hard attribute value is usually set on macro pins, while the
mask2_soft attribute value is usually set on nets.
any_mask
This constraint means that the shape is not colored. Shapes with this
attribute must be at least the standard minimum spacing distance from other
metal shapes; the double-patterning minimum spacing rules do not apply to
these shapes.
Chapter 1: Overview
Double-Patterning Mask Constraints
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To show the double-patterning mask constraints (colors) when you view metal shapes in the
GUI, select Show mask color in the Color tab of the View Settings panel, as shown in
Figure 1-4.
Figure 1-4
Chapter 1: Overview
Double-Patterning in the Design Flow
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Chapter 1: Overview
Double-Patterning in the Design Flow
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Figure 1-6
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To learn about using the IC Compiler tool with advanced-node designs, see
Placement
Routing
Chip Finishing
Chapter 1: Overview
Double-Patterning in the Design Flow
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To start the tool in the graphical user interface (GUI), use the -gui option.
% icc_shell -ag_mode -gui
Chapter 1: Overview
Starting the IC Compiler Tool in Advanced Geometry Mode
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Design Planning and PG Routing
During hierarchical design planning and power and ground (PG) routing, you must consider
the double-patterning requirements to avoid odd-cycle violations or routing difficulties later
in the design flow.
To learn about performing hierarchical design planning and PG routing on advanced-node
designs, see
Hierarchical Floorplanning
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Hierarchical Floorplanning
Maintaining a double-patterning-compliant layout in a hierarchical flow can be difficult
because you do not have complete visibility of the design throughout the flow. When working
at the block level, the top-level shapes are not visible. When working at the top level, only the
extracted pin shapes are visible. When the top level and blocks are integrated, odd-cycle
violations can occur due to same-layer shapes within the double-patterning minimum
spacing distance across the block boundary or same-layer shapes that connect to a block
pin in the block and the top level. Figure 2-1 shows examples of these hierarchical odd-cycle
violations.
Figure 2-1
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that pins with the same mask color have at least the double-patterning minimum
spacing distance between them.
In addition, for blocks with low pin density, you should skip at least one track for every
five pins.
Create routing blockages on the double-patterning layers along the block boundary and
around the block pins to prevent routing shapes in these areas.
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By default, the tool determines the internal padding size based on the average space
between wire tracks on all the layers. You can increase the padding size by using the
-internal_widths and -external_widths options with the
create_fp_plan_group_padding command. However, you cannot decrease the
padding size from the computed default.
3. Perform congestion-driven placement by using the create_fp_placement command.
The create_fp_placement command considers the global routing track utilization
values set in step 1 when performing the placement.
icc_shell> create_fp_placement -congestion_driven
During pin assignment, the tool creates the block pins based on the global routing results
(or on flylines). If possible, the tool places pins on non-double-patterning layers. If it must
place a pin on a double-patterning layer, it automatically increases the pin depth (the
length of the pin extending inside the block from the edge of the block). By default, the
tool uses a double-patterning minimum pin depth of between 10 and 14 times the
minimum track width, depending on the estimated pin density. Figure 2-3 shows an
example of how the tool increases the pin depth for a double-patterning design.
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If the default double-patterning minimum pin depth is not sufficient to enable pin access
for your design, set a pin-depth constraint by using the -depth option with the
set_pin_physical_constraints command. This option specifies the minimum pin
length in microns.
icc_shell>
-layers
icc_shell>
icc_shell>
set_pin_physical_constraints [get_pins *] \
{dpt_layers} -depth min_length
set_fp_pin_constraints -use_physical_constraints on
place_fp_pins -use_existing_routing [get_plan_groups]
When you run the check_fp_pin_assignment command with the -pin_size option, it
verifies that all pins on double-patterning layers have the minimum depth and issues
errors for pins shorter than this minimum depth.
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mask1_hard
mask1_soft
mask2_hard
mask2_soft
same_mask
any_mask
X
mask1_hard
mask1_soft
mask2_hard
mask2_soft
any_mask
9. Create mask constraint route guides around the pins and boundaries of each soft macro.
A mask constraint route guide is a zero-spacing route guide that prevents the router from
creating any net shapes within its boundary and guides the router to create routes
without creating hierarchical mask constraint violations.
icc_shell> create_mask_constraint_route_guides
Figure 2-4 shows the mask constraint route guides created by this command. The figure
on the left illustrates the route guides for a design with low pin density, while the figure on
the right illustrates the route guides for a design with high pin density.
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The route guides created by this command around pins use the naming style
__DPT_ROUTE_GUIDE_PIN_x_y, where x is the mask number and y is a nonnegative
integer. The route guides created by this command around the boundary use the naming
style __DPT_ROUTE_GUIDE_BDRY_x_y, where x is the mask number and y is a
nonnegative integer. You can query, view, and remove these route guides just like any
other route guides.
Note:
If you modify the pin shapes or pin placement, you must regenerate the mask
constraint route guides. The create_mask_constraint_route_guides command
removes any existing mask constraint route guides in the design and then creates
new ones.
10.Perform block-level optimization and implementation.
11.Create a FRAM view for each soft macro that includes mask constraint route guides.
By default, the create_macro_fram command creates mask constraint route guides on
all layers for which double-patterning spacing rules are defined in the technology file.
icc_shell> create_macro_fram
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Avoiding jogs that occupy or block an odd number of pitches (odd-pitch jogs)
Figure 2-5
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Placement
During placement, you need to ensure that the pins of the placed cells do not create
double-patterning violations and that the additional resources required by double-patterning
do not cause congestion issues.
To learn about performing placement on advanced-node designs, see
Placement Overview
For general information about performing placement with the IC Compiler tool, see the
Placement and Optimization chapter in the IC Compiler Implementation User Guide.
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Placement Overview
Figure 3-1 shows the steps used to perform placement in the double-patterning design flow.
The left side shows the steps in the uncolored flow, while the right side shows the steps in
the precolored flow, which contains an additional step (shown in red).
Figure 3-1
Placement Tasks
Chapter 3: Placement
Placement Overview
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Note:
In addition to setting this variable, threshold voltage implant layer rules must be defined
in the technology file and the implant width property must be attached to the FRAM views
of the multiple threshold voltage cells. For information about these library preparation
requirements, see Defining Implant Layer Rules in the Technology File on page A-2.
When you enable these rules,
The legalizer considers the minimum width and minimum spacing rules of the threshold
voltage implant layers and adjusts the cell placements to meet these rules. The following
message in the log file indicates that these rules are enabled during legalization:
INFO: Legalizer/Checker to consider Vth-based spacing rules
To remove the threshold voltage implant layer spacing rules, use the
remove_all_spacing_rules command with the legalizer_consider_vth_spacing
variable set to true.
Chapter 3: Placement
Setting the Placement Constraints
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To determine whether the double-patterning rules are enabled for placement, use the
is_double_patterning_enabled command.
Chapter 3: Placement
Performing Placement in the Precolored Flow
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Cell placement in
Milkyway database
Double-patterning
spacing violation
Cell placement in
GDSII or OASIS
Violation
fixed
Stream out to
GDSII or OASIS
INV1
AN2
INV1
AN2_S_15_1_17_1
Stream out
mask_shift attribute set
to perform color swapping
on this instance
M1, mask1
AN2_S_15_1_17_1
M1, mask2
To perform this swap, the placer sets the mask_shift attribute on the cell instance. This
attribute is a text string that specifies whether to swap the mask constraints within each
layer. For example, when the attribute is set to the following string, the tool swaps the mask
constraints of the shapes in the M1 layer, but not in the VIA1 and M2 layers:
{{M1 1} {VIA1 0} {M2 0}}
The write_stream command uses the mask_shift attribute setting to modify the mask
constraints of the shapes within each cell during stream-out to GDSII or OASIS format. In
this example, the write_stream command swaps the mask constraints in layer M1. For that
layer only, it writes out the shapes with a mask constraint of mask1 to the mask2 mask, and
conversely, writes out the shapes a mask constraint of mask2 to the mask1 mask.
See Also
Chapter 3: Placement
Performing Placement in the Precolored Flow
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Chapter 3: Placement
Performing Congestion-Driven Placement
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Routing
When routing advanced-node designs, Zroute avoids and fixes odd-cycle violations as well
as the other routing design rule violations.
To learn about performing routing on advanced-node designs, see
Routing Overview
For general information about performing routing with Zroute, see the Routing Using
Zroute chapter in the IC Compiler Implementation User Guide.
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Routing Overview
Figure 4-1 shows the steps used to perform routing in the uncolored double-patterning
design flow. Note that the step shown in darker purple is required only in the uncolored flow.
Figure 4-1
Figure 4-2 shows the steps used to perform placement in the precolored double-patterning
design flow, which contains an additional step (shown in green).
Chapter 4: Routing
Routing Overview
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Figure 4-2
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Chapter 4: Routing
Preparing for Routing
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Chapter 4: Routing
Preparing for Routing
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You apply the precoloring routing rule to a net in the same way as any other nondefault
routing rule. For example, to apply the clock_mask1_soft precoloring routing rule defined in
the previous example to the CLK clock, use the following command:
icc_shell> set_clock_tree_options -clock_trees CLK \
-layer_list {M4 M5} -routing_rule clock_mask1_soft \
-use_default_routing_for_sinks 1
To ensure DRC convergence, you should set double-patterning mask constraints only on a
very few timing-critical nets.
Chapter 4: Routing
Preparing for Routing
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See Also
Using Nondefault Routing Rules section in the routing chapter of the IC Compiler
Implementation User Guide
Uses the double-patterning spacing rules to avoid and fix local odd-cycle violations
Unlike other routing design rules, all metal shapes need not meet the double-patterning
spacing rules; the tool checks only for odd-cycle violations. Zroute automatically
identifies metal shapes that can cause odd-cycle violations, such as those caused by
odd-pitch jogs, off-grid wires, or routing in the nonpreferred direction, and applies the
double-patterning spacing rules only when needed.
Ensures that all metal shapes meet the other routing rules, including the advanced-node
routing rules
See Also
Double-Patterning Concepts
Chapter 4: Routing
Routing Advanced-Node Designs
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If a neighboring shape on the same layer is the same mask color or is an undetermined
mask color (same_mask mask constraint), the shapes must meet the double-patterning
minimum spacing requirements.
If a neighboring shape on the same layer is a different mask color or is not colored, the
shapes must meet the minimum spacing defined for the layer (or the nondefault routing
rule, if one has been assigned to the net).
Figure 4-3 shows an odd-cycle violation detected by the interactive DRC capability.
Chapter 4: Routing
Routing Advanced-Node Designs
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Chapter 4: Routing
Verifying the Routing
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Note:
The signoff_drc command uses the on-disk design information, not the design
information in memory. You must save the current state of the design before running the
signoff_drc command.
When you analyze the DRC violations reported by the signoff_drc command, you should
not see local odd-cycle violations, as these are addressed by Zroute. If you see local
odd-cycle violations, check the consistency between the technology file and the runset. If
you see long-range odd-cycle violations (more than 5 microns in extent), use the
signoff_autofix_drc command to fix these violations.
See Also
Performing Signoff Design Rule Checking section in the routing chapter of the
IC Compiler Implementation User Guide
Chapter 4: Routing
Verifying the Routing
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Note that to fix odd-cycle violations, you must run a separate signoff_autofix_drc
command that targets only these violations. When you run the signoff_autofix_drc
command to fix odd-cycle violations, you must
The signoff_autofix_drc command processes only those rules that are specified in
the configuration file. To determine the double-patterning rules for your technology, see
the design rule manual (DRM) provided by your vendor.
Use the -incremental_level off option to disable incremental mode (odd-cycle fixing
works only in non-incremental mode)
The following example shows the syntax used to perform automatic fixing of the odd-cycle
violations detected by signoff_drc:
icc_shell> signoff_autofix_drc \
-init_drc_error_db initial_icv_error_dir \
-config_file DPT_config_file \
-custom_guidance dpt
-incremental_level off
See Also
Automatically Fixing Signoff DRC Violations section in the routing chapter of the
IC Compiler Implementation User Guide
Chapter 4: Routing
Extraction for Advanced-Node Designs
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If you run this command multiple times, the new setting overrides the existing setting;
extraction always uses the latest setting.
For more information about the ER_VS_SI_SPACING and ETCH_VS_WIDTH_AND_SPACING
tables, see the StarRC documentation.
Chapter 4: Routing
Extraction for Advanced-Node Designs
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5
Chip Finishing
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Perform redundant via insertion as a standalone task after completing initial routing and
again after completing all postroute optimization runs.
See Also
Inserting Redundant Vias section in the chip finishing chapter of the IC Compiler
Implementation User Guide
Note:
In addition to setting this variable, the threshold voltage implant layer rules must be
defined in the technology file and the implant width property must be attached to the
FRAM views of the multiple threshold voltage cells. For information about these library
preparation requirements, see Defining Implant Layer Rules in the Technology File on
page A-2.
If you enable both the threshold voltage implant layer spacing rules and the no-1X rule
during filler cell insertion, the reference library must contain at least 2X and 3X filler cells;
otherwise, filler cell insertion fails.
During filler cell insertion, the tool writes insertion details for the implant layers to the log file.
Note:
Consideration of the threshold voltage implant layer spacing rules during filler cell
insertion is not the same as using the -vt_filler option with the
insert_stdcell_filler command to specify the cells used as threshold voltage fillers.
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After performing filler cell insertion, use the signoff_drc command to run DRC checking in
the IC Validator tool to verify that there are no violations of threshold voltage implant layer
spacing rules.
See Also
Inserting Filler Cells section in the chip finishing chapter of the IC Compiler
Implementation User Guide
For the end-cap cells for the left and right boundaries, you specify a single library cell by
using the -left_boundary_cell and -right_boundary_cell options, respectively.
For the end-cap cells for the top and bottom boundaries, you specify a list of library cells
by using the -top_boundary_cells and -bottom_boundary_cells options,
respectively. The command inserts the cells in the specified order. If the remaining space
is smaller than the current cell, the command inserts the next cell in order that fits in the
remaining space.
To ensure that the end-cap cells inserted on the top and bottom boundary rows comply
with the maximum diffusion-to-tap distance limit, you can also insert tap cells on these
boundary rows. To specify the library cell to use for the tap cells, use the -top_tap_cell
and -bottom_tap_cell options, respectively, and use the -tap_distance option to
specify the distance in microns between the tap cells.
For a vertical-row design, rows start at the bottom and end at the top, so the top
boundary is along the left side of the design and the bottom boundary is along the right
side of the design.
For the flipped rows in a double-back design, the top boundary cells are used on the
bottom boundaries and the bottom boundary cells are used on the top boundaries.
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For the outside corner cells, you specify a single library cell for each corner location by
using the -top_left_outside_corner_cell, -top_right_outside_corner_cell,
-bottom_left_outside_corner_cell, and -bottom_right_outside_corner_cell
options.
For the inside corner cells, you specify a list of library cells for each corner location by
using the -top_left_inside_corner_cells, -top_right_inside_corner_cells,
-bottom_left_inside_corner_cells, and -bottom_right_inside_corner_cells
options. The command inserts the first corner cell that matches the size of the inside
corner. If none matches exactly, it inserts the first cell that can be placed without violating
any rules.
Figure 5-1 shows an example of the end-cap and corner cell locations for a horizontal-row
design with two hard macros.
Figure 5-1
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By default, the command places the specified library cells in their default orientation around
the core area, voltage areas, and hard macros without considering blockages or keepout
margins. To change the default behavior, use the -rules option to specify one or more
insertion rules.
To flip the orientation of the boundary cells, specify one or more of the following rules:
mirror_left_boundary_cells, mirror_right_boundary_cells,
mirror_left_outside_corner_cell, mirror_right_outside_corner_cell,
mirror_left_inside_corner_cell, and mirror_right_inside_corner_cell. You
cannot flip the orientation of the top and bottom boundary cells.
To prevent the command from placing boundary cells inside blockages or keepouts,
specify one or more of the following rules: respect_hard_blockage,
respect_soft_blockage, respect_hard_macro_keepout, and
respect_soft_macro_keepout.
To prevent boundary cell insertion when the row length equals two times the corner cell
width plus one unit tile width, specify the no_1x rule. Note that if the row length equals
two times the corner cell width, boundary cells are inserted.
To swap the top and bottom inside corner cells on flipped rows, specify the
swap_top_bottom_inside_corner_cell rule. When you specify this rule, the
command uses the bottom inside corner cell on the top inside corner of flipped rows and
the top inside corner cell on the bottom inside corner of flipped rows.
To remove end-cap cells from your design, use the remove_stdcell_filler -end_cap
command.
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6
Streaming Out a Precolored Design
To learn about streaming out a GDSII or OASIS file for a precolored design, see
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Data type
Mask constraint
108
same_mask
120
mask1_hard
121
mask2_hard
When you stream out a GDSII file for a precolored design, you must use the precolor layer
mapping file shown in Example 6-1 to map the mask constraints to the data types.
Example 6-1
M * *:108
M1 * *:120
M2 * *:121
If you have saved the precolor layer mapping file in the Milkyway design database by using
the set_stream_layer_map_file -format out command, the write_stream command
uses the saved layer mapping file. Otherwise, you must specify the precolor layer mapping
file by using the set_write_stream_options -map_layer command before streaming out
the GDSII file.
Note:
The precolor layer mapping file specified by the set_write_stream_options
-map_layer command overrides the precolor layer mapping file saved in the Milkyway
design database.
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Suffix string
By default, the write_stream command uses SHIFT as the suffix string. To modify the
suffix string, use the set_write_stream_options
-mask_shifted_cell_name_suffix command before running the write_stream
command.
The number 1, indicating a mask swap for the layer (and so on)
For example, suppose that the name of the original cell master is AN2, the default suffix
string SHIFT is being used, and the mask_shift attribute of an AN2 cell instance is set as
follows:
{{M1 1} {VIA1 0} {M2 1}}
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In that case, the swap occurs in layer M1 (layer number 15) and in layer M2 (layer number
17), so the name of the newly generated cell master is AN2_SHIFT_15_1_17_1.
The IC Compiler tool does not add the new cell master to the Milkyway database. It only
streams out the new cell master to the GDSII file.
See Also
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A
Library Preparation
To learn about library preparation steps that might be required to run place and route on
advanced-node designs, see
For general information about the IC Compiler library preparation process, see the Library
Data Preparation for IC Compiler User Guide.
For recommendations about how to design standard cell libraries to improve the routability
of advanced-node designs, see SolvNet article 035309, Application Note for Physical
Library Analysis for Optimal 28-nm and 20-nm Routing.
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Mask swapping is disabled for a specific cell in a LEF file if the MACRO definition contains the
FIXEDMASK keyword.
MACRO macroName
CLASS className subclassName ;
FIXEDMASK ;
...
Layer "VTS_N" {
layerNumber = 60
maskName = "implant"
isDefaultLayer = 1
minWidth = 0.45;
minSpacing = 0.45
}
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Layer VTS_P {
layerNumber = 61
maskName = "implant"
minWidth = 0.45;
minSpacing = 0.45
}
Layer VTL_N {
layerNumber = 62
maskName = "implant"
minWidth = 0.45;
minSpacing = 0.45
}
Layer "VTL_P" {
layerNumber = 63
maskName = "implant"
minWidth = 0.45;
minSpacing = 0.45
}
The technology file defines the implant layers, as described in the previous section,
Defining Implant Layer Rules in the Technology File."
The LEF or GDSII file defines the implant layer geometries for the cells
Physical implementation uses the FRAM views, rather than the CEL views, to check for
spacing violations. Therefore, you must extract the implant width properties from the CEL
views and attach them to the FRAM views before performing physical implementation. To do
this, use the extract_fram_property command with the -implant_width option set to
true.
icc_shell> extract_fram_property -lib myreflib -implant_width true
By default, the extract_fram_property command extracts the implant width property for
all standard cells, standard filler cells, and tap cells in the reference library. To extract the
implant width property for a specific cell, use the -cell option.
To report the extracted implant width properties, use the report_fram_property
command. When you run this command, you must specify the reference library with the
-lib option and specify the cell to report with the -cell option. You can report the extracted
information either for a single cell by specifying the cell name or for all cells by using an
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asterisk (*). For example, to report the extracted information for all cells in the myreflib
reference library, use the following command:
icc_shell> report_fram_property -lib myreflib -cell *
When you use the extract_blockage_pin_via command to convert the CEL view to a
FRAM view, the mask constraints on the terminals are stored in the generated FRAM view.
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In a GDSII file, precolored pins are identified by an extra layer; the data type indicates the
mask constraint. Table A-1 shows the mapping between the GDSII data types and the mask
constraints.
Table A-1
Data type
Mask constraint
108
same_mask
120
mask1_hard
121
mask2_hard
When you stream in the precolored GDSII file, you must use the layer mapping file shown in
Example A-2 (which is the same as the layer mapping file used for stream out).
Example A-2
M * *:108
M1 * *:120
M2 * *:121
If you have saved the precolor layer mapping file in the Milkyway design database by using
the set_stream_layer_map_file -format in command, the read_stream command
uses the saved layer mapping file. Otherwise, you must specify the precolor layer mapping
file by using the set_read_stream_options -map_layer command before streaming in
the GDSII file.
Note:
The precolor layer mapping file specified by the set_read_stream_options
-map_layer command overrides the precolor layer mapping file saved in the Milkyway
design database.
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