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    Homework #3: Due Feb 24th, in Class

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    Parijat Basu
    This homework assignment for a digital systems and circuits course contains three questions about designing and analyzing complex logic gates and circuits. Question 1 involves designing a complex gate to implement the function F=ABC+D and analyzing its logical effort and delay. Question 2 asks about determining the critical path delay and switching combination for a given logic circuit. Question 3 involves determining the optimum number of stages, implementing a given logic function, and sizing the gates to optimize the delay.

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    Homework #3: Due Feb 24th, in Class

    Uploaded by

    Parijat Basu
    29 views2 pages
    This homework assignment for a digital systems and circuits course contains three questions about designing and analyzing complex logic gates and circuits. Question 1 involves designing a complex gate to implement the function F=ABC+D and analyzing its logical effort and delay. Question 2 asks about determining the critical path delay and switching combination for a given logic circuit. Question 3 involves determining the optimum number of stages, implementing a given logic function, and sizing the gates to optimize the delay.

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    HW LogicalEffort1

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    This homework assignment for a digital systems and circuits course contains three questions about designing and analyzing complex logic gates and circuits. Question 1 involves designing a complex gate to implement the function F=ABC+D and analyzing its logical effort and delay. Question 2 asks about determining the critical path delay and switching combination for a given logic circuit. Question 3 involves determining the optimum number of stages, implementing a given logic function, and sizing the gates to optimize the delay.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    29 views2 pages

    Homework #3: Due Feb 24th, in Class

    Uploaded by

    Parijat Basu
    This homework assignment for a digital systems and circuits course contains three questions about designing and analyzing complex logic gates and circuits. Question 1 involves designing a complex gate to implement the function F=ABC+D and analyzing its logical effort and delay. Question 2 asks about determining the critical path delay and switching combination for a given logic circuit. Question 3 involves determining the optimum number of stages, implementing a given logic function, and sizing the gates to optimize the delay.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    EEE 425/591

    Digital Systems and Circuits


    Spring 2016
    Due Feb 24th, in class

    Homework #3
    Use n/p=2

    Q1. Design complex gate gate such that F = ABC + D


    (a) Draw a transistor schematic
    (b) Size the transistors such that the resistance of each path is the same as the resistance of
    the minimum sized inverter.
    (c) What are the logical efforts for this gate inputs?
    (d) What are the worst case delays for this gate driving a fan-out of four minimum sized
    inverters using Elmore delay (use transistor-level diagram and do not ignore internal
    parasitics)?
    Q2. The gates in Figure 1 are all minimum sized. The input capacitance of a minimum sized
    inverter is 10fF.
    (a) Determine the delay of the critical path (in terms of the inverter delay)
    (b) Determine the switching combination that activates the critical path.

    A
    B
    X
    C
    CL=50fF

    Y
    F
    G

    Figure 1

    CL=50fF

    Q3. You are given the logic function: = + + +


    The load at the output is 200fF, the input capacitance of a minimum sized inverter is 3fF.
    (a) Determine the optimum number of stages
    (b) Implement the logic function with the number of stages as close to the number you
    found in part (a)
    (c) When all gates are minimum sized, what is the delay in terms of the delay of the
    minimum-sized inverter?
    (d) Size the path to optimize the delay
    (e) Determine the optimum delay

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