Logical Effort

1 Explain logical effort and stage delay with the help of an example.
2 What is Elmore delay. Explain with the help of an example?

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4 a)Draw the Stick Diagram of 3-input NAND Gate.

b)Define (i) Logical Effort (ii) Parasitic Delay
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Sketch a pseudo nmos gate that implements the function--> F= (A(B+C+D)+EFG)'. Also
calculate its logical efforts (for input A)
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17. What is skewed gate? What is it’s impact on rise delay and fall delay if high skewed gates
are present?
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19. Find the worst-case Elmore parasitic delay of an n-input NOR gate
20. Consider the two designs of a 2-input AND gate shown in Figure. Give an intuitive argument
about which will be faster. Back up your argument with a calculation of the path effort, delay,
and input capacitances x and y to achieve this delay.
21. What are the delays in a logic gate.

a) Compute Elmore delay for Node 2, 5 & 6 (figure 1).
b) Size the transistors so that PUN & PDN resistances are matched & calculate the
logical effort. (Figure 2).
fig 1
fig 2
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42) Is path effort F always equal to GH? If not mention the case when these are not equal.
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50.What is Domino Logic? Implement OAI221 using Domino logic,

and find logical effort at each input.
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What is the logical effort of an OR-AND-INVERT gate at either of the OR terminals?
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67.) For a given circuit, find the values of G, H, B, F, f, and D. Also find out the activity factor for
each stage.
68.) Two 3 input NAND gates are connected in series with an output load of 36λ. The
sizes of the NAND gates are x1 and x2 respectively. The best stage effort is 10. Find
the sizes x1 and x2.
69.)
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b)
c) Find Logical Effort ?

d)
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SOLUTION ON NEXT PAGE
ANSWER 72
73. Sketch a stick diagram for a 4 input NOR gate and calculate is logical effort ( Worst
Case)?
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a) Draw XOR gate using CMOS and determine its logical effort. [3 marks]
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100) Use the linear delay model to estimate the delay of fan-out-of-5(FO5) of a 4 input nor gate.
assume t=3ps.
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a) Define logical effort. Write the limitations of logical effort. (2 Marks)
b) Sketch a 4-input NAND gate with transistor widths chosen to achieve equal rise and fall
resistance as a unit inverter. Find the logical effort. (2 Marks)
c) Give any two types of variations in fabrication which leads to SS lot? (1 Marks)
106.Draw CMOS circuit and stick diagram for the given function?
f(A,B,C) = (A.B + C)’
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Q1- Short answer type-
What is an activity factor? How does it differ from the clock frequency?
Q2- Long Answer type-

Explain the concept of clock gating and power gating with proper diagram .
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146. F = ((A + B) · (C + D))’ ( ’ denotes complement of the expression )
a) sketch a stick diagram

b) sketch the RC circuit for the given expression.
c) Calculate tcdf, tpdr
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Provide equivalent static CMOS logic and stick diagram for the function f=(a+b.c+d)’.
Also mention the width of PMOS and NMOS
STATIC CMOS LOGIC:
SIZING OF PMOS AND NMOS:
STICK DIAGRAM:
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a. Create a CMOS circuit for the following expression: [2] F = (A+BCD)’
b. Size the MOSFETS appropriately for minimum propagation delays. [2] c. Create a stick diagram
for the layout. (Share diffusion wherever possible). [3] d. Draw the RC model for the same for the
above layout. [2] e. Compute output and input capacitance for all inputs. [1 + 0.5+0.5+0.5+0.5] f.
Calculate logical effort for the gate. [1] g. Assume that q copies of the same gate are connected to
the output. Assume connection
of the input which has highest C_in. Assume parasitic delay = number of inputs of device. Calculate
electric effort and delay for your device. [2] h. Assuming the same q copies connected, calculate
tpdr, tpdf, tcdf, tcdr. Mention the input combinations considered for calculating the same. [2+2+2+2]
159.
Explain at least four challenges with domino logic [0.5 x 4 = 2].
160.
Transmission gate logic
a. What is transmission gate logic? [1] b. Explain one drawback of transmission gate logic apart from
the RC delays. [1] c. Derive the RC delay of a transmission gate chain of n identical stages. [1.5] d.
Mention one solution to the delay issues in transmission gates. Backup your answer with
mathematical derivation (if any) [1.5]
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1 Explain logical effort and stage delay with the help of an example.

2 What is Elmore delay. Explain with the help of an example?

4 a)Draw the Stick Diagram of 3-input NAND Gate.

21. What are the delays in a logic gate.

50.What is Domino Logic? Implement OAI221 using Domino logic,

What is the logical effort of an OR-AND-INVERT gate at either of the OR terminals?

c) Find Logical Effort ?

SOLUTION ON NEXT PAGE

Q2- Long Answer type-

a) sketch a stick diagram

c) Calculate tcdf, tpdr

SIZING OF PMOS AND NMOS:

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