DCEPF

Combinational
1. Realize an NAND gate using a 2:1 multiplexer

2. Suppose you have a combinational circuit between two registers driven by a clock. What
will you do if the delay of the combinational circuit is greater than your clock signal?
3.
4. No. of full adders needed to detect the number of 1s in a 7 bit stream.

5. You are required to design a circuit equivalent to the one below, using only Mux
structures.
6. MinMax2 is a component with 2 inputs A and B, and 2 outputs Max and Min. You
guessed it, you connect the 2 n-bit numbers at the inputs and the component drives the
Max output with the bigger of the two and the Min output with the smaller of the two.
Your job is to design a component MinMax4, with 4 inputs and 4 outputs which sorts
the 4 numbers using only MinMax2 components. Try to use as little as
possible MinMax2 components. If you made it so far, try making
a MinMax6 component from MinMax2 and MinMax4 components.
7. There is a shortage of XOR gates. Unfortunately, the only logic gates available are two
weird components called X and Y. The truth table of both components is presented
below Z represents a High-Z value on the output.
Could you help the poor engineers of Logicia to build an XOR gate?
8. Consider the following circuit:
The encoder has the following priorities: I2 > I0 > I1 > I3.
Find outputs W, X, Y, and Z for all possible combinations of inputs A, B, C, and D.
Consider the constants in Table 1, unless otherwise specified in the question.
9. A programmable logic block is given. Implement f(a,b,c) = a.c + a . b function.

10. Implement a D-latch using 2x1 multiplexer(s).
11. Implement a D-FF using 2x1 multiplexer(s).
12.
13.
14.
15.
16.
Sequential
1. Design a divide-by-5 sequential circuit with 50% duty cycle
2. Design a digital circuit to delay the negative edge of the input signal by 2 clock cycles
3. I) Design a state-machine (or draw a state-diagram) to give an output 1 when the
number of As are even and number of Bs are odd. The input is in the form of a serial-
stream (one-bit per clock cycle). The input s could be of the type A, B or C. At any given
clock cycle, the output is a 1, provided the number of As are even and number of Bs
are odd. At any given clock cycle, the output is a 0, if the above condition is not
satisfied. II) Detect the sequence abca when the inputs can be abcd.
4. Design a FSM to divide the clock by 3/2
5. The signal X forms the input to a shift register that is clocked by CLOCK. As shown in
the timing diagram, the signal Z gives one pulse when X goes high and two pulses when
it returns low. If the successive outputs from the shift register are A, B, C, derive a
Boolean expression for Z.
6. The state diagram and input waveforms of a state machine are shown below. All input
and state transitions occur shortly after the clock rising edge. Complete the timing
diagram by indicating the value of the state during each clock cycle and by drawing the
waveform of X. The initial state is 0 as shown.
7. Construct the state diagram for a state machine that emits a single pulse on each rising
edge of its input and a double pulse on each falling edge as shown below. Each output
pulse should last exactly one clock cycle. Assume that the input signal has been
synchronized with the clock rising edge. How does your design react to an input signal
that goes low for less than four clock cycles?
8.
9.
10. Which circuit does the use of the following assignment correspond to?
always @(posedge clk)
begin
A<=Y;
B<=A; end
11.
12. An FSM receives an endless stream of 0s and 1s. The stream cannot be assumed to
have certain properties like randomness, transition density or the like. Is it possible to
build a state machine, which at any given moment outputs whether there were more 0>1
or 1>0 transitions so far?
13. In the diagram below both X and Y are n-bit wide registers. With each clock cycle you
could select a bit-wise basic operation between X and Y and load it to either X or Y, while
the other register keeps its value.
The problem is to exchange the contents of X and Y. Describe the values of the select
logic op and load XnotY signals for each clock cycle.
14.
15. Design a clocked synchronous Moore FSM producing a remainder of division of a

decimal number by 3 on its outputs. FSM receives the digits of a decimal number
sequentially on its inputs.
16.
17.
18.
19.
20.

DCEPF

Uploaded by

Copyright:

Available Formats

DCEPF

Uploaded by

Document Information

Original Description:

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

DCEPF

Uploaded by

Copyright:

Available Formats

Combinational

1. Realize an NAND gate using a 2:1 multiplexer

4. No. of full adders needed to detect the number of 1s in a 7 bit stream.

8. Consider the following circuit:

9. A programmable logic block is given. Implement f(a,b,c) = a.c + a . b function.

11. Implement a D-FF using 2x1 multiplexer(s).

15. Design a clocked synchronous Moore FSM producing a remainder of division of a

You might also like