CMOS Logic Family
CMOS Logic Family
CMOS Logic Family
Its speed is limited by substrate capacitances. To reduce the effect of these substrate
capacitances the latest technology known as silicon on sapphire (SOS) is used in
microprocessor fabrication which employs an insulating substance(sapphire). CMOS has
become the most popular in MSI and LSI area and is the only possible logic for the
fabrication of VLSI devices.
A CMOS switch.
CMOS inverter
The basic CMOS logic circuit is the invertor shown in the CMOS switch. For the
circuit is an invertor shown in the CMOS switch. For the circuit the logic levels are 0V (logic
0) and Vcc (logic 1). When V1=Vcc, T1 turns ON and T2 turns OFF. Therefore V0~0V, and
since the transistor are connected in series the current I0 is very small. In either logic state, T1
or T2 is off and the quiescent power dissipation which is the product of the OFF leakage
current and Vcc is very low. More complex function can be realized by combinations of
invertors.
In similar manner it can be shown that if c=0, transmission is not possible. In this gate
the control c is binary; whereas the input at A may be either digital or analog. [The
instantaneous value must be between v (0) and V (1)]
Noise Margin
Noise margin of CMOS logic is considerably higher than that of TTL and ICs. CMOS
devices have wide supply voltage. Vcc typically it is .45 Vcc
Unconnected inputs
The unconnected CMOS ICs input behave in a way similar to MOS devices.
Therefore the unused inputs must be connected to either the supply voltage terminal or one of
the used inputs provided that the fan out of the signal source is not exceeded. This is highly
unlinked for CMOS circuit because of their high fan out. Some CMOS ICs have zener diodes
connected at the input for protection against high input voltages.
The input voltages A and B are either low (ideally grounded) or high (ideally +5v). If
A or B is low, the base of Q1 is pulled down to approximately .7 V. This reduces the base
voltage of Q2 to almost zero. Therefore Q2 is cut off. With Q2 open ,Q4 goes into cutoff and
the Q3 base is pulled high. Since Q3 act as an emitter follower, the output pulled up to a high
voltage.
On the other hand when A and B are both high voltages the emitter diodes of Q1 stops
conducting and the collector diode goes into forward condition. This forces Q2 base goes
high. It turns Q4 goes into saturation, preceding a low output.
Without diode D1 in the circuit Q3 will conduct slightly when the output is low. To
prevent this, the diode is inserted; its voltage drop keeps the base-emitter diode of Q3
reverse-biased in the way only Q4 conducts when the output is low.
Unconnected Inputs
If any inputs of a TTL gate if left disconnected (open or floating) the corresponding
E-B junction of T1 will not be forward biased. Hence it acts exactly in the same way as if a
logical 1 is applied to the input. Therefore in TTL ICs all connected inputs are treated as
logical 1s. However, the unused inputs should either be connected to some. Use input or
returned to Vcc through a resistor.
Clamping diodes
Clamping diodes are connected only used in all TTL gates to suppress the ringing
causes from the last voltage transition found in TTL. These diodes shown in figure clamp the
negative undershoot at approximately .7V.
5400/7400 TTL series
TTL 5400/7400 series is the most popular and commonly used series of digital
ICs.7400 devices are used for commercial application whereas the 5400 devices are using for
military application. The only differences in these two series are in the temperature and the
power supply range. The temperature range is 0 to 70 degree Celsius for the 7400 series and -
55 to 125 degree Celsius for the 5400 series. The supply voltage range is 5 with tolerance of
.25V for the 7400 series and 5 with a tolerance .5V for 5400 series.
Reference
TTL Logic: