MODULE-4

Microprocessor v/s Microcontroller.

1. A microprocessor requires an external memory for program/data storage. Instruction

execution requires movement of data from the external memory to the microprocessor or vice
versa. Usually, microprocessors have good computing power and they have higher clock speed
to facilitate faster computation.

2. A microcontroller has required on-chip memory with associated peripherals. A

microcontroller can be thought of a microprocessor with inbuilt peripherals.

3. A microcontroller does not require much additional interfacing ICs for operation and it
functions as a stand alone system. The operation of a microcontroller is multipurpose, just like
a Swiss knife.

4. Microcontrollers are also called embedded controllers. A microcontroller clock speed is

limited only to a few tens of MHz. Microcontrollers are numerous and many of them are
application specific.

Features of 8051
ARCHITECTURE OF 8031/8051 MICROCONTROLLER

Fig. 4.1 ARCHITECTURE OF 8031/8051

CPU - Central processing Unit:
1. ALU:
It performs the arithmetic operations such as addition, subtraction, multiplication and division.
 The unit can perform logical operations such as AND, OR; and Exclusive-OR, as well as rotate,
clear, and complement.
The ALU can also manipulate one bit as well as eight-bit data types.
Individual bits may be set, cleared, complemented, tested, and used in logic computation.

2. Accumulator:

It is an 8-bit register.
It holds a data and receives the result of the arithmetic instructions.

3. B register:
An 8-bit general-purpose register.

4. Program Status Word:

Many instructions implicitly or explicitly afect (or are afected by) several status flags, which are
grouped together to form the Program Status Word.
It also used to select the memory bank.
5. Stack Pointer (SP):

The stack pointer register is 8 bit wide.

It is incremented before data is stored during PUSH and CALL instructions.
After reset the value of SP is 07H.

6. Data Pointer (DPTR):

The data pointer is a 16-bit register used to hold the 16-bit address of data memory.
This can also be used as two numbers of 8-bit data pointer namely DPH and DPL.
The 8-bit data pointers are used for accessing internal RAM and SFR.

The 16-bit data pointer is used for accessing external data memory.
The contents of data pointer are programmable using instructions.

7. Program Counter (PC):

It is a 16 bit register.
 PC is used, as address pointer to access program instructions and it is automatically
incremented after every byte of instruction fetch.

I/O Devices:

The 8051 has four numbers of 8-bit ports namely port-0, port- 1, port-2 and port-3.
Each port has a latch and driver (or buffer).
When external memory is employed the port-0 lines will function as multiplexed low byte
address/data lines and port-2 lines will function as high byte address lines.
Also the port pins P3.7 and P3.6 are used to output read and write control signals respectively.
The port-1 is dedicated I/O port and does not have any alternate function.
The ports are also mapped as internal memory in the controller and so they can be addressed as
memory locations for 8-bit operation.

Instruction Register (IR) & timing and control unit:

The 8051 has 8-bit ALU, which performs arithmetic and logical operations on binary data.
The A and B registers are used to hold the input data and the result of ALU operation.
The controller will fetch the instructions one by one, starting from the address stored in PC and
store in
IR, which decodes the instructions and give information to timing and control unit.
Using the information supplied by the IR unit the control signals necessary for internal and
external operations are generated by the timing and control unit.
 Timer/Counter:

The 8031/8051 has two 16-bit programmable timer/counter namely timer-1 and timer 0.
In the counter mode of operation they can count the number of high to low transitions of
the signal applied to the timer pins.
In timer mode of operation they can be independently programmed to work in any one of
the four operation modes. They are called mode-0, mode-1, mode-2 and mode-3.

Serial port:

The 8031/8051 has a serial data communication circuit that uses pins RXD (P3.0) and TXD (P3.0)
for connecting serial communication device.

Special function registers related to serial port are SBUF, SCON and PCON.

DATA TYPES AND DIRECTIVES:

DATA TYPES:

The 8051 microcontroller has only one data type. It is 8 bits, and the size of each
register is also 8 bits.

The data types used by the 8051 can be positive or negative.

DIRECTIVES (PSEUDOCODES):

Directives or assembler directives are instructions given to the assembler. The following are directives
used in 8051

DB (Define Byte):
It is used to define the 8-bit data.
When DB is used to define data, the numbers can be in decimal, binary, hex, or ASCII
formats.

Example: DATA1 DB 24 ; 1 byte of memory is assigned for variable DATA1 and set its value with
decimal 24
DATA2 DB 34H ; 1 byte of memory is assigned for variable DATA2 and set its value with hex
value 34
EQU (Equate):
This is used to define a constant without occupying a memory location
Example:

When executing the instruction MOV R3, #COUNT, the register R3 will be loaded with the
value 25.
ORG (Origin):
The ORG directive is used to indicate the beginning of the address.
The number that comes after ORG can be either in hex or in decimal. If the number is
not followed by H, it is decimal and the assembler will convert it to hex.

END:
Another important DIRECTIVE is the END directive.
This indicates to the assembler the end of the source (asm) file.
The END directive is the last line of an 8051 program, meaning that in the source code
anything after the END directive is ignored by the assembler.

REGISTER BANKS

The 8051 microcontroller has a total of 128 bytes of RAM.

Fig. 4.2 RAM allocation in 8051

There are 128 bytes of RAM in the 8051.

 The 128 bytes of RAM inside the 8051 are assigned addresses 00 to 7FH.
These 128 bytes are divided into three different groups as follows.
o A total of 32 bytes from locations 00 to 1F are set aside for register banks and
the stack.
A total of 16 bytes from locations 20H to 2FH are set aside for bit- addressable
read/write memory.

A total of 80 bytes from locations 30H to 7FH are used for read and write
storage, or what is normally called a scratch pad. These 80 locations of RAM are
widely used for the purpose of storing data and parameters by 8051 programmers.

Register Banks:

As mentioned earlier, a total of 32 bytes of RAM are set aside for the register banks and
stack.
These 32 bytes are divided into 4 banks of registers in which each bank has 8 registers,
RO R7.
The following shows how the 32 bytes are allocated into 4 banks:

Fig. 4.3 Register Banks

We can select register banks by use of the PSW (program status word) register.
Bits D4 and D3 of the PSW are used to select the desired register bank as:

STACK IN 8051
 The stack is a section of RAM used by the CPU to store information temporarily.
The register used to access the stack is called the SP (stack pointer) register.
The stack pointer in the 8051 is only 8 bits wide, which means that it can take values of 00 to
FFH.
When the 8051 is powered up, the SP register contains value 07.
The storing of a CPU register in the stack is called a PUSH, and pulling the contents of the stack
back into a CPU register is called a POP.
Pushing onto the stack
In the 8051 the stack pointer (SP) points to the last used location of the stack. As we
push data onto the stack, the stack pointer (SP) is incremented by one.
Popping from the stack
Popping the contents of the stack back into a given register is the opposite process of
pushing.
With every pop, the top byte of the stack is copied to the register specified by the
instruction and the stack pointer is decremented once.

INSTRUCTION SET
Data Transfer Instructions:

Arithmetic Instructions:
Logical Instructions:

Byte Level Logical Instructions:

Bit level Logical Instructions:

ANL C, bit address ; AND carry flag and the addressed bit
CPL C ; Complement Carry flag
CPL bit address ; Complement the bit by which the address is given.
CLR bit address ; Clear the bit by which the address is given.
SETB bit address ; Set the bit by which the address is given.

JUMP INSTRUCTIONS
Bit Jump Instructions:

Byte Jump Instructions:

 CALL INSTRUCTIONS

Timers / Counters

8051 has two 16-bit programmable UP timers/counters. They can be configured to operate either as timers
or as event counters. The names of the two counters are T0 and T1 respectively. The timer content is
available in four 8-bit special function registers, viz, TL0,TH0,TL1 and TH1 respectively.

In the "timer" function mode, the counter is incremented in every machine cycle. Thus, one can think of it
as counting machine cycles. Hence the clock rate is 1/12 th of the oscillator frequency.

In the "counter" function mode, the register is incremented in response to a 1 to 0 transition at its
corresponding external input pin (T0 or T1). It requires 2 machine cycles to detect a high to low
transition. Hence maximum count rate is 1/24 th of oscillator frequency.

The operation of the timers/counters is controlled by two special function registers, TMOD and TCON
respectively.

Timer Mode control (TMOD) Special Function Register:

TMOD register is not bit addressable.

TMOD
Address: 89 H

Various bits of TMOD are described as follows -

Gate: This is an OR Gate enabled bit which controls the effect of on START/STOP of Timer. It is
set to one ('1') by the program to enable the interrupt to start/stop the timer. If TR1/0 in TCON is set and
signal on pin is high then the timer starts counting using either internal clock (timer mode) or
external pulses (counter mode).

It is used for the selection of Counter/Timer mode.

Mode Select Bits:

M1 and M0 are mode select bits.

Timer/ Counter control logic:

 Fig 4.4 Timer/Counter Control Logic

Timer control (TCON) Special function register:

TCON is bit addressable. The address of TCON is 88H. It is partly related to Timer and partly to interrupt.

Fig 4.5 TCON Register

The various bits of TCON are as follows.

TF1 : Timer1 overflow flag. It is set when timer rolls from all 1s to 0s. It is cleared when processor vectors
to execute ISR located at address 001BH.
TR1 : Timer1 run control bit. Set to 1 to start the timer / counter.
TF0 : Timer0 overflow flag. (Similar to TF1)
TR0 : Timer0 run control bit.
IE1 : Interrupt1 edge flag. Set by hardware when an external interrupt edge is detected. It is cleared when
interrupt is processed.
IE0 : Interrupt0 edge flag. (Similar to IE1)
IT1 : Interrupt1 type control bit. Set/ cleared by software to specify falling edge / low level triggered
external interrupt.
IT0 : Interrupt0 type control bit. (Similar to IT1)
As mentioned earlier, Timers can operate in four different modes. They are as follows

Timer Mode-0:

In this mode, the timer is used as a 13-bit UP counter as follows.

 Fig. 4.6 Operation of Timer on Mode-0

The lower 5 bits of TLX and 8 bits of THX are used for the 13 bit count.Upper 3 bits of TLX are ignored.
When the counter rolls over from all 0's to all 1's, TFX flag is set and an interrupt is generated.

The input pulse is obtained from the previous stage. If TR1/0 bit is 1 and Gate bit is 0, the counter continues
counting up. If TR1/0 bit is 1 and Gate bit is 1, then the operation of the counter is controlled by input.
This mode is useful to measure the width of a given pulse fed to input.

Timer Mode-1:

This mode is similar to mode-0 except for the fact that the Timer operates in 16-bit mode.

Fig 4.7 Operation of Timer in Mode 1

Timer Mode-2: (Auto-Reload Mode)

This is a 8 bit counter/timer operation. Counting is performed in TLX while THX stores a constant value. In
this mode when the timer overflows i.e. TLX becomes FFH, it is fed with the value stored in THX. For
example if we load THX with 50H then the timer in mode 2 will count from 50H to FFH. After that 50H is
again reloaded. This mode is useful in applications like fixed time sampling.

Fig 4.8 Operation of Timer in Mode 2

Timer Mode-3:

Timer 1 in mode-3 simply holds its count. The effect is same as setting TR1=0. Timer0 in mode-3
establishes TL0 and TH0 as two separate counters.
 Fig 4.9 Operation of Timer in Mode 3

Control bits TR1 and TF1 are used by Timer-0 (higher 8 bits) (TH0) in Mode-3 while TR0 and TF0 are
available to Timer-0 lower 8 bits(TL0).

INTERRUPTS

8051 provides 5 vectored interrupts. They are -

1. ( External Interrupt 0)

2. TF0 ( Timer Interrupt 0)

3. ( External Interrupt 1)

4. TF1 ( Timer Interrupt 1)

5. RI/TI ( Serial Port Interrupt)

Out of these, and are external interrupts whereas Timer and Serial port interrupts are
generated internally. The external interrupts could be negative edge triggered or low level triggered.
All these interrupt, when activated, set the corresponding interrupt flags.

Each of these interrupts can be individually enabled or disabled by 'setting' or 'clearing' the
corresponding bit in the IE (Interrupt Enable Register) SFR. IE contains a global enable bit EA which
enables/disables all interrupts at once.

Interrupt Enable register (IE): Address: A8H

EX0 interrupt (External) enable bit

ET0 Timer-0 interrupt enable bit

EX1 interrupt (External) enable bit

ET1 Timer-1 interrupt enable bit

ES Serial port interrupt enable bit

ET2 Timer-2 interrupt enable bit

EA Enable/Disable all

Setting '1' Enable the corresponding interrupt

Setting '0' Disable the corresponding interrupt

Priority level structure:

Each interrupt source can be programmed to have one of the two priority levels by setting (high priority)
or clearing (low priority) a bit in the IP (Interrupt Priority) Register . A low priority interrupt can itself
be interrupted by a high priority interrupt, but not by another low priority interrupt. If two interrupts of
different priority levels are received simultaneously, the request of higher priority level is served. If the
requests of the same priority level are received simultaneously, an internal polling sequence determines
which request is to be serviced. Thus, within each priority level, there is a second priority level
determined by the polling sequence, as follows.

Interrupt Priority register (IP)

'0' low priority

'1' high priority

Interrupt handling:

When an interrupt comes and the program is directed to the interrupt vector address, the Program
Counter (PC) value of the interrupted program is stored (pushed) on the stack. The required Interrupt
Service Routine (ISR) is executed. At the end of the ISR, the instruction RETI returns the value of the
PC from the stack and the originally interrupted program is resumed.

Reset is a non-maskable interrupt. A reset is accomplished by holding the RST pin high for
at least two machine cycles.

Stepper motor interfacing with 8051

Stepper motor is one of the commonly used motors for precise angular movement.
The advantage of using a stepper motor is that the angular position of the motor shaft
can be controlled.
Similar to all the motors, stepper motors will have stator and rotor. Rotor has permanent
magnet and stator has coil.
The basic stepper motor has 4 coils with 90 degrees rotation step.
These four coils are activated in the cyclic order.

Step A B C D
0 1 1 0 0
1 0 1 1 0
2 0 0 1 1
 3 1 0 0 1

Interfacing Diagram:

Motor is connected to the port1 of the microcontroller through a driver IC.

The ULN2003 is a current driver IC. It is used to drive the current of the stepper motor
as it requires more current. It is an array of Darlington pairs.

Stepper motor has 6 pins. In these six pins, 2 pins are connected to the supply of 12V and the
remaining pins are connected to the output of current driver.

Program: