Cs3691-Unit 1

CS3691-Embedded Systems and IOT Prepared by: Mr E U Iniyan,AP/ECE
UNIT-1
8-BIT EMBEDDED PROCESSOR
PART-A
1. What is mean by microcontroller?
A device which contains the microprocessor with integrated peripherals like memory, serial
ports,parallel ports, timer/counter, interrupt controller, data acquisition interfaces like ADC,DAC is
called microcontroller.
2. Explain DJNZ instructions of intel 8051 microcontroller?
a) DJNZ Rn, rel
Decrement the content of the register Rn and jump if not zero.
b) DJNZ direct, rel
Decrement the content of direct 8-bit address and jump if not zero.
3. Specify the single instruction, which clears the most significant bit of B register of 8051,
without affecting the remaining bits.
Single instruction, which clears the most significant bit of B register of 8051, without affecting
the remaining bits is CLR B.7.
4.Explain the function of the pins PSEN and EA of 8051.
PSEN: PSEN stands for program store enable. In 8051 based system in which an external ROM
holdsthe program code, this pin is connected to the OE pin of the ROM.
EA: EA stands for external access. When the EA pin is connected to Vcc, program fetched to
addresses 0000H through 0FFFH are directed to the internal ROM and program fetches to
addresses1000H through FFFFH are directed to external ROM/EPROM. When the EA pin is
grounded, all addresses fetched by program are directed to the external ROM/EPROM.
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5. Explain the 16-bit registers DPTR and SP of 8051.
DPTR: DPTR stands for data pointer. DPTR consists of a high byte (DPH) and a low byte (DPL). Its
function is to hold a 16-bit address. It may be manipulated as a 16-bit data register or as two
independent 8-bit registers. It serves as a base register in indirect jumps, lookup table instructions and
external data transfer.
SP: SP stands for stack pointer. SP is a 8- bit wide register. It is incremented before data is stored
during PUSH and CALL instructions. The stack array can reside anywhere in on-chip RAM. The
stack pointer is initialized to 07H after a reset. This causes the stack to begin at location 08H.
6. What is stack pointer (sp)?
Stack pointer (SP) is a 8 bit wide register and is incremented before the data is stored into the stack
using PUSH or CALL instructions. It contains 8-bit stack top address. It is defined anywhere in the
on-chip 128-byte RAM. After reset, the SP register is initialized to 07. After each write to stack
operation, the 8-bit contents of the operand are stored onto the stack, after incrementing the SP register
by one. It is not a top-down data structure. It is allotted an address in the special function register
bank.
7. What is DPTR?
It is a 16-bit register that contains a higher byte (DPH) and lower byte (DPL) of a 16-bit
external data RAM address. It is accessed as a 16-bit register or two 8-bit registers. It has been
allotted two addresses in the special function register bank, for its two bytes DPH and DPL.
8. What are the different ways of operand addressing in 8051? (May/June 2016)
The five addressing modes are,
Immediate addressing
Register addressing
Direct addressing
Register indirect addressing
Indexed addressing.
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9. Mention the number of register banks and their addresses in 8051?
There are 4 register banks. They are Bank0, Bank1, Bank2& Bank3.
RAM locations from 00 to 07H for bank 0
RAM locations from 08 to 0FH for bank 1
RAM locations from 10 to 17H for bank 2
RAM locations from 18 to 1FH for bank 3
10.Compare Microprocessor and Microcontroller.
11. List the features of 8051 microcontroller?
The features are
Single supply +5 volt operation using HMOS technology.
4096 bytes program memory on chip(not on 8031)
128 data memory on chip.
Four register banks.

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Two multiple mode, 16-bit timer/counter.
Extensive Boolean processing capabilities.
64 KB external RAM size
12. List various instructions available in 8051 microcontroller
 Data Transfer Instructions

 Arithmetic Instructions
 Logical Instructions
 Boolean variable Manipulation Instructions
 Program and Machine Control Instructions
13. Write A Program To Save The Status Of Bits P1.2 And P1.3 On Ram Bit Locations 6 And 7
Respectively.
MOV C, P1.2 ; save status of P1.2 on CY
MOV O6, C ; save carry in RAM bit location 06
MOV C, p1.3 ; save status of p1.3 on CY
MOV 07, C ; save carry in RAM bit location 07.
14. What is SFR?
In the 8051 microcontroller registers A, B, PSW and DPTR are part of the group of registers commonly
referred to as special function registers (SFR)
15. Name the special functions registers available in 8051.
 Accumulator
 B Register
 Program Status Word.
 Stack Pointer.
 Data Pointer
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16. What are the Two Main Features of SFR Addresses?
The following two points should be noted SFR addresses.
I. The special function registers have addresses between 80H and FFH.
These addresses are above 80H, since the addresses 00 to 7FH are addresses of RAM memory inside the
8051.
II. Not all the address space of 80 to FH is used by the SFR. The unused locations 80Hto FFH are
reserved and must not used by the 8051 programmer.
17. Difference between a Timer and a Counter
The points that differentiate a timer from a counter are as follows −
Timer Counter
The register incremented for every The register is incremented considering 1 to 0 transition
machine cycle. at its corresponding to an external input pin (T0, T1).
Maximum count rate is 1/12 of the Maximum count rate is 1/24 of the oscillator frequency.
oscillator frequency.
A timer uses the frequency of the A counter uses an external signal to count pulses.
internal clock, and generates delay.
18. What is Program Status Word?
The PSW or Program Status Word Register is also called as Flag Register and is one of the important
SFRs. The PSW Register consists of Flag Bits, which help the programmer in checking the condition of
the result and also make decisions.
Flags are 1-bit storage elements that store and indicate the nature of the result that is generated by
execution of certain instructions. The following image shows the contents of the PSW Register.
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19. What is a serial data buffer?
Serial data buffer is a special function register and it initiates serial transmission when byte is written
to it and if read, it reads received serial data. It contains two independent registers internally. One of
them is a transmit buffer, which is a parallel-in serial-out register. The other isa receive buffer, which
is a serial-in parallel-out register
20. What are timer registers?
Timer registers are two 16-bit registers and can be accessed as their lower and upper bytes. TLO
represents the lower byte of the timing register 0, while THO represents higher bytes of the timing
register 0. Similarly,TLI and THI represent lower and higher bytes of timing register 1. These
registers can be accessed using the four addresses allotted to them, which lie in the special function
registers address range, i.e., 801 H to FF.
21. What is the use of timing and control unit?
Timing and control unit is used to derive all the necessary timing and control signals required for
the internal operation of the circuit. It also derives control signals that are required for controlling
the external system bus.
22. When are timer overflow bits set and reset?
The timer overflow bits are set when timer rolls over and reset either by the execution of an RET
instruction or by software, manually clearing the bits. The bits are located in the TCON register
along with timer run control (TRn) bits.
23. Explain the mode (0 and1) operation of the timer.
The operations are as follows:
• Timer mode 0 and 1 operations are similar for the 13 bit (mode) or 16 bit (mode 1) counter.
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When the timer reaches the limits of the count, the overflow flag is set and the counter is reset back
to zero.
• The modes 0 and 1 can be used to time external events.
• They can be used as specific time delays by loading them with an initial value before allowing
them to execute and overflow.
24. What is the different modes in which timer 2 can operate?
The two different modes in which Timer 2 operates are.
i. Capture mode-Timer 2 operates as free running clocks, which saves the timers value on each
high to low transition. It can be used for recording bit lengths when receiving Manchester-encoded
data.
ii. Auto-reload mode:-When the timer overflows, value is written into TH2/TL2 registers from
RCA P2H/RCA P21 registers. This feature is used to implement a system watch dog timer.
25. What is Polling ? What are the different types of Polling?
Polling is a scheme or an algorithm to identify the devices interrupting the processor. Polling is
employed when multiple devices interrupt the processor through one interrupt pin of the
processor. The polling can be classified into software and hardware polling. In software polling
the entire polling process is govern by a prograrn.1n hardware polling, the hardware takes care of
checking the status of interrupting devices and allowing one by one to the processor.
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PART-B
1) With neat block diagram, explain the architecture of 8051 Microcontroller.

ARCHITECTURE OF 8051 MICRO CONTROLLER:
Fig: Block Diagram of 8051 Micro Controller
8051 microcontroller is designed by Intel in 1981. It is an 8-bit microcontroller. It is

built with 40 pins DIP (dual inline package) and it consists of
 CPU
 4kilo bytes of On chip ROM
 128 bytes of RAM storage
 Two 16-bit timers
 Four parallel I/O ports,
 On-chip crystal oscillator
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 Interrupt Control
 Serial Port
Basic components present internally inside 8051 Microcontroller architecture are:
a) CPU (Central Processing Unit): CPU act as a mind of any processing machine. It synchronizes
and manages all processes that are carried out in microcontroller. User has no power to control
the functioning of CPU. It interprets the program stored in ROM and carries out from storage and
then performs it projected duty. CPU manage the different types of registers available in 8051
microcontroller.
b) Memory: For operation Micro-controller required a program. This program guides the
microcontroller to perform the specific tasks. This program installed in microcontroller required
some on chip memory for the storage of the program.
Microcontroller also required memory for storage of data and operands for the short duration. In
microcontroller 8051 there is code or program memory of 4 KB that is it has 4 KB ROM and it also
comprise of data memory (RAM) of 128 bytes.
c) Bus : Bus is a group of wires which uses as a communication canal or acts as means of data
transfer. The different bus configuration includes 8, 16 or more cables. Therefore, a bus can bear
8 bits, 16 bits all together.
Types of buses in 8051 Microcontroller:
Let's see the two types of bus used in 8051 microcontroller:
o Address Bus: 8051 microcontrollers is consisting of 16 bit address bus. It is generally be used
for transferring the data from Central Processing Unit to Memory.
o Data bus: 8051 microcontroller is consisting of 8 bits data bus. It is generally be used for
transferring the data from one peripherals position to other peripherals.
o
d) Timers of 8051 and their Associated Registers
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The 8051 has two timers, Timer 0 and Timer 1. They can be used as timers or as event counters. Both
Timer 0 and Timer 1 are 16-bit wide. Since the 8051 follows an 8-bit architecture, each 16 bit is accessed
as two separate registers of low-byte and high-byte.
Timer 0 Register
The 16-bit register of Timer 0 is accessed as low- and high-byte. The low-byte register is called TL0
(Timer 0 low byte) and the high-byte register is called TH0 (Timer 0 high byte). These registers can be
accessed like any other register.
Timer 1 Register
The 16-bit register of Timer 1 is accessed as low- and high-byte. The low-byte register is called TL1
(Timer 1 low byte) and the high-byte register is called TH1 (Timer 1 high byte). These registers can be
accessed like any other register.
e) I/O Ports:
8051 microcontrollers have 4 I/O ports each of 8-bit, which can be configured as input or output. Hence,
total 32 input/output pins allow the microcontroller to be connected with the peripheral devices.
f) Oscillator: As the microcontroller is digital circuit therefore it needs timer for their operation. To
perform timer operation inside microcontroller it required externally connected or on-chip
oscillator. Microcontroller is used inside an embedded system for managing the function of
devices. Therefore, 8051 uses the two 16 bit counters and timers. For the operation of this timers
and counters the oscillator is used inside microcontroller.
g) Interrupts: Interrupts is a sub-routine call that given by the microcontroller when some other
program with high priority is request for acquiring the system buses the n interrupts occur in
current running program.
Interrupts provide a method to postpone or delay the current process, performs a sub-routine task
and then restart the standard program again.
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Let's see the five sources of interrupts in 8051 Microcontroller:
o Timer 0 overflow interrupt - TF0

o Timer 1 overflow interrupt - TF1
o External hardware interrupt - INT0
o External hardware interrupt - INT1
o Serial communication interrupt - RI/TI
2) Explain in detail about various types of interrupt in 8051 Microcontroller:
INTERRUPTS IN 8051:
In most of the real-time processes, to handle certain conditions properly, the actual task must be halt for
some time – it takes required action – and then must return to the main task. For executing such type of
programs, interrupts are necessary.
Types of interrupts in 8051
1. External hardware interrupt – INT0
2. External hardware interrupt – INT1
3. Timer 0 overflow interrupt – TF0
4. Timer 1 overflow interrupt – TF1
5. Serial communication interrupt – RI/TI
Timer and serial interrupts are internally generated by the inbuilt timer and USART peripherals
modules.
External interrupts are generated by external interfacing devices such as switches, number pad, RTC
etc.
When an interrupt occurs, the microcontroller first finishes the instruction that it is executing and then
jumps to the memory location corresponding to the interrupt. This memory location is also known as an
interrupt vector. 8051 microcontroller has fixed interrupt vectors for each interrupt as shown in the
below table.
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Interrupt number Description Memory Address
0 External hardware interrupt INT0 0003h
1 Timer/Counter 0 interrupt 000Bh
2 External hardware interrupt INT1 0013h
3 Timer/Counter 1 interrupt 001Bh
4 Serial communication interrupt 0023h
Fig: 8051 Microcontroller Interrupts Table
Interrupt Priority
In 8051, each interrupt can have either high priority or low priority. The priority level of an interrupt
can be set to high by setting the corresponding bit in Interrupt Priority (IP) register or it can be set to
low by clearing the corresponding bit in the Interrupt Priority (IP) register.
(MSB) IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 (LSB) IP.0
Direct Address B8H – – PT2 PS PT1 PX1 PT0 PX0
Bit Address BF BE BD BC BB BA B9 B8
Fig:Interrupt Priority (IP) Register
Bit 7: Reserved
Bit 6: Reserved
Bit 5: PT2 0: Low priority for Timer 2 interrupt

1: High priority for Timer 2 interrupt
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Bit 4: PS 0: Low priority for Serial interrupt

1: High priority for Serial interrupt

Bit 2: PX1 0: Low priority for External interrupt INT1

1: High priority for External interrupt INT1

Bit 0: PX0 0: Low priority for External interrupt INT0

1: High priority for External interrupt INT0
Fig:Interrupt Priority (IP) Register bits
If multiple interrupts of different priority level are received simultaneously then high priority interrupt
is serviced first. If requests of the same priority level are received simultaneously, an internal polling
sequence determines which request is to be serviced, Thus within each priority level is a second priority
structure determined by the polling sequence. Polling sequence is shown in table below.
S No Source Priority within Level
1 External hardware interrupt INT0 Highest
2 Timer/Counter 0 interrupt
3 External hardware interrupt INT1
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4 Timer/Counter 1 interrupt
5 Serial communication interrupt Lowest
Fig: 8051 Microcontroller Interrupt Priority Order
A combination of Interrupt Priority (IP) register and polling sequence gives unique priorities to all 5
interrupts in the 8051 microcontrollers. If all bits in Interrupt Priority (IP) register are cleared then
external interrupt INT0 will have highest priority, timer 0 will be next and serial communication interrupt
will have lowest priority. If multiple interrupts are triggered at same time, then the interrupts are serviced
according to priority. For instance, if external hardware interrupt INT1 and external hardware interrupt
INT0 are triggered at exactly the same time, then external hardware interrupt INT0 will be serviced first.
Enabling Interrupt
Upon reset, all interrupts are disabled (masked), meaning that the microcontroller will respond to none
if any activated. The interrupts must be enabled by software in order for the microcontroller to respond
to them. There is a register called IE (interrupt enable) that is responsible for enabling (unmasking) and
disabling (masking) the interrupts.
In the 8051 microcontroller, interrupts can be enabled or disabled by setting or clearing corresponding
bits in Interrupt Enable (IE) Register. Also all interrupts can be enabled or disabled globally using EA
bit in Interrupt Enable (IE) register.
(MSB) IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 (LSB) IE.0
Direct Address A8H EA – ET2 ES ET1 EX1 ET0 EX0
Bit Address AF AE AD AC AB AA A9 A8
Fig: Interrupt Enable (IE) Register
Bit 7: EA 0: Disable all interrupts
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1: Enable all interrupts according to individual enable bits
Bit 6: Reserved
Bit 5: ET2 0: Disable Timer 2 interrupt

1: Enable Timer 2 interrupt
Bit 4: ES 0: Disable Serial interrupt

1: Enable Serial interrupt

Bit 2: EX1 0: Disable External interrupt INT1

1: Enable External interrupt INT1

Bit 0: EX0 0: Disable External interrupt INT0

1: Enable External interrupt INT0
Fig: Interrupt Enable (IE) Register Bits
.
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3) Explain in detail about Programming Parallel Ports.
8051 microcontrollers have 4 I/O ports each of 8-bit, which can be configured as input or output. Hence,
total 32 input/output pins allow the microcontroller to be connected with the peripheral devices.
 Pin configuration, i.e. the pin can be configured as 1 for input and 0 for output as per the logic
state.
o Input/Output (I/O) pin − All the circuits within the microcontroller must be connected to
one of its pins except P0 port because it does not have pull-up resistors built-in.
o Input pin − Logic 1 is applied to a bit of the P register. The output FE transistor is turned
off and the other pin remains connected to the power supply voltage over a pull-up resistor
of high resistance.
 Port 0 − The P0 (zero) port is characterized by two functions −
o When the external memory is used then the lower address byte (addresses A0A7) is
applied on it, else all bits of this port are configured as input/output.
o When P0 port is configured as an output then other ports consisting of pins with built-in pull-up resistor
connected by its end to 5V power supply, the pins of this port have this resistor left out.
Fig: Port-0 Structure
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Port-0 can be configured as a normal bidirectional I/O port or it can be used for address/data interfacing
for accessing external memory. When control is '1', the port is used for address/data interfacing. When
the control is '0', the port can be used as a normal bidirectional I/O port.
Let us assume that control is '0'. When the port is used as an input port, '1' is written to the latch.
In this situation both the output MOSFETs are 'off'. Hence the output pin floats. This high impedance
pin can be pulled up or low by an external source. When the port is used as an output port, a '1' written
to the latch again turns 'off' both the output MOSFETs and causes the output pin to float. An external
pull-up is required to output a '1'. But when '0' is written to the latch, the pin is pulled down by the lower
MOSFET. Hence the output becomes zero.
When the control is '1', address/data bus controls the output driver MOSFETs. If the address/data bus
(internal) is '0', the upper MOSFET is 'off' and the lower MOSFET is 'on'. The output becomes '0'. If the
address/data bus is '1', the upper transistor is 'on' and the lower transistor is 'off'. Hence the output is '1'.
Hence for normal address/data interfacing (for external memory access) no pull-up resistors are required.
Port-0 latch is written to with 1's when used for external memory access
2.Port-1:
Port-1 Pin Structure Port-1 has 8 pins (P1.1-P1.7) .The structure of a port-1 pin is shown in fig below.
Fig : Port 1 Structure
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Port-1 does not have any alternate function i.e. it is dedicated solely for I/O interfacing. When used as
output port, the pin is pulled up or down through internal pull-up. To use port-1 as input port, '1' has to
be written to the latch. In this input mode when '1' is written to the pin by the external device then it read
fine. But when '0' is written to the pin by the external device then the external source must sink current
due to internal pull-up. If the external device is not able to sink the current the pin voltage may rise,
leading to a possible wrong reading.
3.Port-2:
PORT 2 Pin Structure Port-2 has 8-pins (P2.0-P2.7) . The structure of a port-2 pin is shown in figure
below:
Fig: Port-3 Structure
Port-2 is used for higher external address byte or a normal input/output port. The I/O operation is similar
to Port-1. Port-2 latch remains stable when Port-2 pin are used for external memory access. Here again
due to internal pull-up there is limited current driving capability.
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4. Port-3:
Port-3 has 8 pin (P3.0-P3.7). Port-3 pins have alternate functions. The structure of a port-3 pin is shown
in figure
Fig 4: Port-3 Structure
Each pin of Port-3 can be individually programmed for I/O operation or for alternate function. The
alternate function can be activated only if the corresponding latch has been written to '1'. To use the port
as input port, '1' should be written to the latch. This port also has internal pull-up and limited current
driving capability.
4) Briefly explain the instruction set of 8051
8051 Instructions
8051 has about 111 instructions. These can be grouped into the following categories
1. Arithmetic Instructions
2. Logical Instructions
3. Data Transfer instructions
4. Boolean Variable Instructions
5. Program Branching Instructions
The following nomenclatures for register, data, address and variables
are used while write instructions.
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A: AccuulatorB: "B" register C: Carry bit

Rn: Register R0 - R7 of the currently selected register bank
Direct: 8-bit internal direct address for data. The data could be in lower
128bytes of RAM (00 - 7FH) or it could be in the special function
register (80 - FFH).
@Ri: 8-bit external or internal RAM address available in register
R0 or R1. This is used for indirect addressing mode.
#data8: Immediate 8-bit data available in the
instruction. #data16: Immediate 16-bit data
available in the instruction.
Addr11: 11-bit destination address for short absolute jump. Used by
instructions AJMP & ACALL. Jump range is 2 kbyte (one page).
Addr16: 16-bit destination address for long call or long jump.
Rel: 2's complement 8-bit offset (one - byte) used for short jump (SJMP)
and all conditional jumps.
bit: Directly addressed bit in internal RAM or SFR
 Arithmetic Instructions
Mnemonics Description Byte Instruction
Cycles s
ADD A, Rn A A + Rn 1 1
ADD A, direct A A + (direct) 2 1
ADD A, @Ri A A + @Ri 1 1
ADD A, #data A A + data 2 1
ADDC A, Rn A A + Rn + C 1 1
ADDC A, direct A A + (direct) + C 2 1
ADDC A, @Ri A A + @Ri + C 1 1
ADDC A, #data A A + data + C 2 1
DA A Decimal adjust accumulator 1 1
DIV AB Divide A by
BA quotient 1 4
B remainder
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DEC A A A -1 1 1
DEC Rn Rn Rn - 1 1 1
DEC direct (direct) (direct) - 1 2 1
DEC @Ri @Ri @Ri - 1 1 1
INC A A A+1 1 1
INC Rn Rn Rn + 1 1 1
INC direct (direct) (direct) + 1 2 1
INC @Ri @Ri @Ri +1 1 1
INC DPTR DPTR DPTR +1 1 2
MUL AB Multiply A by B
A low byte (A*B) 1 4
B high byte (A* B)

SUBB A,
A A - Rn - C 1 1
Rn
SUBB A, A A - (direct) - C 2 1
direct SUBB A A - @Ri - C 1 1
A, @Ri A A - data - C 2 1
SUBB A,
#data
 Logical
Instructions Descriptio Byte Instruction Cycles
n s
Mnemonics
ANL A, Rn A A AND Rn 1 1
ANL A, direct A A AND (direct) 2 1
ANL A, @Ri A A AND @Ri 1 1
ANL A, #data A A AND data 2 1
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ANL direct, A (direct) (direct) AND A 2 1

ANL direct, #data (direct) (direct) AND data 3 2
CLR A A 00H 1 1
CPL A A A 1 1
ORL A, Rn A A OR Rn 1 1
ORL A, direct A A OR (direct) 1 1
ORL A, @Ri A A OR @Ri 2 1
ORL A, #data A A OR data 1 1
ORL direct, A (direct) (direct) OR A 2 1
ORL direct, #data (direct) (direct) OR data 3 2
RL A Rotate accumulator left 1 1
RLC A Rotate accumulator left through 1 1
carry
RR A Rotate accumulator right 1 1
RRC A Rotate accumulator right 1 1
through carry
SWAP A Swap nibbles within 1 1
Acumulator
XRL A, Rn A A EXOR Rn 1 1
XRL A, direct A A EXOR (direct) 1 1
XRL A, @Ri A A EXOR @Ri 2 1
XRL A, #data A A EXOR data 1 1
XRL direct, A (direct) (direct) EXOR A 2 1
XRL direct, #data (direct) (direct) EXOR data 3 2
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Data Transfer Instructions

Mnemonics Description Bytes Instructio
n Cycles
MOV A, Rn A Rn 1 1
MOV A, direct A (direct) 2 1
MOV A, @Ri A @Ri 1 1
MOV A, #data A data 2 1
MOV Rn, A Rn A 1 1
MOV Rn, direct Rn (direct) 2 2
MOV Rn, #data Rn data 2 1
MOV direct, A (direct) A 2 1
MOV direct, Rn (direct) Rn 2 2
MOV direct1, (direct1) (direct2) 3 2
direct2
MOV direct, @Ri (direct) @Ri 2 2
MOV direct, #data (direct) #data 3 2
MOV @Ri, A @Ri A 1 1
MOV @Ri, direct @Ri (direct 2 2
)
MOV @Ri, #data @Ri Data 2 1
MOV DPTR, DPTR data16 3 2
#data16
MOVC A, A Code byte pointed by A + 1 2
DPTR @A+DPTR
MOVC A, A Code byte pointed by A + 1 2
PC @A+PC
MOVC A, @Ri A Code byte pointed by Ri 8-bit 1 2
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address)
MOVX A, A External data pointed by DPTR 1 2
@DPTR
MOVX @Ri, A @Ri A (External data - 8bit address) 1 2
MOVX @DPTR, A PUSH direct (SP) (direct) 2 2
@DPTR A(External data - 16bit 1 2
address)
POP direct (direct) (SP) 2 2
XCH Rn Exchange A with Rn 1 1
XCH direct Exchange A with direct byte 2 1
XCH @Ri Exchange A with indirect RAM 1 1
XCHD A, @Ri Exchange least significant nibble of A 1 1
with that of indirect RAM
Boolean Variable Instructions
Mnemonics Description Byte Instruction
s Cycles
CLR C C-bit 0 1 1
CLR bit bit 0 2 1
SET C C 1 1 1
SET bit bit 1 2 1
CPL C C 1 1
CPL bit Bit 2 1
ANL C, /bit C C. 2 1
ANL C, bit C C. bit 2 1
ORL C, /bit C C+ 2 1
ORL C, bit C C + bit 2 1
MOV C, bit C bit 2 1
MOV bit, C bit C 2 2
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Program Branching Instructions

Mnemonics Description Byte Instructio
s n
Cycles
ACALL addr11 PC + 2 (SP); addr 11 PC 2 2
AJMP addr11 Addr11 PC 2 2
CJNE A, direct, rel Compare with A, jump (PC + rel) if 3 2
not equal
CJNE A, #data, rel Compare with A, jump (PC + rel) if 3 2
not
Equal
CJNE Rn, #data, rel Compare with Rn, jump (PC + rel) if 3 2
not
Equal
CJNE @Ri, #data, Compare with @Ri A, jump (PC + 3 2
rel rel) if
not equal
DJNZ Rn, rel Decrement Rn, jump if not zero 2 2
DJNZ direct, rel Decrement (direct), jump if not 3 2
zero
JC rel Jump (PC + rel) if C bit = 1 2 2
JNC rel Jump (PC + rel) if C bit = 0 2 2
JB bit, rel Jump (PC + rel) if bit = 1 3 2
JNB bit, rel Jump (PC + rel) if bit = 0 3 2
JBC bit, rel Jump (PC + rel) if bit = 1 3 2
JMP @A+DPTR A+DPTR PC 1 2
JZ rel If A=0, jump to PC + rel 2 2
JNZ rel If A ≠ 0 , jump to PC + rel 2 2
LCALL addr16 PC + 3 (SP), addr16 PC 3 2
LJMP addr 16 Addr16 PC 3 2
NOP No operation 1 1
25 | P a g e
RET (SP) PC 1 2
RETI (SP) PC, Enable Interrupt 1 2
SJMP rel PC + 2 + rel PC 2 2
JMP @A+DPTR A+DPTR PC 1 2
JZ rel If A = 0. jump PC+ rel 2 2
JNZ rel If A ≠ 0, jump PC + rel 2 2
NOP No operation 1 1
5) Explain about 8051 Addressing Modes with examples
8051 has four addressing modes.
1. Immediate Addressing:
Data is
immediately
available in the
instruction. For
example -
ADD A, #77; Adds 77 (decimal) to A and stores in A
ADD A, #4DH; Adds 4D (hexadecimal) to A and stores in A MOV DPTR, #1000H;
Moves 1000 (hexadecimal) to data pointer
2. Bank Addressing or Register Addressing:

This way of addressing accesses the bytes in the current register bank.
Data is available in the register specified in the instruction. The
register bank is decided by 2 bits of Processor Status
Word (PSW). For example-

ADD A, R0; Adds content of R0 to A and stores in A
3. Direct Addressing:
The address of the data is available in the instruction. For example -
MOV A, 088H; Moves content of SFR TCON (address 088H)to A
4. Register Indirect Addressing:
26 | P a g e
The address of data is available in the R0 or R1 registers as

specified in the instruction. For example - MOV A, @R0 moves
content of address pointed by R0 to A .
5. External Data Addressing:
Pointer used for external data addressing can be either R0/R1 (256 byte access) or
DPT
MOVX A, @R0; Moves content of 8-bit address

pointed by R0 to A MOVX A, @DPTR; Moves
content of 16-bit address pointed by DPTR to A
6. External Code Addressing:

Sometimes we may want to store non-volatile data into the ROM e.g.
look-up tables. Such data may require reading the code memory. This
may be done as follows -
MOVC A, @A+DPTR; Moves content of address pointed by A+DPTR to A
MOVC A, @A+PC; Moves content of address pointed by A+PC to A
6)Explain the Timer/Counter operation of 8051.
A timer is a specialized type of clock which is used to measure time intervals. A timer that counts
from zero upwards for measuring time elapsed is often called a stopwatch. It is a device that counts
down from a specified time interval and used to generate a time delay, for example, an hourglass
is a timer.
A counter is a device that stores (and sometimes displays) the number of times a particular event
or process occurred, with respect to a clock signal. It is used to count the events happening outside
the microcontroller. In electronics, counters can be implemented quite easily using register-type
circuits such as a flip-flop.
27 | P a g e
Timers of 8051 and their Associated Registers
The 8051 has two timers, Timer 0 and Timer 1. They can be used as timers or as event counters.
Both Timer 0 and Timer 1 are 16-bit wide. Since the 8051 follows an 8-bit architecture, each 16
bit is accessed as two separate registers of low-byte and high-byte.
Timer 0 Register
The 16-bit register of Timer 0 is accessed as low- and high-byte. The low-byte register is called
TL0 (Timer 0 low byte) and the high-byte register is called TH0 (Timer 0 high byte).
Timer 1 Register
The 16-bit register of Timer 1 is accessed as low- and high-byte. The low-byte register is called
TL1 (Timer 1 low byte) and the high-byte register is called TH1 (Timer 1 high byte).
The Gate flags in TMOD decide whether counting will be gated by the corresponding external
interrupt pin in P3. If the Gate Flag is cleared, the counter is enabled by the TR flag alone. If the
Gate flag is set, counting also requires the corresponding external interrupt pin in P3 to be HIGH.
This is useful for measuring pulse widths
28 | P a g e
TMOD (Timer Mode) Register
Both Timer 0 and Timer 1 use the same register to set the various timer operation modes. It is an
8-bit register in which the lower 4 bits are set aside for Timer 0 and the upper four bits for Timers.
In each case, the lower 2 bits are used to set the timer mode in advance and the upper 2 bits are
used to specify the location.
Gate − When set, the timer only runs while INT(0,1) is high.
C/T − Counter/Timer select bit.
M1 − Mode bit 1.
M0 − Mode bit 0.
GATE
Every timer has a means of starting and stopping. Some timers do this by software, some by
hardware, and some have both software and hardware controls. 8051 timers have both software
and hardware controls. The start and stop of a timer is controlled by software using the
instruction SETB TR1 and CLR TR1 for timer 1, and SETB TR0 and CLR TR0 for timer 0.
The SETB instruction is used to start it and it is stopped by the CLR instruction. These instructions
start and stop the timers as long as GATE = 0 in the TMOD register. Timers can be started and
stopped by an external source by making GATE = 1 in the TMOD register.
C/T (CLOCK / TIMER)
This bit in the TMOD register is used to decide whether a timer is used as a delay generator or
an event manager. If C/T = 0, it is used as a timer for timer delay generation. The clock source to
29 | P a g e
create the time delay is the crystal frequency of the 8051. If C/T = 0, the crystal frequency attached
to the 8051 also decides the speed at which the 8051 timer ticks at a regular interval.
Timer frequency is always 1/12th of the frequency of the crystal attached to the 8051. Although
various 8051 based systems have an XTAL frequency of 10 MHz to 40 MHz, we normally work
with the XTAL frequency of 11.0592 MHz. It is because the baud rate for serial communication
of the 8051.XTAL = 11.0592 allows the 8051 system to communicate with the PC with no errors.
M1 / M2
M1 M2 Mode
0 0 13-bit timer mode.
0 1 16-bit timer mode.
1 0 8-bit auto reload mode.
1 1 Spilt mode.
Timer Control Register (TCON)
(MSB) TCON. TCON. TCON. TCON. TCON. TCON. (LSB)

TCON. 6 5 4 3 2 1 TCON.
7 0
Direct TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Addres
s 88H
Bit 8F 8E 8D 8C 8B 8A 89 88
Addres
s
Fig: Timer Control (TCON) Register
30 | P a g e
Bit 7: Timer 1 overflow bit set by the controller when timer 1 overflows.
TF1 Cleared when processor vectors to execute interrupt service routine located at
program address 001Bh.
Bit 6: 0: Turn Off Timer 1

TR1 1: Turn On Timer 1
Bit 5: Timer 0 overflow bit set by controller when timer 0 overflows.

TF0 Cleared when processor vectors to execute interrupt service routine located at
program address 000Bh.
Bit 4: 0: Turn Off Timer 0

TR0 1: Turn On Timer 0
Bit 3: External interrupt 1 Edge flag. Set to 1 when a high-to-low edge signal is
IE1 received on port 3.3 (INT1).
Cleared when processor vectors to interrupt service routine at program address
0013h. Not related to timer operations..0
.ma
Bit 2: 0: External interrupt INT1 triggered on low level

IT1 1: External interrupt INT1 triggered on falling edge
Bit 1: External interrupt 0 Edge flag. Set to 1 when a high-to-low edge signal is
IE0 received on port 3.2 (INT0).
Cleared when processor vectors to interrupt service routine at program address
0003h. Not related to timer operations.
31 | P a g e
Bit 0: 0: External interrupt INT0 triggered on low level

IT0 1: External interrupt INT0 triggered on falling edge
Fig: Timer Control (TCON) Register Bits
TF0 and TF1 bits of the TCON register are set by the controller when all bits of timer 0 or timer 1
rollover from 1 to 0. TF0 and TF1 bits can be polled to detect timer overflow event. These bits are
automatically cleared when the processor executes the interrupt service routine (ISR) located at
the respective timer vector address.
TR0 and TR1 bits are used to run or stop timer 0 and timer 1 respectively
7)Explain various Modes of Operation of Timers

Mode 0 (13-Bit Timer Mode)
Both Timer 1 and Timer 0 in Mode 0 operate as 8-bit counters (with a divide-by-32 prescaler).
Timer register is configured as a 13-bit register consisting of all the 8 bits of TH1 and the lower 5
bits of TL1. The upper 3 bits of TL1 are indeterminate and should be ignored. Setting the run flag
(TR1) does not clear the register. The timer interrupt flag TF1 is set when the count rolls over from
all 1s to all 0s. Mode 0 operation is the same for Timer 0 as it is for Timer 1.
Mode 1 (16-Bit Timer Mode)
Timer mode "1" is a 16-bit timer and is a commonly used mode. It functions in the same way as
13-bit mode except that all 16 bits are used. TLx is incremented starting from 0 to a maximum
255. Once the value 255 is reached, TLx resets to 0 and then THx is incremented by 1. As being a
full 16-bit timer, the timer may contain up to 65536 distinct values and it will overflow back to 0
after 65,536 machine cycles.
32 | P a g e
Mode 2 (Auto Reload Mode)
Both the timer registers are configured as 8-bit counters (TL1 and TL0) with automatic reload.
Overflow from TL1 (TL0) sets TF1 (TF0) and also reloads TL1 (TL0) with the contents of Th1
(TH0), which is preset by software. The reload leaves TH1 (TH0) unchanged.
The benefit of auto-reload mode is that you can have the timer to always contain a value from 200
to 255. If you use mode 0 or 1, you would have to check in the code to see the overflow and, in
that case, reset the timer to 200. In this case, precious instructions check the value and/or get
reloaded. In mode 2, the microcontroller takes care of this. Once you have configured a timer in
33 | P a g e
mode 2, you don't have to worry about checking to see if the timer has overflowed, nor do you
have to worry about resetting the value because the microcontroller hardware will do it all for you.
The auto-reload mode is used for establishing a common baud rate.
Mode 3 (Split Timer Mode)
Timer mode "3" is known as split-timer mode. When Timer 0 is placed in mode 3, it becomes
two separate 8-bit timers. Timer 0 is TL0 and Timer 1 is TH0. Both the timers count from 0 to 255
and in case of overflow, reset back to 0. All the bits that are of Timer 1 will now be tied to TH0.
When Timer 0 is in split mode, the real Timer 1 (i.e. TH1 and TL1) can be set in modes 0, 1 or 2,
but it cannot be started/stopped as the bits that do that are now linked to TH0. The real timer 1 will
be incremented with every machine cycle.
Initializing a Timer.3
Decide the timer mode. Consider a 16-bit timer that runs continuously, and is independent of any
external pins.
Initialize the TMOD SFR. Use the lowest 4 bits of TMOD and consider Timer 0. Keep the two
bits, GATE 0 and C/T 0, as 0, since we want the timer to be independent of the external pins. As
16-bit mode is timer mode 1, clear T0M1 and set T0M0. Effectively, the only bit to turn on is bit
0 of TMOD
7))Explain briefly about Serial port of 8051 and its registers.
8051 has built-in UART with RXD (serial data receive pin) and TXD (serial data transmit pin) on
PORT3.0 and PORT3.1 respectively.
34 | P a g e
Serial port consists of registers:
1.SBUF(Serial Data Buffer) Register
2.SCON(Serial Control) Register
3.PCON(Power Control) Register.
SBUF register
Its an 8 bit register used solely for serial communication in 8051. For a byte of data to be
transferred via TxD line, it muse be placed in SBUF register. Similarly SBUF register holds the
serially inputed data received by TxD line of 8051.
The moment the byte is written in SBUF, it is framed with start and stop bits and transferred
serially through TxD line.
Similarly when bits are received serially via RxD it is deframed by eliminating stop and start bits
and a byte of data is received and placed in SBUF.
SCON: Serial Control Register
Serial control register SCON is used to set serial communication operation modes. Also it is used
to control transmit and receive operations.
Bit 7:6 - SM0:SM1: Serial Mode Specifier
Mode SM0 SM1 Mode
0 0 0 1/12 of Oscillator frequency shift register mode fixed baud rate
1 0 1 8-bit UART with timer 1 determined baud rate
2 1 0 9-bit UART with 1/32 of Oscillator fixed baud rate
3 1 1 9-bit UART with timer 1 determined baud rate
35 | P a g e
Normally mode-1 (SM0 =0, SM1=1) is used with 8 data bits, 1 start bit, and 1 stop bit.
Bit 5 - SM2: for Multiprocessor Communication
This bit enables a multiprocessor communication feature in mode 2 & 3.
Bit 4 - REN: Receive Enable
1 = Receive enable
0 = Receive disable
Bit 3 - TB8: 9th Transmit Bit
This is the 9th bit which is to be transmitted in mode 2 & 3 (9-bit mode)
Bit 2 - RB8: 9th Receive Bit
This is the 9th received bit in mode 2 & 3 (9-bit mode), whereas in mode 1 if SM2 = 0 then RB8
hold the stop bit that received
Bit 1 - TI: Transmit Interrupt Flag
This bit indicates the transmission is complete and gets set after transmitting the byte from the
buffer. Normally TI (Transmit Interrupt Flag) is set by hardware at the end of the 8th bit in mode
0 and at the beginning of stop bit in other modes.
Bit 0 – RI: Receive Interrupt Flag
This bit indicates reception is complete and gets set after receiving the complete byte in the
buffer. Normally RI (Receive Interrupt Flag) is set by hardware in receiving mode at the end of
the 8th bit in mode 0 and at the stop bit receive time in other modes.
PCON Register: Power control register
PCON (Power Control) register is used to force the 8051 microcontrollers into power-saving
mode. The power control register of 8051 contains two power-saving mode bits and one serial
baud rate control bit.
36 | P a g e
Bit 7 – SMOD
1 = Baud rate is doubled in UART mode 1, 2 and 3.
0 = No effect on Baud rate.
Bit 3:2 – GF1 & GF0:
These are general purpose bit for user.
Bit 1 – PD: Power Down
1 = Enable Power-Down mode. In this mode, the Oscillator clock turned OFF and both CPU
and peripherals clock stopped. Hardware reset can cancel this mode.
0 = Disable Power-down mode.
Bit 0 – IDL: Idle
1 = Enable Idle mode. CPU clock turned off whereas internal peripheral module such as a
timer, serial port, interrupts works normally. Interrupt and H/W reset can cancel this mode.
0 = Disable Idle mode.
37 | P a g e

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CS3691-Embedded Systems and IOT Prepared by: Mr E U Iniyan,AP/ECE

1. What is mean by microcontroller?

2. Explain DJNZ instructions of intel 8051 microcontroller?

a) DJNZ Rn, rel

Decrement the content of the register Rn and jump if not zero.

b) DJNZ direct, rel

the remaining bits is CLR B.7.

4.Explain the function of the pins PSEN and EA of 8051.

5. Explain the 16-bit registers DPTR and SP of 8051.

6. What is stack pointer (sp)?

The five addressing modes are,

Register indirect addressing

9. Mention the number of register banks and their addresses in 8051?

RAM locations from 00 to 07H for bank 0

RAM locations from 08 to 0FH for bank 1

RAM locations from 10 to 17H for bank 2

RAM locations from 18 to 1FH for bank 3

10.Compare Microprocessor and Microcontroller.

11. List the features of 8051 microcontroller?

The features are

Single supply +5 volt operation using HMOS technology.

4096 bytes program memory on chip(not on 8031)

128 data memory on chip.

Four register banks.

Two multiple mode, 16-bit timer/counter.

Extensive Boolean processing capabilities.

64 KB external RAM size

12. List various instructions available in 8051 microcontroller

 Data Transfer Instructions

MOV C, P1.2 ; save status of P1.2 on CY

MOV O6, C ; save carry in RAM bit location 06

MOV C, p1.3 ; save status of p1.3 on CY

MOV 07, C ; save carry in RAM bit location 07.

14. What is SFR?

15. Name the special functions registers available in 8051.

 Program Status Word.

16. What are the Two Main Features of SFR Addresses?

The following two points should be noted SFR addresses.

reserved and must not used by the 8051 programmer.

17. Difference between a Timer and a Counter

The points that differentiate a timer from a counter are as follows −

18. What is Program Status Word?

19. What is a serial data buffer?

20. What are timer registers?

21. What is the use of timing and control unit?

22. When are timer overflow bits set and reset?

23. Explain the mode (0 and1) operation of the timer.

The operations are as follows:

• The modes 0 and 1 can be used to time external events.

24. What is the different modes in which timer 2 can operate?

The two different modes in which Timer 2 operates are.

25. What is Polling ? What are the different types of Polling?

1) With neat block diagram, explain the architecture of 8051 Microcontroller.

Fig: Block Diagram of 8051 Micro Controller

8051 microcontroller is designed by Intel in 1981. It is an 8-bit microcontroller. It is

Basic components present internally inside 8051 Microcontroller architecture are:

Types of buses in 8051 Microcontroller:

Let's see the two types of bus used in 8051 microcontroller:

d) Timers of 8051 and their Associated Registers