PROCEDURE FOR DESIGN PROJECT IN XILINX SOFTWARE

1.Open Xilinx 14.2.

2. Create a New Project

File New Project Type the Name of the project and select the location
Next

Check the simulator and preferred language.

If simulator is ISim and preferred language is Verilog, then click Next Finish

3. Click on Project New Source

Select Verilog module and type the file name Next Finish .

4. Type the program and Save .

5. Click on the module and double click on synthesize.

6. Click on Simulation Enlarge ISim simulator Double click on Simulate Behavioral

Model .

7. Right click on the inputs appeared on the output window and click on Force constant .

Apply the values ( Test Vectors ) and Run for the specified time interval.

8. Verify the output waveform .

Exp No: 1(a) Date:

DESIGN OF LOGIC GATES

Aim:

To design basic Logic gates (AND Gate, OR Gate, NOT Gate, XOR Gate, XNOR Gate)
using Dataflow modeling.

Tools Required:

Xilinx Software V14.2.

Program:

AND Gate:

module AndGate (A,B,Y);

input A,B;
output Y;
assign Y = A & B;
endmodule

OR Gate:

module ORGate (A, B, Y);

input A, B;
output Y;
assign Y = A | B;
endmodule

NOT Gate:

module NOTGate (A, Y);

input A;
output Y;
assign Y = ~A;
endmodule

XOR Gate:

module xor1(Y,A,B);
output Y;
input A,B;
assign Y= A^ B;
endmodule
XNOR Gate:

module xnor1(Y,A,B);
output Y;
input A,B;
assign Y= ~(A^ B);
endmodule

Logic Diagram and Truth Table

AND Gate

Logic Diagram

Truth Table

A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1

OR Gate

Logic Diagram

Truth Table

A B Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1
NOT Gate

Logic Diagram

Truth Table

A Y=A

0 1

1 0

XOR Gate

Logic Diagram

Truth Table

A B Y=AB
0 0 0
0 1 1
1 0 1
1 1 0

XNOR Gate

Logic Diagram
Truth Table

A B Y=(AB)
0 0 1
0 1 0
1 0 0
1 1 1

Result

The design of basic logic gates are done by Data flow modeling and verified the
functionality by simulation.
Exp No: 1(b) Date:

DESIGN OF UNIVERSAL GATES

Aim:

To design of Universal Logic Gates (NAND Gate, NOR Gate) using Gate level
modeling.

Tools Required:

Xilinx Software V14.2

Program:

NAND Gate:

module NAND(Y,A,B);
output Y;
input A,B;
nand u1(Y,A,B);
endmodule

NOR Gate:

module NOR(Y,A,B);
output Y;
input A,B;
nor u1(Y,A,B);
endmodule

Logic Diagram and Truth Table

NAND Gate

Logic Diagram
Truth Table

A B Y=(A.B)
0 0 1
0 1 1
1 0 1
1 1 0

NOR Gate

Logic Diagram

Truth Table

A B Y=(A+B)
0 0 1
0 1 0
1 0 0
1 1 0

Result

The design of universal gates are done by Gate level modeling and verified the
functionality by simulation.
Exp No: 2 Date:

DESIGN OF ADDERS

Aim:

To design the following Adders using basic logic gates

Half Adder(HA)

Full Adder(FA)

Tools Required:

Xilinx Software V14.2

Program:

Half Adder

module HA (S, C, A,B);

output S, C;
input A,B;
xor XOR(S, A,B);
and AND(C, A,B);
endmodule

Full Adder

module FA(Sum, Cout, a, b, Cin);

output Sum, Cout;
input a, b, Cin ;
wire s1, c1, c2,c3;
xor XOR1(s1, a, b);
xor XOR2(sum, s1, Cin);
and AND1(c1, a, b);
and AND2(c2, b, Cin);
and AND3(c3,a,Cin);
or OR(Cout, c2, c1,c3);
endmodule
Logic Diagram and Truth Table

Half Adder

Logic Diagram

Truth Table

INPUTS OUTPUTS

A B S= A B C= A.B

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1
Full Adder

Logic Diagram

Truth Table

INPUTS OUTPUTS

a b Cin Sum=abCin Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Result

The design of adders (Half and Full Adder) are done by Gate level modeling and verified
the functionality by simulation..
Exp No: 3 Date:

DESIGN OF RIPPLE CARRY ADDER

Aim:

To design the Ripple Carry Adder using Full Adders.

Tools Required:

Xilinx Software V14.2

Program:

Ripple Carry Adder

module RCA( output [3:0] Sum,

output Cout,

input [3:0] A,B,

input Cin

);

wire C1,C2,C3;

FA FA1(Sum[0],C1,A[0],B[0],Cin);

FA FA2(Sum[1],C2,A[1],B[1],C1);

FA FA3(Sum[2],C3,A[2],B[2],C2);

FA FA4(Sum[3],Cout,A[3],B[3],C3);

endmodule

/* Full Adder */

module FA(Sum, Cout, a, b, Cin);

output Sum, Cout;
input a, b, Cin ;
wire s1, c1, c2,c3;
xor XOR1(s1, a, b);
xor XOR2(sum, s1, Cin);
and AND1(c1, a, b);
and AND2(c2, b, Cin);
 and AND3(c3,a,Cin);
or OR(Cout, c2, c1,c3);
endmodule

Circuit Diagram

Ripple Carry Adder

Result

The design of ripple carry adder is done by full adders and verified the functionality by
simulation..
Exp No: 4 Date:

DESIGN OF SUBTRACTOR

Aim:

To design the following Subtractor using basic logic gates

Half Subtractor (HS)

Full Subtractor (FS)

Tools Required:

Xilinx Software 14.2

Program:

Half Subtractor

module HS(Diff, Bor, A, B);

output Diff, Bor;

input A,B;

wire W;

xor XOR(Diff,A,B);

and AND(Bor,W,B);

not NOT1(W,A);

endmodule

Full Subtractor

module FS( Diff, Bor, A, B, C);

output Diff, Bor;

input A, B, C;

wire W0,W1,W2,W3,W4;

xor XOR1( W0,A,B);

xor XOR2( Diff, C,W0);

 not NOT( W1,A);

and AND1( w2, B, w1);

and AND2( W3, B,C);

and AND3( W4,C,W1);

or OR1( Bor, W2,W3,W4);

endmodule

Logic Diagram and Truth Table

Half Subtractor

Logic Diagram

Truth Table

INPUTS OUTPUTS

A B Diff= A B Bor= A.B

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0
Full Subtractor

Logic Diagram

Truth Table

INPUTS OUTPUTS

A B C Diff Bor

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

Result

The design of subtractor (Half and Full Subtractor) are done by Gate level modeling and
verified the functionality by simulation..
Exp No : 5 Date:

DESIGN OF LATCHS

Aim:

To design following Latchs using Gate level modeling

SR Latch ( using NAND and NOR gates)

D Latch ( using NAND and NOR gates)

Tools Required:

Xilinx Software 14.2

Programs

(a). SR Latch using NOR Gate

module SRNor(Q , Qbar , S,R);
input S,R;
output Q, Qbar ;
nor N1(Q, R, Qbar);
nor N2(Qbar , S, Q);
endmodule
(b). SR Latch using NAND Gate
module SRNand(Q , Qbar , S,R);
input S,R;
output Q, Qbar ;
nand N1(Q, S, Qbar);
nand N2(Qbar ,R, Q);
endmodule

(c). D Latch using NAND Gate

module DNand(Q , Qbar , D,E);
input D,E;
output Q, Qbar ;
wire S, R,W;
not N1 (W,D);
nand N2(S,E,D);
nand N3(R,W,E);
nand N4(Q, S, Qbar);
nand N5(Qbar ,R, Q);
endmodule
 (d). D Latch using NOR Gate
module DNor(Q , Qbar , D,E);
input D,E;
output Q, Qbar ;
wire S, R,W;
not N1 (W,D);
and N2(S,E,D);
and N3(R,W,E);
nor N4(Q, R, Qbar);
nor N5(Qbar ,S, Q);
endmodule

Logic Diagram

SR latch using NOR Gate

Truthtable

Inputs Outputs

S R Q Q

0 0 Previous State Output

0 1 0 1

1 0 1 0

1 1 Forbidden / Indeterminate State

SR latch using NAND Gate

Truthtable

Inputs Outputs

S R Q Q

0 0 Forbidden / Indeterminate State

0 1 1 0

1 0 0 1

1 1 Previous State Output

D Latch

Using NAND gate

Truthtable

Inputs Outputs

E D Q Q

0 X Previous State Output

1 0 0 1

1 1 1 0

Using NOR Gate

Truthtable

Inputs Outputs

E D Q Q

0 X Previous State Output

1 0 0 1

1 1 1 0

Result

The design of Latchs (SR and D) using universal gates are done by Gate level
modeling and verified the functionality by simulation.
Exp No: 6 Date:

DESIGN OF FLIPFLOPS

Aim:

To design and simulate following Flipflops using Universal Gates

D Flipflop

Tools Required:

Xilinx Software 14.2

Programs

(a). D Flipflop using Nand gate

module DNand(Q , Qbar , D,Clk);
input D,Clk;
output Q, Qbar ;
wire S, R,W;
not N1 (W,D);
nand N2(S,Clk,D);
nand N3(R,W,Clk);
nand N4(Q, S, Qbar);
nand N5(Qbar ,R, Q);
endmodule

(b). D Flipflop using Nor gate

module DNor(Q , Qbar , D,Clk);
input D,Clk;
output Q, Qbar ;
wire S, R,W;
not N1 (W,D);
and N2(S,Clk,D);
and N3(R,W,Clk);
nor N4(Q, R, Qbar);
nor N5(Qbar ,S, Q);
endmodule
Logic Digram

D Flipflop

Using NAND gate

Using NOR Gate

Truthtable for D-Flipflop

Inputs Outputs

Clock Pulse D Q Q

No Clock Pulse X No Change

Clock Pulse 0 0 1

Clock Pulse 1 1 0
Result

Thus the design of D flip flop using universal gates was done and output was verified by
the functionality.
Exp.No:7 Date:

TESTING OF LOGIC GATES

Aim

To test and verify the truth table of following logic gates using ICs.

NAND (IC7400) Gate, NOR (IC7402) Gate, NOT (IC7404) Gate, AND (IC7408) Gate, OR
(IC7432), XOR(IC7486) Gate and XNOR (IC747266) Gate.

Apparatus Required

o IC 7400 ,IC 7402 , IC 7404 , IC 7408 1 no (each IC )

IC 7432 , IC 7486 , IC 74266

o Patch Cord / Connecting Wires

Theory

OR (IC7432)Gate:

The OR Gate performs logical addition, commonly known as OR Function. IC7432 is a

quad 2-input OR function. It has two or more inputs and only one output. The operation of OR
gate is such that a HIGH (1) on the output is produced when any one of the inputs is HIGH (1).
The output is LOW (0) only when all the inputs are LOW (0).

AND (IC7408)Gate:

The AND Gate performs logical multiplication, commonly known as AND function.
IC7408 is a quad 2-input AND function. It has two inputs and only one output. The output of an
AND gate is HIGH only when all the inputs are HIGH. Even if any one of the inputs is LOW,
the output will be LOW.

NOT (IC7404)Gate:

The NOT performs the basic logical function called inversion or complementation.
IC7404 is a hex 1-input NOT function. It has one input and one output. The purpose of this logic
gate is to convert one logic to the opposite logic level. When HIGH input is applied to an
inverter, a LOW output appears at its output and vice versa.

NAND (IC7400)Gate:

NAND gate is a contraction of the NOT-AND gates. IC7400 is a quad 2-input NAND
function. It has two inputs and only one output. When all the inputs are HIGH, the output is
LOW. If any one or both the inputs are LOW, then the output is HIGH. The NAND called as
Universal Gate.

NOR(IC7402) Gate:

NOR gate is a contraction of the NOT-OR gates. IC7402 is a quad 2-input NOR
function. It has is a gate with two and one output. When all the inputs are LOW, the output is
HIGH. If any one or both the inputs are HIGH, then the output is LOW. The NOR gate called as
Universal Gate.

EX-OR (IC7486) Gate:

IC7486 is a quad 2-input EX-OR function. The output of a gate is HIGH when odd
numbers of HIGH inputs are applied. If Even number of HIGH inputs or all the inputs are LOW
the output will be LOW.

EX-NOR (IC74266) Gate:

IC74266 is a quad 2-input Ex-NOR function. It is a gate with two and one output. When
all the inputs are LOW or HIGH the output will be HIGH. The output of a gate is LOW when
odd numbers of HIGH inputs are applied.

Procedure

Note: Student should write it on your own with proper meaning and sentence formation

Circuit Diagram

NAND Gate (IC7400)

IC Diagram
Logic Diagram

Truth Table

A B Y=(A.B)
0 0
0 1
1 0
1 1

NOR Gate (IC7402)

IC Diagram

Logic Diagram

Truthtable

A B Y=(A+B)
0 0
0 1
1 0
1 1
NOT Gate (IC7404)

IC Diagram

Logic Diagram

Truth Table

A Y=A

AND Gate (IC7408)

IC Diagram
Logic Diagram

Truth Table

A B Y=A.B
0 0
0 1
1 0
1 1
OR Gate (IC 7432)

IC Diagram

Logic Diagram
Truth Table

A B Y=A+B
0 0
0 1
1 0
1 1

EX-OR Gate (IC7486)

IC Diagram

Logic Diagram

Truth Table

A B Y=AB
0 0
0 1
1 0
1 1
EX-NOR Gate (IC74266)

IC Diagram

Logic Diagram

Truth Table

A B Y=(AB)
0 0
0 1
1 0
1 1

Result

The testing of logic gates using ICs was done and output was verified by the
functionality.
Exp.No: 8 Date:

TESTING OF ADDERS

Aim

To test and verify the following adders using IC 7486, 7408 & 7432.

Half Adder
Full Adder

Apparatus Required

o ICs: 7486, 7408, 7432

o Patch Cord

Theory

Half Adder:

The half adder is an example of a simple, functional digital circuit built from two logic
gates. The half adder adds to one-bit binary numbers (AB). The output is the sum of the two
bits (S) and the carry (C). Note how the same two inputs are directed to two different gates. The
inputs to the XOR gate are also the inputs to the AND gate. The input "wires" to the XOR gate
are tied to the input wires of the AND gate; thus, when voltage is applied to the A input of the
XOR gate, the A input to the AND gate receives the same voltage.

Sum = AB + AB = AB

Carry = AB

Full Adder:

The full-adder circuit adds three one-bit binary numbers (C A B) and outputs two one-bit
binary numbers, a sum (S) and a carry (C1). The full-adder is usually a component in a cascade
of adders, which add 8, 16, 32, etc. binary numbers. The carry input for the full-adder circuit is
from the carry output from the circuit "above" itself in the cascade. The carry output from the
full adder is fed to another full adder "below" itself in the cascade. If you look closely, you'll see
the full adder is simply two half adders joined by an OR.

Sum = ABC

Carry = AB + BC + AC
Procedure

Note: Student should write it on your own with proper meaning and sentence formation

Half Adder

Truthtable

INPUTS OUTPUTS

A B S= A B C= A.B

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

K-Map

Note: Student should have to find out the expression of Sum and Carry using Half Adder
truthtable

Logic Diagram

Circuit Diagram
Full Adder

Truthtable

INPUTS OUTPUTS

a b Cin Sum=abCin Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

K-map:

Note: Student should have to find out the expression of Sum and Carry using Full Adder
truthtable
Logic Diagram

Circuit Diagram
Result

Thus the testing of half adder and full adder using ICs was done and output is verified by
the functionality.
Exp.No: 9 Date:

TESTING OF SUBTRACTORS

Aim

To test and verify the following Subtractors using ICs 7486, 7408, 7404, 7432.

Half Subtractor
Full Subtractor

Apparatus Required

o ICs: 7486, 7408, 7432,7404

o Patch Cord

Theory

Half Subtractor:

The half-subtractor is a combinational circuit which is used to perform subtraction of two

bits. It has two inputs, A(minuend) and B (subtrahend) and two outputs D (difference) and B
(borrow).

Difference = AB + AB = AB

Borrow = AB

Full Subtractor:

As in the case of the addition using logic gates, a full subtractor is made by combining two half-
subtractors and an additional OR-gate. A full subtractor has the borrow in capability and so allows
cascading which results in the possibility of multi-bit subtraction. The circuit diagram for a full
subtractor is given below.

Difference = ABC

Borrow = AB + BC + AC

Procedure

Note: Student should write it on your own with proper meaning and sentence formation
Half Subtractor

Truthtable

INPUTS OUTPUTS

A B Diff= A B Bor= A.B

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

K-Map

Note: Student should have to find out the expression of Difference and Borrow using
Half Subtractor truthtable

Logic Diagram

Circuit Diagram
Full Subtractor

Truthtable

INPUTS OUTPUTS

A B C Diff Bor

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

K-Map

Note: Student should have to find out the expression of Difference and Borrow using Full
Subtractor truthtable
Logic Diagram
Circuit Diagram

Result

Thus the testing of half subtractor and full subtractor using ICs was done and output was
verified by the functionality.
Exp.No: 10 Date:

TESTING OF 4 BIT MAGNITUDE COMPARATOR

Aim

To test and verify the truth table of four bit binary comparator circuit using IC 74LS85.

Apparatus Required

o IC 74LS85

o Connecting Wires

Theory

Comparator

The 74LS85 is a 4-bit magnitude comparator that can be expanded to almost any length.
It compares two 4-bit binary, BCD, or other monotonic codes and presents the three possible
magnitude results at the outputs. The 4-bit inputs are weighted (A0A3) and (B0B3) where A3
and B3 are the most significant bits. The operation of the 74LS85 is described in the Function
Table, showing all possible logic conditions. The upper part of the table describes the normal
operation under all conditions that will occur in a single device or in a series expansion scheme.
In the upper part of the table the three outputs are mutually exclusive. In the lower part of the
table, the outputs reflect the feed-forward conditions that exist in the parallel expansion scheme.
The expansion inputs IA>B, and IA=B and IA<B are the least significant bit positions. When used for
series expansion, the A>B, A=B and A<B outputs of the lease significant word are connected to
the corresponding IA>B, IA=B and IA<B inputs of the next higher stage. For proper operation, the
expansion inputs of the least significant word should be tied as follows: IA>B= 0 , IA=B= 1, and
IA<B= 0.

Procedure

Note: Student should write it on your own with proper meaning and sentence formation.

Circuit Diagram

IC Diagram
Logic Symbol

Truth Table

Comparing Inputs Cascading Inputs Outputs

A3,B3 A2,B2 A1,B1 A0,B0 IA>B IA<B IA=B OA>B OA<B OA=B
A3>B3 X X X X X X 1 0 0
A3<B3 X X X X X X 0 1 0
A3=B3 A2>B2 X X X X X 1 0 0
A3=B3 A2<B2 X X X X X 0 1 0
A3=B3 A2=B2 A1>B1 X X X X 1 0 0
A3=B3 A2=B2 A1<B1 X X X X 0 1 0
A3=B3 A2=B2 A1=B1 A0>B0 X X X 1 0 0
A3=B3 A2=B2 A1=B1 A0<B0 X X X 0 1 0
A3=B3 A2=B2 A1=B1 A0=B0 1 0 0 1 0 0
A3=B3 A2=B2 A1=B1 A0=B0 0 1 0 0 1 0
A3=B3 A2=B2 A1=B1 A0=B0 X X 1 0 0 1
A3=B3 A2=B2 A1=B1 A0=B0 1 1 0 0 0 0
A3=B3 A2=B2 A1=B1 A0=B0 0 0 0 1 1 0

Result

The testing of 4 bit binary comparator using IC 74LS85 was done and output was
verified by functionality.
Exp.No: 11 Date:

TESTING OF MULTIPLEXER AND DEMULTIPLEXER

Aim

To test and verify the truth table of following combinational circuits using ICs 74LS151
& 74LS155.

Multiplexer
Demultiplexer

Apparatus Required

o ICs 74LS151 & 74LS155

o Connecting Wires

Theory

Multiplexer

Multiplexer is a combinational circuit that is one of the most widely used in digital
design. The LS151 is a logical implementation of a single pole, 8-position switch with the switch
position controlled by the state of three Select inputs, S0, S1, S2. Both assertion and negation
outputs are provided. The Enable input (E) is active 0. When it is not activated, the negation
output is 1 and the assertion output is 0 regardless of all other inputs. The LS151 provides the
ability, in one package, to select from eight sources of data or control information. By proper
manipulation of the inputs, the LS151 can provide any logic function of four variables and its
negation.

Demultiplexer

The data distributor, known more commonly as a Demultiplexer or Demux for short, is
the exact opposite of the Multiplexer we saw in the previous tutorial. The demultiplexer takes
one single input data line and then switches it to any one of a number of individual output lines
one at a time. The demultiplexer converts a serial data signal at the input to a parallel data at its
output lines. These monolithic transistor-transistor logic (TTL) circuit feature dual 1 to 4 line
demultiplexer with individual strobes end common binary address inputs in a single 16 pin
package. When both sections are enabled by the strobes, the common binary address inputs
sequentially select and route associated inputs data to the appropriate output of each section. The
individual strobes permit activating or inhibiting each of the 4- bit sections as desired. Data
applied to inputs 1C is inverted at its outputs and data applied at 2C' is not inverted through its
outputs. The inverter following the 1C data input permits use as a 3 to 8 line decoder or 1 to 8
line demultiplexer without external gating. Input clamping diodes are provided on all of these
circuits to minimize transmission line effects and simplify system design.
Procedure

Note: Student should write it on your own with proper meaning and sentence formation

Multiplexer

Pin Diagram

Logic Diagram
Truthtable

Select Input Output

Lines
E S2 S1 S0 I0 I1 I2 I3 I4 I4 I6 I7 Z Z
1 X X X X X X X X X X X 1 0
0 0 0 0 0 X X X X X X X 1 0
0 0 0 0 1 X X X X X X X 0 1
0 0 0 1 X 0 X X X X X X 1 0
0 0 0 1 X 1 X X X X X X 0 1
0 0 1 0 X X 0 X X X X X 1 0
0 0 1 0 X X 1 X X X X X 0 1
0 0 1 1 X X X 0 X X X X 1 0
0 0 1 1 X X X 1 X X X X 0 1
0 1 0 0 X X X X 0 X X X 1 0
0 1 0 0 X X X X 1 X X X 0 1
0 1 0 1 X X X X X 0 X X 1 0
0 1 0 1 X X X X X 1 X X 0 1
0 1 1 0 X X X X X X 0 X 1 0
0 1 1 0 X X X X X X 1 X 0 1
0 1 1 1 X X X X X X X 0 1 0
0 1 1 1 X X X X X X X 1 0 1

Demultiplexer

Pin Diagram
Logic Symbol

Truthtable

Address Demultiplexer A Demultiplexer B

Line Enable Ea Output Enable Eb Output
A1 A0 E1/C1 E2/G0 1Y0 1Y1 1Y2 1Y3 E14/C2 E15/G1 2Y0 2Y1 2Y2 2Y3
X X 0 X 1 1 1 1 1 X 1 1 1 1
X X X 1 1 1 1 1 X 1 1 1 1 1
0 0 1 0 0 1 1 1 0 0 0 1 1 1
0 1 1 0 1 0 1 1 0 0 1 0 1 1
1 0 1 0 1 1 0 1 0 0 1 1 0 1
1 1 1 0 1 1 1 0 0 0 1 1 1 0

Result

The testing of Multiplexer (MUX) and Demultiplexer (DEMUX) using ICs was done
and output was verified by functionality.
Exp.No: 12 Date:

TESTING OF DECODER AND ENCODER

Aim

To test and verify the truth table of following combinational circuits using ICs.

Decoder
Encoder

Apparatus Required

o IC 74HC138N - 1 no

o IC 74HC148N - 1 no

o Connecting Wires

Theory

Decoder

The combinational logic of a typical 3-to-8-line decoder based on the 74HC138, an IC

that has many uses apart from address decoding, it is often used with a binary counter driving its
inputs, when its eight outputs constantly step through a 0 to 7 sequence. Typical applications
include sequence generating for lamp control, row scanning for dot matrix displays, digital
operation of analogue controls and anywhere that a sequence of unique outputs is required.Data
sheets for the 74HC138 point out the advantages of the three Enable pins, which can be used for
simply connecting the decoders together to make larger decoders. Where two 74HC138 ICs are
connected together using only one additional NOT gate. Note that the pin connections on the ICs
are not in the consecutive 1 to 16 order of the real 74HC138 pinout, but can be identified in the
IC Pin diagram.

Encoder

The 74HC148 also uses priority encoding and features eight active low inputs and a
three-bit active low binary (Octal) output. The internal logic of the 74HC148 is shown in logic
symbol. The IC is enabled by an active low Enable Input (EI), and an active low Enable output
(EO) is provided so that several ICs can be connected in cascade, allowing the encoding of more
inputs, for example a 16-to-6-line encoder using two 8-to-3 encoders.

The CMOS 74HC148 also uses active low inputs and outputs. The operation of the
74HC148 can be seen from its truth table. Notice from truthtable that the IC is only active when
EI is low, and also that for each input selected by a low logic level (L), all lower value inputs
indicate Dont Care, typical of priority encoding. Two further outputs (GS and EO) are used for
connecting additional 74HC148 ICs in cascade.
 The EI input is normally used on the most significant IC and whenever an input on this
IC is selected, the EO output goes high (disabling any less significant ICs), and the Group Select
(GS) output goes low indicating that the group of outputs of this IC are active.

Procedure

Note: Student should write on your own with proper meaning and sentence formation.

Decoder

Pin Diagram

Logic Symbol

Truthtable

Inputs Outputs

E1 E2 E3 A2 A1 A0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

1 X X X X X 1 1 1 1 1 1 1 1

X 1 X X X X 1 1 1 1 1 1 1 1

X X 0 X X X 1 1 1 1 1 1 1 1
 0 0 1 0 0 0 1 1 1 1 1 1 1 0

0 0 1 0 0 1 1 1 1 1 1 1 0 1

0 0 1 0 1 0 1 1 1 1 1 0 1 1

0 0 1 0 1 1 1 1 1 1 0 1 1 1

0 0 1 1 0 0 1 1 1 0 1 1 1 1

0 0 1 1 0 1 1 1 0 1 1 1 1 1

0 0 1 1 1 0 1 0 1 1 1 1 1 1

0 0 1 1 1 1 0 1 1 1 1 1 1 1

Encoder

Pin Diagram
Logic Symbol

Truthtable

Inputs Outputs

EI I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0 GS EO

1 X X X X X X X X 1 1 1 1 1

0 1 1 1 1 1 1 1 1 1 1 1 1 0

0 X X X X X X X 0 0 0 0 0 1

0 X X X X X X 0 1 0 0 1 0 1

0 X X X X X 0 1 1 0 1 0 0 1

0 X X X X 0 1 1 1 0 1 1 0 1

0 X X X 0 1 1 1 1 1 0 0 0 1

0 X X 0 1 1 1 1 1 1 0 1 0 1

0 X 0 1 1 1 1 1 1 1 1 0 0 1

0 0 1 1 1 1 1 1 1 1 1 1 0 1

Result

The testing of Decoder and Encoder using ICs was done and output was verified by
functionality.
Exp.No: 12 Date:

TESTING OF FLIPFLOP AND LATCH

Aim

To study and verify the truth table of following sequential circuits using IC CD4027BE.

JK Flipflop
SR Latch

Apparatus Required

o IC CD4027BE 1 No

o Connecting Wires

Theory

CD4027BE is a single monolithic chip integrated circuit containing two identical

complementary symmetry J-K master slave flipflop. Each flipflop has provisions for individual J,
k , Ser(S) ,Reset (R) and clock input signals. Buffered Q and Q' signals are provided as outputs.
this output arrangement provides for compactable operation with the RCA-CD4013B dual D
type of flipflop. The CD4027BE is useful in performing in control , register , toggle functions.

Logic levels present at the j and K inputs along with internal self-steering control the
state of each flipflop; changes in the flipflop state are synchronous with the positive going
transition of the clock pulse. Set and Reset functions are independent clock and are initiated
when a high level signal is present at either the Set or Reset input.

Procedure

Note: Student should write it on your own with proper meaning and sentence formation

Pin Diagram
Logic Symbol

Truthtable

JK Flipflop

INPUTS OUTPUTS

S R J K Clock Q Q

1 0 x x x 1 0

0 1 x x x 0 1

1 1 x x x Forbidden State

0 0 0 0 Previous State Output

0 0 0 1 0 1

0 0 1 0 1 0

0 0 1 1 Toggle State
SR Latch

INPUTS OUTPUTS

S R Q Q

0 0 Previous State Output

0 1 0 1

1 0 1 0

1 1 Forbidden / Undefined State

Result

The testing of JK Flipflop and SR Latch using IC CD4027BE was done and output was
verified by functionality.
Exp.No: 14 Date:

TESTING OF BCD DECADE COUTER

Aim

To test and verify the truth table of BCD Decade counter circuit using IC 74LS90 .

Apparatus Required

o IC 74LS90

o Connecting Wires

Theory

Decade Counter

The counters four outputs are designated by the letter symbol Q with a numeric subscript equal
to the binary weight of the corresponding bit in the BCD counter circuits code. So for example
Q0, Q1, Q2 and Q3. The 74LS90 counting sequence is triggered on the negative going edge of the
clock signal, that is when the clock signal CP0 goes from logic 1 (HIGH) to logic 0 (LOW).The
additional input pins MR1 and MR2 are counter reset pins while inputs MS1 and MS2 are set
pins. When connected to logic 1, the Reset inputs MR1 and MR2 reset the counter back to zero, 0
(0000), and when the Set inputs MS1 and MS2 are connected to logic 1, they Set the counter to
maximum, or 9 (1001) regardless of the actual count number or position.

As we said before, the 74LS90 counter consists of a divide-by-2 counter and a divide-by-
5 counter within the same package. Then we can use either counter to produce a divide-by-2
frequency counter only, a divide-by-5 frequency counter only or the two together to produce our
desired divide-by-10 BCD counter.With the four flip-flops making up the divide-by-5 counter
section disabled, if a clock signal is applied to input pin 14 (CP0) and the output taken from pin
12 (Q0), we can produce a standard divide-by-2 binary counter for use in frequency dividing
circuits as shown.

Procedure

Note: Student should write it on your own with proper meaning and sentence formation.
Decade Counter

IC Diagram

Circuit Diagram
Truthtable

Count Sequence

Count Output
Q0 Q1 Q2 Q3
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

Result

The testing of decade counter using IC 74LS90 was done and output was verified by
functionality.
Exp.No: 15 Date:

TESTING OF UNIVERSAL SHIFT REGISTER

Aim

To test and verify the truth table of Universal Shift Register (sequential circuit) using IC
74LS194N.

Apparatus Required

o IC SN74LS194N

o Connecting Wires

Theory

Universal Shift Register (SN74LS194N)

These universal shift registers are designed to incorporate virtually all of the features a
system designer may want in a shift register. The circuit contains 46 equivalent gates and
features parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode
control inputs and a direct overriding clear line. The register has four distinct modes of
operation, namely:

Inhibit clock (do nothing)

Shift right (in the direction Q0 towards Q3)
Shift left (in the direction Q3 towards Q0)
Parallel (broadside) load

Synchronous parallel loading is accomplished by applying the four bits of data and taking
both mode control inputs S0 and S1 high. The data are loaded into the associated flip-flops and
appear at the outputs after the positive transition of the clock input. During loading serial data
flow in inhibited. Shift right is accomplished synchronously with the rising edge of the clock
pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data
input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the
shift-left serial input.

Clocking of the shift register is inhibited when both mode control inputs are low. The mode
controls of the SN54194/SN74194 should be changed only while the clock input is high.

Procedure

Note: Student should write it on your own with proper meaning and sentence formation.
IC Diagram

Logic Symbol

Truthtable

Inputs Outputs
MR S1 S0 DSR DSL Q0 Q1 Q2 Q3
0 X X X X 0 0 0 0
1 0 0 X X q0 q1 q2 q3
1 0 1 0 X 0 q0 q1 q2
1 0 1 1 X 1 q0 q1 q2
1 1 0 X 0 q1 q2 q3 0
1 1 0 X 1 q1 q2 q3 1
1 1 1 X X P0 P1 P2 P3
Result

The testing of universal shift register using IC SN74LS194N was done and output was
verified by functionality.