Static Logigates 12
Static Logigates 12
CH 12 PR 1:
Design, layout, and simulate the operation of a CMOS AND gate with a Vsp of approximately 500mV. Use the standard-cell frame
discussed in CH. 4 for the layout.
Design:
Use the CMOS NAND gate with inverter at output, treating the mosfet’s as resistors.
Rn + Rn
V sp = VDD *
Rn + Rn + Rp || Rp
For Vsp=.5VDD and Rn=Rn’/Wn=3.4k/Wn and Rp=Rp’/Wp=6.8k/Wp
2 * 3.4k / Wn
.5VDD = VDD *
2 * 3.4k / Wn + 1 / 2 * 6.8k / Wp
Wn = 2 * Wp
Let Wp=10 => Wn=20
.control
destroy all
run
plot vin out
.endc
.option scale=.050u
.dc vin 0 1 100u
vdd vdd 0 DC 1
Vin vin 0 DC 0
*INV
M11 out out1 0 0 NMOS L=1 W=10
M12 out out1 VDD VDD PMOS L=1 W=20
.ends
John Spratt EE 510 Physical IC Design 4/17/2004
Layout:
Problem 12.2 Steve Bard
Design and simulate the operation of a CMOS AOI half adder circuit using static logic gates.
Solution: A half adder circuit calculates a half sum (HS) and a carry out (CO). It takes two input
bits, A and B. The logic equations for HS and CO are
HS = A ⊕ B
CO = A ⋅ B = ( A + B )
Figure 1 shows a circuit schematic of a half adder’s components. For clarity, the components are
not wired together in the figure. The SPICE simulation and code appear on the next page.
VDD VDD
B
B
.control
destroy all
run
plot VA VB CO HS
.endc
.option scale=50n
.tran 10p 2.2n
Vdd Vdd 0 DC 1
VA VA 0 DC 0 pulse 0 1 250p 50p 50p 0.5n 1n
VB VB 0 DC 0 pulse 0 1 1.5n 50p 50p 0.5n 1n
*A inverter
M2 A_ VA Vdd Vdd PMOS L=1 W=20
M1 A_ VA 0 0 NMOS L=1 W=10
*B inverter
M4 B_ VB Vdd Vdd PMOS L=1 W=20
M3 B_ VB 0 0 NMOS L=1 W=10
.end
12.3 Shambhu Roy
Repeat Ex 12.3 for a three-input NOR gate (Use the effective resistances to estimate Vsp)
Ex 12.3 Estimate the intrinsic propagation delays t PHL + t PLH , of a three input NAND gate
made using 10/1 NMOS and 20/1 PMOS in a short channel process. Estimate and
simulate the delay when the gate is driving a load capacitance of 50fF. Assume that
inputs are tied together.
Solution:
For a 3 input NOR when it goes from high to low the load is charged through 3 NMOS is
parallel and when output goes from low to high it has 3 PMOS resistances in series, So
Rn C outp
t PHL = 0.7 (3.C outn + + C load )
3 3
C outp
t PLH = 0.7.3.R p (3.C outn + + C load ) + 0.35 R p C oxp .3 2
3
Using the values of resistances and capacitances for a short channel process from table
10.2
3.4k 1.25 fF
t PHL = 0.7 (3.0.625 fF + + 50 fF ) = 41.4 ps
3 3
1.25 fF
t PLH = 0.7.3.3.4k (3.0.625 fF + + 50 fF ) + 0.35.3.4k .1.25 fF .3 2 = 386.7 ps
3
delay = 41.4+386.7=428.1ps
3.R p 3.R p
Vsp can vary from to ie 900mV to 750mV
R 3.R p + Rn
3.R p + n
3
*** Sol 12.3 ***
.control
destroy all
run
plot vin out ylimit 0 1
.endc
.option scale=50n
.tran 10p 2n 10p
vdd vdd 0 DC 1
Vin vin 0 DC 0 pulse 0 1 200p 0 0 0.5n 4n
Repeat Ex. 12.4 for a three-input NOR gate. (Use the effective resistances to
estimate the VSP)
Solution:
tPHL = 0.7 (Rn)(Cload)
tPHL = 0.7 (3.4K)(50fF)
tPHL = 119ps
Simulations Results
tPLH = 566ps ( Considerably longer Since single NMOS device is pulling the output high.
Rupa Balan
12.5 Sketch the schematic of an OR gate with 20 inputs. Comment on your design.
OR gate with 20 inputs can be drawn with a 20 input NOR gate and inverter as shown
In this case there are 20 PMOS in series in the NOR gate. Hence low to high propagation delay of the NOR gate
is high.
(In case of equal sized NMOS and PMOS devices, Rp>Rn and here the PMOS are in series. Hence here tpLH of
NOR gate is very high. Also here the delay tpLH of NOR gate increases as the square of N, where N is number of
inputs which are 20.)
Also 21 PMOS and 21 NMOS including the inverter for a total of 42 Mosfets are needed.
So the following schematic can be used which again uses a 20 input NOR gate and an inverter.
Here also the low to high propagation delay of the NOR gate would be considerably high due to the large
resistance of the long length pull up device and also due to the large output capacitance of the parallel NMOS.
But here only 23 Mosfets are needed.
In order to ensure that the output of the NOR gate gets pulled low enough (VOL=0), the resistance of the Long L
PMOS has to be atleast four times the resistance of the NMOS in the NOR gate.
For the simulation shown below, the size of all NMOS devices in the NOR gate has been taken as 10/1, the size
of long L PMOS in the NOR gate has been taken as 20/10, the size of NMOS in the inverter is 10/1 and size of
PMOS in the inverter is 20/1.
Thus by using a long value for L in the PMOS, the output vout1 of the NOR gate is pulled to zero as seen in the
simulation.
PROBLEM 12.6 Indira
Sketch the schematic of a static logic gate that implements . Estimate the worst
case delay delay through the gate when driving a 50fF load capacitance?
Solution:
PMOS=20/1 NMOS=10/1
COUT=2/3COXN + COXN + 3/5COXP + CLOAD
COUT=2/3(0.625Ff) + 0.625Ff + 3/5(1.25Ff) + 50Ff
COUT=51.78Ff
Worst-case delay is when all the , and (PMOS) are ON. We will have three resistors in
series. Therefore we get,
3Rp=3(68K/20)
=10.2K
tPLH =0.7*10.2K*51.78Ff
tPLH =369.7ps
HW#11 KRISHNAMRAJU KURRA DATE:04/19/04
PROBLEM 12.7
Design and simulate the operation of a CVSL OR gate made with minimum size devices.
By using minimum size devices the output was being pulled by the PMOS devices to high before
it reached zero. The out put can be pulled down to zero by increasing the strength of the
NMOS(increase width of NMOS)or by decreasing the strength of the PMOS(increase length of
PMOS).
Problem 12.8: Surendranath C Eruvuru
Design and simulate the operation of a tri-state buffer that has propagation delays
under 5ns when driving a 1 pF load. Assume that the maximum input capacitance of
the buffer is 100fF.
In tri – state buffer if enable is low, then the output will be high impedance
state. If enable is high, then the output will have the same logic value as A.
According to the question, input capacitance can’t exceed 100fF. So, the
total input capacitance can be written as follows:
Inverter NAND
After solving,
Wn Ln~178 & Wp Lp~ 356.
Approximating above values in the following net list, a Tri-state buffer that
has propagation delay under 5ns has been obtained.
Net list:
.CONTROL
DESTROY ALL
RUN
Plot V(A) V(out)
.ENDC
.option scale=50n
.tran .1n 50n UIC
*.IC V(BOUT)=1
VDD Vdd 0 DC 1
VA A 0 DC 0 PULSE 0 1 0 0.1n 0.1n 10n 20n
VEn En 0 DC 1
C1 out 0 1p
*****SUBCKT 1******
.SUBCKT INV in1 out1 Vdd
M1 out1 in1 Vdd Vdd PMOS L=1 W=20
M2 out1 in1 0 0 NMOS L=1 W=10
.ENDS
*****SUBCKT 2 ******
.SUBCKT Nand A B Vdd out
M1 1 B 0 0 NMOS L=5 W=40
M2 out A 1 0 NMOS L=5 W=40
M3 out A Vdd Vdd PMOS L=5 W=80
M4 out B Vdd Vdd PMOS L=5 W=80
.ENDS
*****SUBCKT 3 ******
.SUBCKT Nor A B Vdd out
M1 out B 0 0 NMOS L=5 W=40
M2 out A 0 0 NMOS L=5 W=40
M3 1 A Vdd Vdd PMOS L=5 W=80
M4 out B 1 Vdd PMOS L=5 W=80
.ENDS
TPHL = 2.1ns
TPLH = 2.3ns
Problem 12.9 Justin Wood
A B C Z
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0
By applying Boolean math, an AOI logic function can be developed. (See Below.)
_ _ _ _ _ _
Z=A⊕B⊕C=A•B•C+ B•A•C+ C•A•B
_ _ _ _
Z= (A+B+C)•(B+A+C)•(C+A+B)
________________________
_ _ _
Z= (A+B+C)•(B+A+C)•(C+A+B)
______ ______ ______
_ _ _
Z= (A+B+C)+(B+A+C)+(C+A+B)
The circuit shown in Fig. 12.27 is an edge detector. Discuss and simulate the operation of the
circuit.
Xor gate gives us logic 1 out any time we have 2 different signals at the input of the gate (logic 1
and logic 0). Other logic combination inputs gives us output of logic 1. So if we have same
inputs just one delayed then for the time of the delay inputs are going to be different whenever
input signal changes for 0 to 1 (rising edge) or from 1 to 0 (falling edge). Basically, we generate
pulse at each edge with the width of the delay at the input signals.
Figure bellow shows simulation of the circuit in Fig. 12.27. Input signals was delayed with 8
stage buffers that gave about 200 psec delays. Simulation shows that we generated pulse at
output at each edge of input signal with the width of about 200 psec.
.control
destroy all
run
plot vin vout vin_delayed
.endc
.option scale=50n
.tran 10p 4n 50p
vdd vdd 0 DC 1
Vin vin 0 DC 0 pulse 0 1 0.2n 10p 10p 1n 2n