UNIT I

8051 ARCHITECTURE

Architecture – memory organization – addressing modes – instruction set – Timers -

Interrupts - I/O ports, Interfacing I/O Devices – Serial Communication.

The microprocessor is the core of computer systems. Nowadays many

communication, digital entertainment, portable devices, are controlled by them.A
designer should know what types of components he needs, ways to reduce production
costs and product reliable.

Microprocessors

• Only CPU is inbuilt

• Needs many other extra ICs to implement a small system

The necessary tools for a microprocessor/controller

• CPU: Central Processing Unit

• I/O: Input /Output

• Bus: Address bus & Data bus
• Memory: RAM & ROM
• Timer
• Interrupt
• Serial Port
• Parallel Port
• General-purpose microprocessor
• CPU for Computers

• No RAM, ROM, I/O on CPU chip itself

Example：Intel’s x86, Motorola’s 680x0
A smaller computer

On-chip RAM, ROM, I/O ports...

Example：Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X

Microprocessor

• CPU is stand-alone, RAM, ROM, I/O, timer are separate

• designer can decide on the amount of ROM, RAM and I/O ports.
• versatility hence general-purpose usage

Microcontroller

• CPU, RAM, ROM, I/O and timer are all on a single chip
• fixed amount of on-chip ROM, RAM, I/O ports hence used for applications in
which cost, power and space are critical
• single-purpose Embedded System
• Embedded system means the processor is embedded into that application.
• An embedded product uses a microprocessor or microcontroller to do one task
only.
 • In an embedded system, there is only one application software that is typically
burned into ROM.
Example：printer, keyboard, video game player

Three criteria in Choosing a Microcontroller

• meeting the computing needs of the task efficiently and cost effectively

• speed, the amount of ROM and RAM, the number of I/O ports and timers, size,
packaging, power consumption
• easy to upgrade
• cost per unit
• availability of software development tools
assemblers, debuggers, C compilers, emulator, simulator, technical
support
• wide availability and reliable sources of the microcontrollers.

MCS-51 family, originally designed by Intel in the 1980’s

• Used in a large percentage of embedded systems

• Includes several on-chip peripherals, like timers and counters
• 128 bytes of on-chip data memory and up to 4K bytes of on-chip program
memory
• 8-bit CPU optimized for control applications

• Extensive Boolean processing (single-bit logic) capabilities

• 64K Program Memory address space
• 64K Data Memory address space
• Up to 4K bytes of on-chip Program Memory
• 128 bytes of on-chip Data RAM
• 32 bi-directional and individually addressable I/O lines
• Two 16-bit timer/counters
• 6-source/5-vector interrupt structure with two priority levels
 • Vcc（pin 40）：

• Vcc provides supply voltage to the chip.

• The voltage source is +5V.
• GND（pin 20）：ground
• XTAL1 and XTAL2（pins 19,18）
•
• Using a quartz crystal oscillator

• We can observe the frequency on the XTAL2 pin.

• RST（pin 9）：reset

• It is an input pin and is active high（normally low）.

• The high pulse must be high at least 2 machine cycles.
• It is a power-on reset.
• Upon applying a high pulse to RST, the microcontroller will reset and all
values in registers will be lost.

• /EA（pin 31）：external access

• There is no on-chip ROM in 8031 and 8032 .

• The /EA pin is connected to GND to indicate the code is stored externally.
• /PSEN ＆ ALE are used for external ROM.
• For 8051, /EA pin is connected to Vcc.
• “/” means active low.
• /PSEN（pin 29）：program store enable
• This is an output pin and is connected to the OE pin of the ROM.
• ALE（pin 30）：address latch enable

• It is an output pin and is active high.

 • 8051 port 0 provides both address and data.
• The ALE pin is used for de-multiplexing the address and data by connecting to
the G pin of the 74LS373 latch.
• I/O port pins
• The four ports P0, P1, P2, and P3.
• Each port uses 8 pins.
• All I/O pins are bi-directional.
• The 8051 has four I/O ports

•Port 0 （pins 32-39）：P0（P0.0～P0.7）

•Port 1（pins 1-8） ：P1（P1.0～P1.7）
•Port 2（pins 21-28）：P2（P2.0～P2.7）
•Port 3（pins 10-17）：P3（P3.0～P3.7）
•Each port has 8 pins.
• Named P0.X （X=0,1,...,7）, P1.X, P2.X, P3.X
Ex：P0.0 is the bit 0（LSB）of P0
Ex：P0.7 is the bit 7（MSB）of P0
• These 8 bits form a byte.
• Each port can be used as input or output (bi-direction).

Hardware Structure of I/O Pin

• Internal CPU bus：communicate with CPU

• A D latch store the value of this pin
• D latch is controlled by “Write to latch”
• Write to latch＝1：write data into the D latch
• 2 Tri-state buffer
• TB1: controlled by “Read pin”
• Read pin＝1：really read the data present at the pin
• TB2: controlled by “Read latch”
• Read latch＝1：read value from internal latch
• A transistor M1 gate
• Gate=0: open
• Gate=1: close
A Pin of Port 1

Writing “1” to Output Pin P1.X

Writing “0” to Output Pin P1.X

Reading “High” at Input Pin

Reading “Low” at Input Pin

• P1, P2, and P3 have internal pull-up resisters.

• P1, P2, and P3 are not open drain.

• P0 has no internal pull-up resistors and does not connects to Vcc inside the
8051.
• P0 is open drain.
• Compare the figures of P1.X and P0.X.
• However, for a programmer, it is the same to program P0, P1, P2 and P3.
• All the ports upon RESET are configured as output.
A Pin of Port 0
Port 0 with Pull-Up Resistors
PORT 0
(1). Port 0 is 8-bitbidirectional I/O port.

(2). Port 0 pins can be used as high-impedance inputs.

(3). Port 0 is also the multiplexed low-order address and data bus during accesses to
external program and data memory.

(4). We r using pins no. from 32 to 39.

(5). When used as an output the pin latches are programmed to 0.

(5). When used as an input the pin latches are programmed to 1.

PORT 1
(1). Port 1 is an 8-bit bidirectional I/0 port.

(2). We r using pins no. from 1 to 9.

(3). Port 1 have no dual functions.

(4). When used as an output the pin latches are programmed to 0.

(5). When used as an input the pin latches are programmed to 1.

PORT 2
(1). Port 2 is an 8-bit bidirectional I/O port.

(2). Port 2 emits the high-order address byte during fetches from external program
memory and during accesses to external data memory that use 16-bit addresses
(MOVX @DPTR).

(3). When used as an output the pin latches are programmed to 0.

(4). When used as an input the pin latches are programmed to 1.

(5). (5). We r using pins no. from 21 to 28.
PORT 3

(1). Port 3 is an 8-bit bi-directional I/0 port.

(2). We r using pins no. from 10 to 17.

• RXD (P3.0): Serial input port,

• TXD (P3.1): Serial output port,
• INT0 (P3.2): External interrupt,
• INT1 (P3.3): External interrupt,
• T0 T0 (P3.4): Timer 0 external input,
• T1 (P3.5): Timer 1 external input,
• WR (P3.6): External data memory write strobe,
• RD (P3.7): External data memory read strobe,
Port 3 Alternate Functions

RESET Value of Some 8051 Registers:

Registers

Timer / Counter:
Many microcontroller applications require the counting of external events or
the generation of time delay between two actions. Timing and counting tasks can be
implemented by software. But software loops keep the microcontroller to be occupied
and other tasks can not be done. To avoid this, hardware timers/counters are available
in 8051.
8051 has two 16 bit timer/counter registers namely Timer 0 and Timer 1. They
can be independently configured to operate as timer or counter.
When used as a timer, the register is incremented after every machine cycle. Since
one machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the
oscillator frequency.
When used as a counter, the register is incremented in response to a high to low
transition of the corresponding external input pin T0 and T1.
Timer / Counter mode control register (TMOD):
Timer0 and Timer1 have four operating modes. The Timer or Counter
operation and the mode of operation can be configured using TMOD register in the
special function registers.
 TMOD is dedicated to the two timers and can be considered to be two
duplicate 4 bit registers.

G – gate enable bit which controls RUN/STOP of timers. Set to 1 by program to

enable timer to run if bit TR in TCON is set and signal on external interrupt
INT is high.
C/T – set by program; =1 to use as counter; =0 to use as timer

Timer Control (TCON) Register:

TCON is a bit addressable special function register. TCON has control bits and
flags for the timers in the upper nibble and control bits and flags for the external
interrupts in the lower nibble.
TF – timer overflow flag. Set when timer rolls from all 1s to 0. Cleared when
interrupt processed.
TR – timer run control bit. Set to 1 by program to enable timer to count.
Cleared to 0 by Program, to halt timer. Does not reset timer.
IE – external interrupt edge flag. Set when high to low edge signal is received
on INT pin. Cleared when processor vector to interrupt service
subroutine. Not related to timer operations.
IT – external interrupt signal type control bit. Set to 1 by program to enable a
low
Timer – Modes of Operation:

The timers may operate in any of four modes that are determined by the mode
bits M1 and M0 in the TMOD register.
MODE 0:
In this mode, the timer register is configured as a 13 bit register ( TL 5 bits and
TH 8 bits ). The 5 bits in the TL sets the divide by 32 prescale to the TH as an 8 bit
counter. The timer is enabled when TR=1 and G=0 or INT =1. Setting G=1 allows the
timer to be controlled by external input INT.
Timer 0 in mode 0 (13-bit timer)
This mode is for compatibility with the previous versions of microcontrollers.
This mode configures timer 0 as a 13-bit timer which consists of all 8 bits of TH0 and
the lower 5 bits of TL0. As a result, the Timer 0 uses only 13 of 16 bits. How does it
operate? Each coming pulse causes the lower register bits to change their states. After
receiving 32 pulses, this register is loaded and automatically cleared, while the higher
byte (TH0) is incremented by 1. This process is repeated until registers count up 8192
pulses. After that, both registers are cleared and counting starts from 0.
Timer 0 in mode 1 (16-bit timer)
Mode 1 configures timer 0 as a 16-bit timer comprising all the bits of both
registers TH0 and TL0. Timer operates in the same way as in mode 0, with difference
at the registers count up to 65 536 as allowable by the 16 bits.

Timer 0 in mode 2 (Auto-Reload Timer)

Mode 2 configures timer 0 as an 8-bit timer. Actually, timer 0 uses only one 8-
bit register for counting and never counts from 0, but from an arbitrary value (0-255)
stored in another (TH0) register. The following example shows the advantages of this
mode. Suppose it is necessary to constantly count up 55 pulses generated by the
clock.
If mode 1 or mode 0 is used, It is necessary to write the number 200 to the
timer registers and constantly check whether an overflow has occured, i.e. whether
they reached the value 255. When it happens, it is necessary to rewrite the number
200 and repeat the whole procedure. The same procedure is automatically performed
by the microcontroller if set in mode 2. In fact, only the TL0 register operates as a
timer, while another (TH0) register stores the value from which the counting starts.
When the TL0 register is loaded, instead of being cleared, the contents of TH0 will be
reloaded to it. Referring to the previous example, in order to register each 55th pulse,
the best solution is to write the number 200 to the TH0 register and configure the
timer to operate in mode 2.

Timer 0 in Mode 3 (Split Timer)

Mode 3 configures timer 0 so that registers TL0 and TH0 operate as separate 8-bit
timers. In other words, the 16-bit timer consisting of two registers TH0 and TL0 is
split into two independent 8-bit timers. This mode is provided for applications
requiring an additional 8-bit timer or counter. The TL0 timer turns into timer 0, while
the TH0 timer turns into timer 1. In addition, all the control bits of 16-bit Timer 1
(consisting of the TH1 and TL1 register), now control the 8-bit Timer 1. Even though
the 16-bit Timer 1 can still be configured to operate in any of modes (mode 1, 2 or 3),
it is no longer possible to disable it as there is no control bit to do it. Thus, its
operation is restricted when timer 0 is in mode 3.
Serial Communication:
Synchronous Serial Communication
Synchronous serial Communication requires that the sender and receiver share
a clock with one another, or that the sender provide a strobe so that the receiver
knows when to “read” the next bit of the data. In most forms of serial Synchronous
communication, if there is no data available at a given instant to transmit, a fill
character must be sent so that data is always being transmitted. Synchronous
communication is usually more efficient because only data bits are transmitted
between sender and receiver, and synchronous communication can be more costly if
extra wiring and circuits are required to share a clock signal between the sender and
receiver.
A form of Synchronous transmission is used with printers and fixed disk
devices in that the data is sent on one set of wires while a clock or strobe is sent on a
different wire. Printers and fixed disk devices are not normally serial devices because
most fixed disk interface standards send an entire word of data for each clock or
strobe signal by using a separate wire for each bit of the word. In the PC industry,
these are known as Parallel devices.
The standard serial communications hardware in the PC does not support
Synchronous operations. This mode is described here for comparison purposes only.
Asynchronous Serial Transmission
Asynchronous transmission allows data to be transmitted without the sender
having to send a clock signal to the receiver. Instead, the sender and receiver must
agree on timing parameters in advance and special bits are added to each word which
are used to synchronize the sending and receiving units.
When a word is given to the UART for Asynchronous transmissions, a bit
called the "Start Bit" is added to the beginning of each word that is to be transmitted.
The Start Bit is used to alert the receiver that a word of data is about to be sent, and to
force the clock in the receiver into synchronization with the clock in the transmitter.
These two clocks must be accurate enough to not have the frequency drift by more
than 10% during the transmission of the remaining bits in the word. (This
requirement was set in the days of mechanical teleprinters and is easily met by
modern electronic equipment.)
After the Start Bit, the individual bits of the word of data are sent, with the
Least Significant Bit (LSB) being sent first. Each bit in the transmission is
transmitted for exactly the same amount of time as all of the other bits, and the
receiver “looks” at the wire at approximately halfway through the period assigned to
each bit to determine if the bit is a 1 or a 0. For example, if it takes two seconds to
send each bit, the receiver will examine the signal to determine if it is a 1 or a 0 after
one second has passed, then it will wait two seconds and then examine the value of
the next bit, and so on.
The sender does not know when the receiver has “looked” at the value of the
bit. The sender only knows when the clock says to begin transmitting the next bit of
the word. When the entire data word has been sent, the transmitter may add a Parity
Bit that the transmitter generates. The Parity Bit may be used by the receiver to
perform simple error checking. Then at least one Stop Bit is sent by the transmitter.
When the receiver has received all of the bits in the data word, it may check for the
Parity Bits (both sender and receiver must agree on whether a Parity Bit is to be
used), and then the receiver looks for a Stop Bit. If the Stop Bit does not appear when
it is supposed to, the UART considers the entire word to be garbled and will report a
Framing Error to the host processor when the data word is read. The usual cause of a
Framing Error is that the sender and receiver clocks were not running at the same
speed, or that the signal was interrupted.
Regardless of whether the data was received correctly or not, the UART
automatically discards the Start, Parity and Stop bits. If the sender and receiver are
configured identically, these bits are not passed to the host.
If another word is ready for transmission, the Start Bit for the new word can be
sent as soon as the Stop Bit for the previous word has been sent. Because
asynchronous data is “self synchronizing”, if there is no data to transmit, the
transmission line can be idle.

Sequence without framing

Framed data
 Framed data including a parity bit
RS-232 Serial Communications
The EIA RS-232 serial communication standard is a universal standard,
originally used to connect teletype terminals to modem devices. Figure shows a PC
connected to a device such as a modem or a serial printer using the RS-232
connection. In a modern PC the RS-232 interface is referred to as a COM port. The
COM port uses a 9-pin D-type connector to attach to the RS-232 cable. The RS-232
standard defines a 25-pin D-type connector but IBM reduced this connector to a 9-pin
device so as to reduce cost and size. Figure shows a simple simplex serial
communication link where data is being transmitted serially from left to right. A
single Tx (transmit) wire is used for transmission and the return (Gnd) wire is
required to complete the electrical circuit. Figure shows the inclusion of another
physical wire to support full-duplex (or half-duplex) serial communication. The
RS-232 (COM port) standard includes additional signal wires for “hand-shake”
purposes, but the fundamental serial communication can be achieved with just two or
three wires as shown. The serial data is transmitted at a predefined rate, referred to as
the baud rate. The term baud rate refers to the number of state changes per second
which is the same as the bit rate for this particular communication scheme. Typical
baud rates are: 9600 bps; 19,200 bps; 56kbps etc.
SBUF Register
SBUF is an SFR register which can be written to, so as to hold the next data
byte to be transmitted. Also it can be read from to get the latest data byte received by
the serial port. SBUF is thus effectively two registers: one for transmitting and one
for receiving.
SCON Register
The SCON (Serial Control) register is an SFR register, used for configuring
and monitoring the serial port status.

• SM0, SM1 bits define the mode of operation, such as the number of data bits
(8 or9), the clock source etc
• SM2 is set to 0 for normal operation
• REN is set to 1 to enable reception, 0 to disable reception
• TB8 is the ninth bit (parity bit) to be transmitted
• RB8 is the ninth bit received (parity bit)
• TI Transmit Interrupt flag. A logic 1 indicates that transmit buffer (SBUF) is
empty.
• This flag must be cleared by software.
• RI Receive Interrupt flag. A logic 1 indicates that data has been received in the
receive buffer (SBUF). This flag must be cleared by software.
Setting the BAUD rate
Timer/Counter 1 (in SCON mode 3) provides the serial port baud rate clock.
Usually the 8-bit auto reload operation (Timer/Counter mode 2) is used. The table
shows some values defined for the TH1 register to achieve some of the more common
baud rates.The values shown assume a processor clock rate of 11.059MHz. This is a
common crystal value for 8051 based designs as it divides down to provide accurate
baud rates.

Note. The most significant bit of the PCON register is assumed to be at 0. If this were
set to 1 the baud rate value would be doubled.
8051 Microcontroller Interrupts
There are five interrupt sources for the 8051, which means that they can
recognize 5 different events that can interrupt regular program execution. Each
interrupt can be enabled or disabled by setting bits of the IE register. Likewise, the
whole interrupt system can be disabled by clearing the EA bit of the same register.
Refer to figure below.
Now, it is necessary to explain a few details referring to external interrupts-
INT0 and INT1. If the IT0 and IT1 bits of the TCON register are set, an interrupt will
be generated on high to low transition, i.e. on the falling pulse edge (only in that
moment). If these bits are cleared, an interrupt will be continuously executed as far as
the pins are held low.
EA - global interrupt enable/disable:
0 - disables all interrupt requests.
1 - enables all individual interrupt requests.
ES - enables or disables serial interrupt:
0 - UART system cannot generate an interrupt.
1 - UART system enables an interrupt.
ET1 - bit enables or disables Timer 1 interrupt:
0 - Timer 1 cannot generate an interrupt.
1 - Timer 1 enables an interrupt.
EX1 - bit enables or disables external 1 interrupt:
0 - change of the pin INT0 logic state cannot generate an interrupt.
1 - enables an external interrupt on the pin INT0 state change.
ET0 - bit enables or disables timer 0 interrupt:
0 - Timer 0 cannot generate an interrupt.
1 - enables timer 0 interrupt.
EX0 - bit enables or disables external 0 interrupt:
0 - change of the INT1 pin logic state cannot generate an interrupt.
1 - enables an external interrupt on the pin INT1 state change.
Interrupt Priorities
It is not possible to foreseen when an interrupt request will arrive. If several
interrupts are enabled, it may happen that while one of them is in progress, another
one is requested. In order that the microcontroller knows whether to continue
operation or meet a new interrupt request, there is a priority list instructing it what to
do.
The priority list offers 3 levels of interrupt priority:
1. Reset! The absolute master. When a reset request arrives, everything is stopped
and the microcontroller restarts.
2. Interrupt priority 1 can be disabled by Reset only.
3. Interrupt priority 0 can be disabled by both Reset and interrupt priority 1.
4. The IP Register (Interrupt Priority Register) specifies which one of existing
interrupt sources have higher and which one has lower priority. Interrupt priority is
usually specified at the beginning of the program. According to that, there are several
possibilities:
If an interrupt of higher priority arrives while an interrupt is in progress, it will
be immediately stopped and the higher priority interrupt will be executed first.
If two interrupt requests, at different priority levels, arrive at the same time then the
higher priority interrupt is serviced first.
If the both interrupt requests, at the same priority level, occur one after another,
the one which came later has to wait until routine being in progress ends.
If two interrupt requests of equal priority arrive at the same time then the interrupt to
be serviced is selected according to the following priority list:
1. External interrupt INT0
2. Timer 0 interrupt
3. External Interrupt INT1
4. Timer 1 interrupt
5. Serial Communication Interrupt
The IP register bits specify the priority level of each interrupt (high or low priority).

PS - Serial Port Interrupt priority bit

o Priority 0
o Priority 1
PT1 - Timer 1 interrupt priority
o Priority 0
o Priority 1
PX1 - External Interrupt INT1 priority
o Priority 0
o Priority 1
PT0 - Timer 0 Interrupt Priority
o Priority 0
o Priority 1
PX0 - External Interrupt INT0 Priority
o Priority 0
o Priority 1
Handling Interrupt
When an interrupt request arrives the following occurs:
1. Instruction in progress is ended.
2. The address of the next instruction to execute is pushed on the stack.
3. Depending on which interrupt is requested, one of 5 vectors (addresses) is
written to the program counter in accordance to the table below:
4. These addresses store appropriate subroutines processing interrupts. Instead of
them, there are usually jump instructions specifying locations on which these
subroutines reside.
5. When an interrupt routine is executed, the address of the next instruction to
execute is poped from the stack to the program counter and interrupted program
resumes operation from where it left off.
One of the 8051’s many powerful features is it’s integrated UART, otherwise
known as a serial port. The fact that the 8051 has an integrated serial port means that
you may very easily read and write values to the serial port. If it were not for the
integrated serial port, writing a byte to a serial line would be a rather tedious process
requiring turning on and off one of the I/O lines in rapid succession to properly
"clock out" each individual bit, including start bits, stop bits, and parity bits.
Setting the Serial Port Mode
The first thing we must do when using the 8051’s integrated serial port is,
obviously, configure it. This lets us tell the 8051 how many data bits we want, the
baud rate we will be using, and how the baud rate will be determined. First, let’s
present the "Serial Control" (SCON) SFR and define what each bit of the SFR
represents:
Additionally, it is necessary to define the function of SM0 and SM1 by an additional
table:
Note: The baud rate indicated in this table is doubled if PCON.7 (SMOD) is set.
The SCON SFR allows us to configure the Serial Port. Thus, we’ll go through each
bit and review it’s function.
The first four bits (bits 4 through 7) are configuration bits.
Bits SM0 and SM1 let us set the serial mode to a value between 0 and 3,
inclusive. The four modes are defined in the chart immediately above. As you can
see, selecting the Serial Mode selects the mode of operation (8-bit/9-bit, UART or
Shift Register) and also determines how the baud rate will be calculated. In modes 0
and 2 the baud rate is fixed based on the oscillators frequency. In modes 1 and 3 the
baud rate is variable based on how often Timer 1 overflows. Well talk more about the
various Serial Modes in a moment.
The next bit, SM2, is a flag for "Multiprocessor communication." Generally,
whenever a byte has been received the 8051 will set the "RI" (Receive Interrupt) flag.
This lets the program know that a byte has been received and that it needs to be
processed. However, when SM2 is set the "RI" flag will only be triggered if the 9th
bit received was a "1". That is to say, if SM2 is set and a byte is received whose 9th
bit is clear, the RI flag will never be set. This can be useful in certain advanced serial
applications. For now it is safe to say that you will almost always want to clear this
bit so that the flag is set upon reception of any character.
The next bit, REN, is "Receiver Enable." This bit is very straightforward: If
you want to receive data via the serial port, set this bit. You will almost always want
to set this bit.
The last four bits (bits 0 through 3) are operational bits. They are used when
actually sending and receiving data--they are not used to configure the serial port.
The TB8 bit is used in modes 2 and 3. In modes 2 and 3, a total of nine data bits are
transmitted. The first 8 data bits are the 8 bits of the main value, and the ninth bit is
taken from TB8. If TB8 is set and a value is written to the serial port, the datas bits
will be written to the serial line followed by a "set" ninth bit. If TB8 is clear the ninth
bit will be "clear."
The RB8 also operates in modes 2 and 3 and functions essentially the same
way as TB8, but on the reception side. When a byte is received in modes 2 or 3, a
total of nine bits are received. In this case, the first eight bits received are the data of
the serial byte received and the value of the ninth bit received will be placed in RB8.
TI means "Transmit Interrupt." When a program writes a value to the serial port, a
certain amount of time will pass before the individual bits of the byte are "clocked
out" the serial port. If the program were to write another byte to the serial port before
the first byte was completely output, the data being sent would be garbled. Thus, the
8051 lets the program know that it has "clocked out" the last byte by setting the TI
bit. When the TI bit is set, the program may assume that the serial port is "free" and
ready to send the next byte.
Finally, the RI bit means "Receive Interrupt." It funcions similarly to the "TI"
bit, but it indicates that a byte has been received. That is to say, whenever the 8051
has received a complete byte it will trigger the RI bit to let the program know that it
needs to read the value quickly, before another byte is read.
Setting the Serial Port Baud Rate
Once the Serial Port Mode has been configured, as explained above, the
program must configure the serial ports baud rate. This only applies to Serial Port
modes 1 and 3. The Baud Rate is determined based on the oscillators frequency when
in mode 0 and 2. In mode 0, the baud rate is always the oscillator frequency divided
by 12. This means if youre crystal is 11.059Mhz, mode 0 baud rate will always be
921,583 baud. In mode 2 the baud rate is always the oscillator frequency divided by
64, so a 11.059Mhz crystal speed will yield a baud rate of 172,797.
In modes 1 and 3, the baud rate is determined by how frequently timer 1
overflows. The more frequently timer 1 overflows, the higher the baud rate. There are
many ways one can cause timer 1 to overflow at a rate that determines a baud rate,
but the most common method is to put timer 1 in 8-bit auto-reload mode (timer mode
2) and set a reload value (TH1) that causes Timer 1 to overflow at a frequency
appropriate to generate a baud rate.
To determine the value that must be placed in TH1 to generate a given baud
rate, we may use the following equation (assuming PCON.7 is clear).
Writing to the Serial Port
Once the Serial Port has been propertly configured as explained above, the
serial port is ready to be used to send data and receive data. If you thought that
configuring the serial port was simple, using the serial port will be a breeze.
To write a byte to the serial port one must simply write the value to the SBUF
(99h) SFR. For example, if you wanted to send the letter "A" to the serial port, it
could be accomplished as easily as:
MOV SBUF,#A
Upon execution of the above instruction the 8051 will begin transmitting the
character via the serial port. Obviously transmission is not instantaneous--it takes a
measureable amount of time to transmit. And since the 8051 does not have a serial
output buffer we need to be sure that a character is completely transmitted before we
try to transmit the next character.
The 8051 lets us know when it is done transmitting a character by setting the
TI bit in SCON. When this bit is set we know that the last character has been
transmitted and that we may send the next character, if any. Consider the following
code segment:
CLR TI ;Be sure the bit is initially clear
MOV SBUF,#A ;Send the letter A to the serial port
JNB TI,$ ;Pause until the TI bit is set.
The above three instructions will successfully transmit a character and wait for
the TI bit to be set before continuing. The last instruction says "Jump if the TI bit is
not set to $"--$, in most assemblers, means "the same address of the current
instruction." Thus the 8051 will pause on the JNB instruction until the TI bit is set by
the 8051 upon successful transmission of the character.
Reading the Serial Port
Reading data received by the serial port is equally easy. To read a byte from the
serial port one just needs to read the value stored in the SBUF (99h) SFR after the
8051 has automatically set the RI flag in SCON.
For example, if your program wants to wait for a character to be received and
subsequently read it into the Accumulator, the following code segment may be used:
JNB RI,$ ;Wait for the 8051 to set the RI flag MOV A,SBUF ;Read the character
from the serial port
The first line of the above code segment waits for the 8051 to set the RI flag;
again, the 8051 sets the RI flag automatically when it receives a character via the
serial port. So as long as the bit is not set the program repeats the "JNB" instruction
continuously.
Once the RI bit is set upon character reception the above condition
automatically fails and program flow falls through to the "MOV" instruction which
reads the value.
Instruction
An instruction is an order or command given to a processor by a computer
program. All commands are known as instruction set and set of instructions is known
as program. 8051 have in total 111 instructions, i.e. 111 different words available for
program writing.

Where first part describes WHAT should be done, while other explains HOW
to do it. The latter part can be a data (binary number) or the address at which the data
is stored. Depending upon the number of bytes required to represent 1 instruction
completely.
Instructions are divided into 3 types;

One/single byte instruction.

Two/double byte instruction.

Three/triple byte instruction.

One/single byte instructions :

If operand is not given in the instruction or there is no digits present with instruction,
the instructions can be completely represented in one byte opcode.

OPCODE 8 bit
Two/double byte instruction:

If 8 bit number is given as operand in the instruction, the such instructions can
be completed represented in two bytes.

First byte OPCODE

Second byte 8 bit data or I/O port

Three/triple byte instruction:

If 16 bit number is given as operand in the instructions than such instructions

can be completely represented in three bytes 16 bit number specified may be data or
address.
First byte will be instruction code. Second byte will be 8 LSB’s of 16 bit number.
Third byte will be 8 MSB’s of 16 bit number.

• First byte OPCODE.

• Second byte 8 LSB’s of data/address.

• Third byte 8 MSB’S of data/address.

Addressing Modes
Addressing modes specifies where the data (operand) is. They specify the
source or destination of data (operand) in several different ways, depending upon the
situation.

Addressing modes are used to know where the operand located is.

There are 5 types of addressing modes:

• Register addressing.

• Direct addressing.

• Register indirect addressing.

• Immediate addressing.

• Index addressing.

Register Addressing Mode

In register addressing mode; the source and/or destination is a register. In this
case; data is placed in any of the 8 registers(R0-R7); in instructions it is specified
with letter Rn (where N indicates 0 to 7).

For example;

ADD A, Rn (This is general instruction).

ADD A, R5 (This instruction will add the contents of register R5 with the
accumulator contents).
Direct Addressing Mode
In direct addressing mode; the address of memory location containing data to
be read is specified in instruction. In this case; address of the data is given with the
instruction itself.
For example;

MOV A, 25H (This instruction will read/move the data from internal RAM address
25H and store it in the accumulator.

Register indirect addressing mode

In register indirect addressing mode; the contents of the designated register are
used as a pointer to memory. In this case; data is placed in memory, but address of
memory location is not given directly with instruction.
For example;
MOV A,@R0 This instruction moves the data from the register whose address is in
the R0 register into the accumulator.

Immediate Addressing Mode

In immediate addressing mode, the data is given with the instruction itself. In
this case; the data to be stored in memory immediately follows the opcode.
For example;

MOV A, #25H (This instruction will move the data 25H to accumulator.

Index Addressing Mode

Offset (from accumulator) is added to the base index register( DPTR OR
Program Counter) to form the effective address of the memory location. In this case;
this mode is made for reading tables in the program memory.
For example;

MOVC A, @ A + DPTR ( This instruction moves the data from the memory to
accumulator; whose address is computed by adding the contents of accumulator and
DPTR)
8051 Instruction Sets
Types Of Instructions
• Data transfer instructions.

• Arithmetic instructions.

• Logical instructions.

• Logical instructions with bits.

• Branch instructions.
Data Transfer Instructions
These instructions move the content of one register to another one. Data can be
transferred to stack with the help of PUSH and POP instructions.
MNEMONIC DESCRIPTION BYTES

MOV A,Rn (A) (Rn) 1

MOV A,Rx (A) (Rx) 2
MOV A,@Ri (A) (Ri) 1
MOV A,#X (A) Data 2
MOV Rn,A (Rn) (A) 1
MOV Rn, Rx (Rn) (Rx) 2
MOV Rn, #X (Rn) Data 2
MOV Rx, A (Rx) (A) 2
MOV Rx, Rn (Rx) (Rn) 2
MOV Rn, #X (Rn) Data 2
MOV Rx, A (Rx) (A) 2
MOV Rx, Rn (Rx) (Rn) 2
MOV Rx, Ry (RX) (Ry) 3
MOV Rx, @ Ri (Rx) (Ri) 2
MOV Rx, # X (Rx) Data 3
MOV @ Ri, A (Ri) (A) 1
MOV @ Ri, Rx (Ri) (Rx) 2
MOV @ Ri, #X (Ri) Data 2
MOV DPTR, #X (DPTR) Data 3
MOVC A @ (A) (A+DPTR) 1 A+DPTR
MOVC A@ (A) (A+PC) 1A+PC
MOVX A,@ Ri A (Ri) 1
MOVX A, @ (A) (DPTR) 1
MOVX @Ri, A (Ri) (A) 1
MOVX @ (DPTR) (A) 1
PUSH Rx Push directly 2 addressed Rx register on stack
POP Rx (A) (Rx) 2
XCH A, Rn (A) (Rn) 1
XCH A, Rx (A) (Rx) 2
XCH A, @Ri (A) (Ri) 1
XCHD Exchange 4 lower 1 bits in accumulator with indirectly
addressed register
Arithmetic Instructions
These instructions perform several basic operations. After execution, the result is
stored in the first operand. 8 bit addition, subtraction, multiplication, increment-
decrement instructions can be performed.

MNEMONICS DESCRIPTION BYTE

ADD A, Rn A = A + Rn 1
ADD A, Rx A = A + Rx 2
AAD A, @ Ri A = A+ Ri 1
ADD A, # X A = A + Byte 2
ADDC A, Rn A = A + Rn + C 1
ADDC A , Rx A = A + Rx + C 2
ADDC A, @ Ri A = A + Ri + C 1
ADDC A, # X A = A + Byte + C 2
SUBB A, Rn A = A – Rn – 1 1
SUBB A, Rx A = A – Rx – 1 2
SUBB A, @ Ri A = A – Ri – 1 1
SUBB A, # X A = A – Byte – 1 2
INC A A=A+1 1
INC Rn Rn = Rn + 1 1
INC Rx Rx = Rx + 1 2
INC @ Ri Ri = Ri + 1 1
DEC A A=A– 1 1
DEC Rn Rn = Rn – 1 1
DEC Rx Rx = Rx – 1 2
DEC @ Ri Ri = Ri – 1 1
INC DPTR DPTR = DPTR + 1 1
MUL AB B:A = A * B 1
DIV AB A = [A/B] 1
DA A Decimal adjustment of 1 accumulator according to BCD code
Logical Instructions
These instructions perform logical operations between two register contents on
bit by bit basis.After execution, the result is stored in the first operand.
MNEMONIC DESCRIPTION BYTE

ANL A, Rn (A) (A) ^ (Rn) 1

ANL A, Rx (A) (A) ^ (Rx) 2

ANL A,@ Ri (A) (A) ^ (Ri) 1

ANL A, # X (A) (8 bit data) ^ (A) 2

ANL Rx, A (Rx) (A) ^ (Rx) 2

ANL Rx,# X (Rx) (8 bit data) ^ (Rx) 3

ORL A, Rn (A) (A) + (Rn) 1

ORL A, Rx (A) (A) + (Rx) 2

ORL A, @ Ri (A) (A) + (Ri) 2

ORL Rx, A (Rx) (A) + (Rx) 2

ORL Rx,# X (Rx) (8 bit data) + (Rx) 2

XORL A, Rn Logical exclusive 1 OR operation between the contents of
accumulator and R register.

XORL A, Rx Logical exclusive OR 2 operation between the contents of thE

accumulator and directly addressed register Rx.

XORL A,@ Ri Logical exclusive OR 1 operation between the contents of the

accumulator and directly addressed register.
XORL A, # X Logical exclusive OR 2 operation between the contents
of accumulator and the given 8 bit data.

XORL Rx, A Logical exclusive OR 2 operation between the contents

of the accumulator and directly addressed register Rx.
XORL Rx, # X Logical exclusive OR 3 operation between the contents of the
directly addressed register Rx and the given 8 bit data.

CLR A (A) 0 1
CPL A (A) (/A) 1
SWAP A (A3-0) (A7-4) 1
RL A (An + 1) (An) 1
RLC (An + 1) (An) 1
RR A (An) (An + 1) 1
RRC A (An) (An + 1) 1

Logical Instructions On Bits

Similar to logical instructions, these instructions also perform logical operations. The
difference is that these operations are performed on single bits.
MNEMONIC DESCRIPTION BYTE

CLR C (C=0) 1

CLR bit clear directly addressed bit 2

SETB C (C=1) 1
SETB bit Set directly 2
addressed bit

CPL C (1 = 0, 0 = 1) 1

CPL bit Complement directly 2 addressed bit

ANL C, bit Logical AND operation 2 between Carry bit and directly
addressed bit.

ANL C,/bit Logical AND operation 2 between Carry bit and inverted
directly addressed bit.

ORL C, bit Logical OR operation 2 between Carry bit and directly

addressed bit.

ORL C,/bit Logical OR operation 2 between Carry bit and inverted

directly addressed bit.

MOV C, bit Move directly addressed 2 bit to carry bit.

MOV bit, C Move Carry bit to directly 2 addressed bit.

Program Flow Control Instructions

In this group, instructions are related to the flow of the program, these are used
to control the operation like, JUMP and CALL instructions. Some instructions are
used to introduce delay in the program, to the halt program.
MNEMONIC DESCRIPTION BYTE

ACALL adr11 (PC) (PC) + 2 2

(SP) - (SP) + 1
((SP)) - (PC7 – 0)
(SP) - (SP) + 1
((SP)) - (PC15-8)
LCALL adr16 (PC) - (PC) + 3 3
(SP) - (SP) + 1
 ((SP)) - (PC7-0)
(SP) - (SP) + 1
((SP)) - (PC15-8)
RET (PC15-8) ((SP)) 1
(SP) - (SP) – 1
(PC7-0) - ((SP))
(SP) - (SP) – 1
RETI (PC15-8) ((SP)) 1
(SP) - (SP) – 1
(PC7-0) - ((SP))
(SP) - (SP) – 1
AJMP addr11 (PC) (PC) + 2
LJMP addr16 (PC) addr15-0 3
SJMP rel short jump from 2 (from -128 to +127 locations in relation
to first next instruction)

JC rel (PC) (PC) + 2 2

IF ( C ) = 1 THEN (PC) (PC) + rel
JNC rel (PC) (PC) + 2 2
IF ( C) = 0 THEN (PC) (PC) + rel
JB bit, rel Jump if bit set 3
bit is set. Short jump.
JBC bit, rel Jump if bit is not set 3
Short jump.
JMP @A + DPTR (PC) (A) + (DPTR) 1
JZ rel (PC) (PC) + 2 2
IF (A) = 0
THEN (PC) (PC) + rel
JNZ rel (PC) (PC) + 2 2
IF (A) = 0
THEN (PC) (PC) + rel
CJNE A, Rx, rel Compare the contents 3
 of acc. And directly addressed register Rx. Jump if they are
different. Short jump.
CJNE A, #X, rel (PC) (PC) + 3 3
IF ( A) < > data
THEN (PC) (PC) + relative offset
CJNE @ RI, # x, rel (PC) (PC) + 3 3
IF (Rn) <> data
THEN (PC) (PC) + relative
offset
IF (Rn) < data
THEN ( C ) 1
ELSE ( C ) 0
CJNE @ Ri, # X, rel (PC) (PC) + 3 3
IF ((Ri)) <> data
THEN (PC) (PC) + relative
offset
DJNZ Rn , rel (PC) (PC) + 2 2
(Rn) (Rn) - 1
IF (Rn) > 0 or (Rn) < 0
THEN (PC) (PC) + rel
DJNZ Rx, rel (PC) (PC) + 2 3
(Rx) (Rn) – 1
IF (Rx) > 0 or (Rx) < 0
THEN (PC) (PC) + rel
NOP No operation 1