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UNIT II
PIC Microcontrollers
PIC stands for Peripheral Interface Controller given by Microchip Technology to
identify its single-chip microcontrollers. These devices have been very successful in
8-bit microcontrollers. The main reason is that Microchip Technology has
continuously upgraded the device architecture and added needed peripherals to the
microcontroller to suit customers' requirements
Low - end PIC Architectures :
Microchip PIC microcontrollers are available in various types. When PIC
microcontroller MCU was first available from General Instruments in early 1980's, the
microcontroller consisted of a simple processor executing 12-bit wide instructions
with basic I/O functions. These devices are known as low-end architectures. They
have limited program memory and are meant for applications requiring simple
interface functions and small program & data memories. Some of the low-end device
numbers are
12C5XX
16C5X
16C505
Mid range PIC Architectures
Mid range PIC architectures are built by upgrading low-end architectures with more
number of peripherals, more number of registers and more data/program memory.
Some of the mid-range devices are
16C6X
16C7X
16F87X
Program memory type is indicated by an alphabet.
C = EPROM
F = Flash
RC = Mask ROM
Popularity of the PIC microcontrollers is due to the following factors.
1.
Speed: Harvard Architecture, RISC architecture, 1 instruction cycle = 4 clock
cycles.
2.
Instruction set simplicity: The instruction set consists of just 35 instructions (as
opposed to 111 instructions for 8051).
3.
Power-on-reset and brown-out reset. Brown-out-reset means when the power
supply goes below a specified voltage (say 4V), it causes PIC to reset; hence
malfunction is avoided.
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4.
A watch dog timer (user programmable) resets the processor if the
software/program ever malfunctions and deviates from its normal operation.
5.
PIC microcontroller has four optional clock sources.
o
Low power crystal
o
Mid range crystal
o
High range crystal
o
RC oscillator (low cost).
6.
Programmable timers and on-chip ADC.
7.
Up to 12 independent interrupt sources.
8.
Powerful output pin control (25 mA (max.) current sourcing capability per pin.)
9.
EPROM/OTP/ROM/Flash memory option.
10. I/O port expansion capability.
11. Free assembler and simulator support from Microchip at www.microchip.com
CPU Architecture:
The CPU uses Harvard architecture with separate Program and Variable (data)
memory interface. This facilitates instruction fetch and the operation on
data/accessing of variables simultaneously.

Fig 16.1 CPU Architecture of PIC microcontroller

PIC Memory Organisation:
PIC microcontroller has 13 bits of program memory address. Hence it can address up
to 8k of program memory. The program counter is 13-bit. PIC 16C6X or 16C7X
program memory is 2k or 4k. While addressing 2k of program memory, only 11- bits
are required. Hence two most significant bits of the program counter are ignored.
Similarly, while addressing 4k of memory, 12 bits are required. Hence the MSb of the
program counter is ignored.
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Fig 16.2 Program Memory map

The program memory map of PIC16C74A is shown in Fig 16.2.
On reset, the program counter is cleared and the program starts at 00H. Here a 'goto'
instruction is required that takes the processor to the mainline program.
When a peripheral interrupt, that is enabled, is received, the processor goes to 004H.
A suitable branching to the interrupt service routine (ISR) is written at 004H.
Data memory (Register Files):
Data Memory is also known as Register File. Register File consists of two
components.
1.
General purpose register file (same as RAM).
2.
Special purpose register file (similar to SFR in 8051).

Specifications of some popular PIC microcontrollers are as follows:

Program Data RAM I/O ADC Timers CCP
Device Memory
(bytes)
Pins
8/16 (PWM)
(14bits)
bits
16C74A
4K
192
33 8 bits x
2/1
2
EPROM
8
channels
16F877 8K Flash 368 (RAM) 33 10 bits x 2/1
2
256
8
(EEPROM)
channels
3

USAR
T SPI /
I2C
USART
SPI /
I2 C
USART
SPI /
I2 C

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Interrupt
Sources
12
15

Instruction
Set
35
35

Device
16C74A
16F877
PIC Microcontroller Clock
Most of the PIC microcontrollers can operate upto 20MHz. One instructions
cycle (machine cycle) consists of four clock cycles.

Fig 17.1 Relation between instruction cycles and clock cycles for PIC
microcontrollers
Instructions that do not require modification of program counter content get
executed in one instruction cycle.
Although the architectures of various midrange 8 - bit PIC microcontroller are
not the same, the variation is mostly interns of addition of memory and
peripherals. We will discuss here the architecture of a standard mid-range PIC
microcontroller, 16C74A. Unless mentioned otherwise, the information given
here is for a PIC 16C74A
microcontroller Chip.

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Architecture of PIC16C74A

Fig 17.2 Basic Architecture of PIC 16C74A

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The basic architecture of PIC16C74A is shown in fig 17.2. The architecture

consists of Program memory, file registers and RAM, ALU and CPU registers.
It should be noted that the program Counter is 13 - bit and the program
memory is organised as 14 - bit word. Hence the program Memory capacity is
8k x 14 bit. Each instruction of PIC 16C74A is 14 - bit long. The various CPU
registers are discussed here.
CPU registers (registers commonly used by the CPU)
W, the working register, is used by many instructions as the source of an
operand. This is similar to accumulator in 8051. It may also serve as the
destination for the result of the instruction execution. It is an 8 - bit register.

Fig 17.3 W register

STATUS Register
The STATUS register is a 8-bit register that stores the status of the processor.
This also stores carry, zero and digit carry bits.
STATUS - address 03H, 83H
Fig 17.4 STATUS register
C = Carry bit
DC = Digit carry (same as auxiliary carry)
Z = Zero bit
NOT_TO and NOT_PD - Used in conjunction with PIC's sleep mode
RP0- Register bank select bit used in conjunction with direct addressing mode.
FSR Register
(File Selection Register, address = 04H, 84H)
FSR is an 8-bit register used as data memory address pointer. This is used in
indirect addressing mode.
INDF Register
(INDirect through FSR, address = 00H, 80H)
INDF is not a physical register. Accessing INDF access is the location pointed
to by FSR in indirect addressing mode.
PCL Register
(Program Counter Low Byte, address = 02H, 82H)
PCL is actually the lower 8-bits of the 13-bit program counter. This is a both
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readable and writable register.

PCLATH Register
(Program Counter Latch, address = 0AH, 8AH)
PCLATH is a 8-bit register which can be used to decide the upper 5bits of the
program counter. PCLATH is not the upper 5bits of the program counter.
PCLATH can be read from or written to without affecting the program
counter. The upper 3bits of PCLATH remain zero and they serve no purpose.
When PCL is written to, the lower 5bits of PCLATH are automatically loaded
to the upper 5bits of the program counter, as shown in the figure.

Fig 17.5 Schematic of how PCL is loaded from PCLATH

Program Counter Stack
An independent 8-level stack is used for the program counter. As the program
counter is 13bit, the stack is organized as 8x13bit registers. When an interrupt
occurs, the program counter is pushed onto the stack. When the interrupt is
being serviced, other interrupts remain disabled. Hence, other 7 registers of the
stack can be used for subroutine calls within an interrupt service routine or
within the mainline program.

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Register File Map

Fig 17.6 Register File Map

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It can be noted that some of the special purpose registers are available both in
Bank-0 and Bank-1. These registers have the same value in both banks.
Changing the register content in one bank automatically changes its content in
the other bank.
Port Structure and Pin Configuration of PIC 16C74A
As mentioned earlier, there is a large variety of PIC microcontrollers.
However, the midrange architectures are widely used. Our discussion will
mainly confine to PIC16C74A whose architecture has most of the required
features of a mid-range PIC microcontroller. Study of any other mid-range PIC
microcontroller will not cause much variation from the basic architecture of
PIC 16C74A ..
PIC 16C74A has 5 I/O Ports. Each port is a bidirectional I/O port. In addition,
they have the following alternate functions.

In addition to I/O pins, there is a Master clear pin (MCLR) which is equivalent
to reset in 8051. However, unlike 8051, MCLR should be pulled low to reset
the micro controller. Since PIC16C74Ahas inherent power-on reset, no special
connection is required with MCLR pin to reset the micro controller on poweron.
There are two VDD pins and two VSS pins. There are two pins (OSC1 and
OSC2) for connecting the crystal oscillator/ RC oscillator. Hence the total
number of pins with a 16C74A is 33+7=40. This IC is commonly available in a
dual-in-pin (DIP) package.

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Fig 17.7 Pin configuration of PIC 16C74A

Fig 16.3 Data Memory map

The special purpose register file consists of input/output ports and control registers.
Addressing from 00H to FFH requires 8 bits of address. However, the instructions that
use direct addressing modes in PIC to address these register files use 7 bits of
instruction only. Therefore the register bank select (RP0) bit in the STATUS register
is used to select one of the register banks.
In indirect addressing FSR register is used as a pointer to anywhere from 00H to FFH
in the data memory.

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Addressing Modes of PIC Microcontroller

Addressing modes
RAM memory locations can be accessed directly or indirectly.
1. Direct Addressing
Direct Addressing is done through a 9-bit address. This address is obtained by
connecting 7th bit of direct address of an instruction with two bits (RP1, RP0) from
STATUS register as is shown on the following picture. Any access to SFR registers is
an example of direct addressing.
CODE:
Bsf STATUS, RP0 ;Bankl
movlw 0xFF
;w=0xFF
movwf TRISA
;address of TRISA register is taken from
;instruction movwf

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2. Indirect Addressing
Indirect unlike direct addressing does not take an address from an instruction but
derives it from IRP bit of STATUS and FSR registers. Addressed location is accessed
via INDF register which in fact holds the address indicated by a FSR. In other words,
any instruction which uses INDF as its register in reality accesses data indicated by a
FSR register. Let's say, for instance, that one general purpose register (GPR) at
address 0Fh contains a value of 20. By writing a value of 0Fh in FSR register we will
get a register indicator at address 0Fh, and by reading from INDF register, we will get
a value of 20, which means that we have read from the first register its value without
accessing it directly (but via FSR and INDF). It appears that this type of addressing
does not have any advantages over direct addressing, but certain needs do exist during
programming which can be solved smoothly only through indirect addressing.

Such examples include sending a set of data via serial communication, working with
buffers and indicators (which will be discussed further in a chapter with examples), or
erasing a part of RAM memory (16 locations) as in the following instance.

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Reading data from INDF register when the contents of FSR register is equal to zero
returns the value of zero, and writing to it results in NOP operation (no operation).
Reading from EEPROM Memory
Setting the RD bit initializes transfer of data from address found in EEADR register to
EEDATA register. As in reading data we don't need so much time as in writing, data
taken over from EEDATA register can already be used further in the next instruction.

Sample of the part of a program which reads data in EEPROM, could look something
like the following:

After the last program instruction, contents from an EEPROM address zero can be
found in working register w.
Writing to EEPROM Memory
In order to write data to EEPROM location, programmer must first write address to
EEADR register and data to EEDATA register. Only then is it useful to set WR bit
which sets the whole action in motion. WR bit will be reset, and EEIF bit set
following a writing what may be used in processing interrupts. Values 55h and AAh
are the first and the second key whose disallow for accidental writing to EEPROM to
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occur. These two values are written to EECON2 which serves only that purpose, to
receive these two values and thus prevent any accidental writing to EEPROM
memory. Program lines marked as 1, 2, 3, and 4 must be executed in that order in even
time intervals. Therefore, it is very important to turn off interrupts which could change
the timing needed for executing instructions. After writing, interrupts can be enabled
again.
Example of the part of a program which writes data 0xEE to first location in
EEPROM memory could look something like the following:

NOTE: It is recommended that WREN be turned off the whole time except when
writing data to EEPROM, so that possibility of accidental writing would be
minimal. All writing to EEPROM will automatically clear a location prior to writing a
new.

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Guidelines from Microchip Technology

For writing assembly language program Microchip Technology has suggested the
following guidelines.
1.
Write instruction mnemonics in lower case. (e.g., movwf)
2.
Write the special register names, RAM variable names and bit names in
upper case. (e.g., PCL, RP0, etc.)
3.
Write instructions and subroutine labels in mixed case. (e.g., Mainline,
LoopTime)
Instruction Set:
The instruction set for PIC16C74A consists of only 35 instructions. Some of these
instructions are byte oriented instructions and some are bit oriented instructions.
The byte oriented instructions that require two parameters (For example, movf f,
F(W)) expect the f to be replaced by the name of a special purpose register (e.g.,
PORTA) or the name of a RAM variable (e.g., NUM1), which serves as the source
of the operand. 'f' stands for file register. The F(W) parameter is the destination of
the result of the operation. It should be replaced by:
F, if the destination is to be the source register.
W, if the destination is to be the working register (i.e., Accumulator or W
register).
The bit oriented instructions also expect parameters (e.g., btfsc f, b). Here 'f' is to
be replaced by the name of a special purpose register or the name of a RAM
variable. The 'b' parameter is to be replaced by a bit number ranging from 0 to 7.
For example:
Z equ 2
btfsc STATUS, Z
Z has been equated to 2. Here, the instruction will test the Z bit of the STATUS
register and will skip the next instruction if Z bit is clear.
The literal instructions require an operand having a known value (e.g., 0AH) or a
label that represents a known value.
For example:
NUM equ 0AH ;
Assigns 0AH to the label NUM ( a constant )
movlw NUM ;
will move 0AH to the W register.
Every instruction fits in a single 14-bit word. In addition, every instruction also
executes in a single cycle, unless it changes the content of the Program Counter.
These features are due to the fact that PIC micro controller has been designed on
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the principles of RISC (Reduced Instruction Set Computer) architecture.

Instruction set:
Mnemonics
bcf f, b
bsf f, b
clrw
clrf f
movlw k
movwf f
movf f, F(W)
swapf f, F(W)
andlw k
andwf f, F(W)
andwf f, F(W)
iorlw k
iorwf f, F(W)
xorlw k
xorwf f, F(W)
addlw k
addwf f, F(W)
sublw k
subwf f, F(W)
rlf f, F(W)
rrf f, F(W)
btfsc f, b
btfss f, b

Description
Clear bit b of register f
Set bit b of register f
Clear working register W
Clear f
Move literal 'k' to W
Move W to f
Move f to F or W
Swap nibbles of f, putting result in F or W
And literal value into W
And W with F and put the result in W or F
And W with F and put the result in W or F
inclusive-OR literal value into W
inclusive-OR W with f and put the result in
F or W
Exclusive-OR literal value into W
Exclusive-OR W with f and put the result in
F or W
Add the literal value to W and store the
result in W
Add W to f and store the result in F or W
Subtract the literal value from W and store
the result in W
Subtract f from W and store the result in F
or W
Copy f into F or W; rotate F or W left
through the carry bit
Copy f into F or W; rotate F or W right
through the carry bit
Test 'b' bit of the register f and skip the next
instruction if bit is clear
Test 'b' bit of the register f and skip the next
16

Instructio
n Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1/2
1/2

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instruction if bit is set

Decrement f and copy the result to F or W;
decfsz f, F(W)
1/2
skip the next instruction if the result is zero
Increment f and copy the result to F or W;
incfcz f, F(W)
1/2
skip the next instruction if the result is zero
goto label
Go to the instruction with the label "label"
2
Go to the subroutine "label", push the
call label
2
Program Counter in the stack
Return from the subroutine, POP the
retrun
2
Program Counter from the stack
Retrun from the subroutine, POP the
retlw k
2
Program Counter from the stack; put k in W
Return from Interrupt Service Routine and
retie
2
re-enable interrupt
clrwdt
Clear Watch Dog Timer
1
sleep
Go into sleep/ stand by mode
1
nop
No operation
1
Encoding of instruction:
As has been discussed, each instruction is of 14-bit long. These 14-bits contain
both op-code and the operand. Some examples of instruction encoding are shown
here.
Example-1:
bcf f, b
Clear 'b' bit of register 'f'
Operands:
0 f 127
0b7
Encoding:

The instruction is executed in one instruction cycle, i.e., 4 clock cycles. The
activities in various clock cycles are as follows.

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Example-2:
goto K
Operand:
Operation:

Unit II

Go to label 'k' instruction

0 K 2047 (11-bit address is specified)
K
PC <10:0>
PCLATH <4:3>
PC <12:11>

Encoding:

Since this instruction requires modification of program Counter, it takes two

instruction cycles for execution.
Q-Cycle activities are shown as follows.

Discussion on I/O ports of PIC16C74A:

PIC16C74A has five I/O ports. Port-B, Port-C and Port-D have 8 pins each. Port-A
and Port-E have 6 and 3 pins respectively. Each port has bidirectional digital I/O
capability. In addition, these I/O ports are multiplexed with alternate functions for the
peripheral devices on the microcontroller. In general, when a peripheral is enabled,
that pin may not be used as a general purpose I/O pin. Each port latch has a
corresponding TRIS (Tri-state Enable) register for configuring the port either as an
input or as an output. The port pins are designated by the alphabet R, followed by the
respective port (viz. A, B, C, D or E) and the pin number. For example, Port-A pins
are named as RA0, RA1, etc.
Port-A
Port-A pins RA0-RA3 and RA5 are similar. These pins function (alternate function)
as analog inputs to the analog-to-digital converter.

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Fig 19.1 RA0-RA3 and RA5 pin of Port-A

The structure of Port-A pins RA0-RA3 and RA5 is shown in the figure. TRISA
register decides whether the port-pin is configured as an input or as an output (digital)
pin. Setting a TRISA register bit puts the corresponding output driver in high
impedance mode. In this mode, the pin can be used as a digital or analog input.
Clearing a bit in the TRISA register puts the contents of the data latch on the selected
pins, i.e., the pin functions as a digital output. Pins RA0-RA and RA5 have current
sourcing capability of 25mA.
The alternate function of RA4 pin is Timer-0 clock input (T0CKI). RA4 pin is an
open drain pin and hence requires external pull-up when configured as output pin. It is
shown in the following figure.

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Fig 19.2 RA4 pin Configuration

Configuration of Port-A pins
Example : Set RA0-RA3 as outputs and RA4 - RA5 as inputs.
bcf STATUS, RP0 ;
Select Bank-0
clrf PORTA ;
Clears the data latch
bsf STATUS, RP0 ;
Select Bank-1
movlw 30H ;
W
03H ( data direction )
movwf TRISA ;
Set RA0-RA3 as outputs, RA4-RA5 as inputs
Port-B
Port-B is an 8-bit bidirectional I/O port. The data direction in Port-B is controlled by
TRISB register. Setting a bit in TRISB register puts the corresponding output in high
impedance input mode. When a bit in TRISB is made zero, the corresponding pin in
Port-B outputs the content of the latch (output mode).
Each port pin has a weak internal pull-up that can be enabled by clearing bit
of
OPTION register (bit-7). When a pin is configured in the output mode, the weak pullup is automatically turned off. Internal pull-up is used so that we can directly drive a
device from the pins.

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Overview of Timer Modules :

PIC 16C74A has three modules, viz., Timer-0, Timer-1 and Timer-2. Timer-0 and
Timer-2 are 8-bit timers. Timer-1 is a 16-bit timer. Each timer module can
generate an interrupt on timer overflow.
Timer-0 Overview:
The timer-0 module is a simple 8-bit UP counter. The clock source can be either
the internal clock (fosc /4) or an external clock. When the clock source is external,
the Timer-0 module can be programmed to increment on either the rising or
falling clock edge. Timer-0 module has a programmable pre-scaler option. This
pre-scaler can be assigned either to Timer-0 or the Watch dog timer, but not to
both.
The Timer-0 Counter sets a flag T0IF (Timer-0 Interrupt Flag) when it overflows
and can cause an interrupt at that time if that interrupt source has been enabled,
(T0IE = 1), i.e., timer-0 interrupt enable bit = 1.
OPTION Register Configuration :
Option Register (Addr: 81H) Controls the prescaler and Timer -0 clock source.
The following OPTION register configuration is for clock source = fosc /4 and no
Watchdog timer.

Timer-0 use without pre-scalar

Internal clock source of f osc /4. (External clock source, if selected, can be applied
at RA4/TOCKI input at PORTA).
The following diagram shows the timer use without the prescaler.

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Fig 20.1 Timer - 0 operation without prescaler

Timer-0 use with pre-scalar:
The pre-scalar can be used either with the Timer-0 module or with the Watchdog
timer. The pre-scalar is available for Timer-0 if the pre-scalar assignment bit PSA
in the OPTION register is 0. Pre-scalar is a programmable divide by n counter that
divides the available clock by a pre-specified number before applying to the
Timer-0 counter.

Fig 20.2 Timer - 0 with prescaler

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Fig 19.3 Pins RB0-RB3 of Port-B

Configuration of Port-B pins
Example :
Set RB0-RB3 as outputs, RB4-RB5 as inputs, RB7 as output.

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bcf STATUS, RP0

clrf PORTB
bsf STATUS, RP0
movlw 70H
movwf TRISB
Timer - 1 Module
Timer 1 module is a 16-bit timer/counter consisting of two 8-bit registers
(TMR1H and TMR1L) which are readable and writable. The TMR1 register
pair (TMR1H:TMR1L) increments from 0000H to FFFFH and rolls over to
0000H. The TMR1 interrupt, if enabled, is generated on overflow, which
sets the interrupt flag bit TMR1IF (bit-0 of PIR1 register). This interrupt can
be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE
(bit-0 of the PIE1 register).
The operating and control modes of Timer1 are determined by the special
purpose register T1CON.
Various bits of T1CON register are given as follows:-

Fig 21.1 T1CON Register

TMR1 ON : Timer1 ON bit
0 = stops Timer 1;
1 = Enables Timer 1
TMR1CS : Timer 1 Clock source Select Bit
1 = External Clock (RCO/T1OSO/T1CKI)
0 = Internal Clock (
)
: Timer 1 External Clock Input Synchronization Bit
(Valid if TMR1CS = 1)
1 - Do not synchronize
0 - Synchronize
T1OSCEN: Oscillator enable control bit
1 = Oscillator is enabled
0 = Oscillator is shut off
Timer 1 Input Clock Prescaler
Select bits

Prescaler
Value
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T1CKP T1CKPS0
S1
1
1
1
0
0
1
0
0

Unit II

1:8
1:4
1:2
1:1

Fig 21.2 Operation of Timer 1

Timer 1 can operate in one of the two modes
As a timer (TMR1CS = 0). In the timer mode, Timer 1 increments in

every instruction cycle. The timer 1 clock source is

. Since the
internal clock is selected, the timer is always synchronized and there
is no further need of synchronization.
As a counter (TMR1CS = 1). In the counter mode, external clock
input from the pin RCO/T1CKI is selected.

Reading and writing Timer 1

Reading TMR1H and TMR1L from Timer 1, when it is running from an
external clock source, have to be done with care. Reading TMR1H or
TMR1L for independent 8 - bit values does not pose any problem. When the
16-bit value of the Timer is required, the high byte (TMR1H) is read first
followed by the low byte (THR1lL). It should be ensured that TMR1L does
not overflow (that is goes from FFH to 00H) since THR1H was read. This
condition is verified by reading TMR1H once again and comparing with
previous value of TMR1H.
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Example Program
Reading 16bit of free running Timer 1
movf TMR1H
;
read high byte
movwf TMPH
;
store in TMPH
movf TMR1L
;
read low byte
movwf TMPL
;
store in TMPL
movf TMR1H, W
;
read high byte in W
subwf TMPH, W
;
subtract 1 st read with 2 nd read
btfsc STATUS, Z
;
and check for equality
goto next ;
; if the high bytes differ, then there is an overflow
; read the high byte again followed by the low byte
movf TMR1H, W
;
read high byte
movwf TMPH
movf TMR1L, W
;
read low byte
movwf TMPL
next : nop
Timer 2 Overview

Fig 21.3 Schematic diagram showing operation of Timer 2

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Timer 2 is an 8 - bit timer with a pre-scaler and a post-scaler. It can be used

as the PWM time base for PWM mode of capture compare PWM (CCP)
modules. The TMR2 register is readable and writable and is cleared on
device reset.
The input clock (
) has a pre-scaler option of 1:1, 1:4 or 1:16 which is
selected by bit 0 and bit 1 of T2CON register respectively.
The Timer 2 module has an 8bit period register (PR2). Timer-2 increments
from 00H until it is equal to PR2 and then resets to 00H on the next clock
cycle. PR2 is a readable and writable register. PR2 is initailised to FFH on
reset.
The output of TMR2 goes through a 4bit post-scaler (1:1, 1:2, to 1:16) to
generate a TMR2 interrupt by setting TMR2IF.

Fig 21.4 The T2CON Register

Interrupt Logic in PIC 16C74A
PIC 16C74A microcontroller has one vectored interrupt location (i.e.,
0004H) but has 12 interrupt sources. There is no interrupt priority. Only one
interrupt is served at a time. However interrupts can be masked. The
interrupt logic is shown below :

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Fig 21.5 Schematic diagram showing the interrupt logic for PIC

Capture / Compare /PWM (CCP) Modules:

PIC16C74A has two CCP Modules. Each CCP module contains a 16 bit register
(two 8-bit registers) and can operate in one of the three modes, viz., 16-bit capture,
16-bit compare, or up to 10-bit Pulse Width Modulation (PWM). The details of the
two modules (CCP1 and CCp2) are given as follows.
CCP1 Module:
CCP1 Module consists of two 8-bit registers, viz., CCPR1L (low byte) and CCPR1H
(high byte). The CCP1CON register controls the operation of CCP1 Module.
CCP2 Module:
CCP2 Module consists of two 8 bit registers, viz., CCPR2L (Low byte) and CCPR2H
(high byte). The CCP1CON register controls the operation of CCP2 Module.
Both CCP1 and CCP2 modules are identical in operation with the exception of the
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operation of special event trigger.

The following table shows the timer resources for the CCP Mode.
CCP Mode
Timer Used
Capture
Timer 1
Compare

Timer 1

PWM
Timer 2
CCP1CON Register (Address 17H )
CCP2CON Register is exactly similar to CCP1CON register. CCP2CON Register
address is 1DH. CCP1CON controls CCP module1 where as CCP2CON controls
CCP Module2.

Bit 5-4:
CCP1X CCP1Y: PWM least significant bits. These bits are of no use in Capture
mode. In PWM Mode, these bits are the two Lsbs of the PWM duty cycle. The eight
Msbs are found in CCPR1L. Thus the PWM mode operates in 10-bit mode.
Bit 3-0:
CCP1M3:CCP1MO (CCP1 Mode select bits)
0000=Capture/Compare/PWM Mode off
0100=Capture mode, every falling edge
0101=Capture mode, every rising edge
0110=Capture mode, every 4 th rising edge
0111=Capture mode, every 16 th rising edge
1000=Compare mode, set output on match (CCP1IF bit is set)
1001=Compare mode, clear output on match (CCP1IF bit is set)
1010=Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1
pin unaffected)
1011=Compare mode, trigger special event (CCP1IF bit is set;CCP1 resets Tmr1;
CCP2 resets TMR1 and starts A/D conversion if A/D module is Enabled)
11XX=PWM mode.
Capture Mode (CCP1):
Capture Mode captures the 16-bit value of TMR1 into CCPR1H:CCPR1L register
pair in response to an event occurring on RC2/CCP1 pin. Capture Mode for CCP2 is
exactly similar to that of CCP1.
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An event on RC2/CCP1 pin is defined as follows:

Every falling edge
Every rising edge.
Every 4 th rising edge.
Every 16 th rising edge.
As mentioned earlier, this event is decided by bit 3-0 of CCP1CON register.
Schematic diagram for capture mode of operation

Fig 22.1 Capture operation

Required condition for capture mode:
1. RC2/CCP1 pin should be configured as an input by setting TRISC (bit 2).
2. Timer 1 should be operated from the internal clock (fosc/4), i.e., timer mode or
in synchronized counter mode.
Compare Mode (CCP1)
Compare mode for CCP2 is similar to that of CCP1, except that in special event
trigger mode, CCP1 resets TMR1 only, whereas CCP2 resets TMR1 and starts A/D
conversion if A/D module is enabled.
In compare mode, the 16-bit CCPR1 register value is compared against TMR1
register pair (TMR1H and TMR1L) value. When a match occurs, the RC2/CCP1 pin
is driven high or driven low or remains unchanged as decided by CCP1CON<3:0>
bits.

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Fig 22.2 Compare Operation

Required conditions for compare mode
1. RC2/CCP1 pin must be configured as an output by clearing TRISC<2> bit.
2. Timer-1 should be operated in timer mode (i.e., internal clock source of fosc/4)
or in synchronized counter mode.
In software interrupt mode, CCP1IF bit is set but CCP1 pin in unaffected.
As shown in the figure, in special event trigger mode, both CCP1 and CCP2 intiates
an A/D conversion.
PWM mode (CCP1)
Both CCP1 and CCP2 have similar operation in PWM mode. Here we will discuss
PWM with respect to CCP1.
In PWM mode, the CCP1 pin produces upto a 10-bit resolution Pulse Width
Modulation (PWM) output. RC2/CCP1 pin should be configured in the uotput mode
by clearing TRISC<2> bit.
The schematic block diagram of CCP1 module in PWM mode is shown in the figure.

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Fig 22.3 PWM Operation

It can be noted that PR2 (Period Register, 8 bit) decides the PWM period where
CCPR1L (8-bits) and CCP1CON <5:4> (2-bits) decide the PWM duty cycle. When
TMR2 equals PR2, the SR latch is set and RC2/CCP1 pin is pulled high. In the same
time, TMR2 is cleared and the duty cycle value available in CCPR1L is latched to
CCPR1H. CCPR1H, CCP1CON <5:4> decide the duty cycle and when this 10-bit
ewquals the TMR2+2 prescaler or Q-bits, the SR latch is set and RC2/CCP1 pin is
driven low.

A PWM output as shown has a time period. The time for which the output stays high
is called duty cycle.
PWM Period
The PWM period is specified by writing to PR2 register. The PWM period can be
calculated using the following formula:
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PWM period = [( PR 2) + 1] 4 T osc (TMR2 prescale value)

PWM frequency = 1/ PWM period
When TMR2 is equal to PR2, the following events occur on the next increment cycle.
TMR2 is cleared
the CCP1 pin is set (if PWM duty cycle is 0
The PWM duty cycle is latched from CCPR1L into CCPR1H
PWM duty cycle
The PWM duty cycle is specified by writing to the CCPR1L register and to
CCP1CON < 5 : 4 > bits. Up to 10-bit resolution is available where CCPR1L
contains the eight MSBs and CCP1CON < 5 : 4 > contains the two LSB's. The 10-bit
value is represented by CCPR1L : CCP1CON < 5 : 4 >.
The PWM duty cycle is given by
PWM duty cycle = (CCPR1L : CCP1CON < 5 : 4 > ). T osc . (TMR2 prescale value)
To understand the 10-bit counter configuration from Timer-2, let us first see the
counting mechanism of Timer-2, as shown in Fig 22.4.

Fig 22.4 Counting mechanism in Timer - 2

If the prescaler is 1, the 10-bit counter is configured as follows

Fig 22.5 Prescaler set to divide by one

If the prescaler is 4, the 10-bit counter is configured as follows.

Fig 22.6 Prescaler programed to divide by four

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If the prescaler is 16, the 10-bit counter is realized as follows.

Fig 22.7 Prescaler programed to divide by 16

Although CCPR1L and CCP1CON < 5 : 4 > can be written to at anytime, the duty
cycle value is not latched into CCPR1H until a match between PR2 and TMR2
occurs. In PWM mode, CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM
duty cycle. This double buffering is essential for glitchless PWM operation. When
the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q
clock or 2-bits of prescaler, the CCP1 pin is cleared. Maximum PWM resolution
(bits) for a given PWM frequency can be calculated as

If the PWM duty cycle is longer than the PWM period, then the CCP1 pin will not be
cleared.
PWM Period and duty cycle calculation
Example:
Desired PWM frequency = 78.125 kHz
f osc = 20MHz
TMR2 Prescalar = 1

Find the maximum resolution of duty cycle that can be used with a 78.124 kHz
frequency and 20 MHz oscillator.

256 = 2PWM Resolution

At most, an 8-bit resolution duty cycle can be obtained from a 78.125 kHz frequency
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and 20 MHz oscillator

ie, 0 CCPR1L : CCP1CON <5 : 4> 255 .
Any value greater than 255 will result in a 100 % duty cycle. The following table
gives the PWM frequency fPWM if fosc = 20MHz
Duty cycle resolution

10-Bit counter scale

PR2 value

Prescaler 1

Prescaler 4

Prescaler 16

10 bit

1024

255

19.53 KHz

4.88 kHz

1.22 kHz

10 bit

1000

249

20kHz

5kHz

1.25kHz

8 bit

256

63

78.125kHz

19.53kHz

4.88kHz

6 bit

64

15

312.5kHz

78.125kHz

19.53kHz

ADC Module
An analog-to-digital converter (ADC) converts an analog signal into an equivalent
digital number. PIC 16C74A has an inbuilt ADC with the following features

8-bit conversion
8 analog input channels
An analog multiplexer
A sample and hold circuit for signal on the selected input channel
Alternative clock sources for carrying out conversion
Adjustable sampling rate
Choice of an internal or external reference voltage
Interrupt to microcontroller on end of conversion

Port A and Port E pins are used for analog inputs/reference voltage for ADC. In A/D
conversion, the input analog voltage is digitized and an equivalent digital output is
generated as shown in the figure.

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Fig 23.1 Digital output versus analog input

Port-A pins (Alternate functions)
RA0/AN0
can be used as analog input-0
RA1/AN1
can be used as analog input-1
RA2/AN2
can be used as analog input-2
RA3/AN3/Vref can be used as analog input-3 or analog reference voltage
RA4/TOCKI clock input to Timer-0
RA5/ /AN4 can be used for analog input 4 or slave select for the
synchronized serial port.
Port-E pins (Alternate functions)
RE0/ /AN5 - can be used as analog input-5
RE1/ /AN6 - can be used as analog input-6
RE2/ /AN7 - can be used as analog input-7
PIC microcontroller has internal sample and hold circuit. The input signal should be
stable across the capacitor before the conversion is initiated.

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Fig 23.2 Sample and Hold Circuit

After waiting for the sampling time, a conversion can be initiated. The ADC Circuit
will open the sampling switch and carry out the conversion of the input voltage as it
was at the moment of opening of the switch. Upon completion of the conversion, the
sampling switch is again closed and VHold once again tracks VSource.
Using the A/D Converter
Registers ADCON1, TRISA, and TRISE must be initialized to select the reference
voltage and input channels. The first step selects the ADC clock from among the four
choices (fosc/2, fosc/8, fosc/32, and RC). The constraint for selcting clock frequency is
that the ADC clock period must be 1.6micro seconds or greater.
The A/D module has 3registers. These registers are: A/D result register (ADRES)
A/D control register 0 (ADCON 0)
A/D control register 1 (ADCON 1)
The ADCON0 register, which is shown below, controls the operation of A/D module.

Fig 23.3 ADCON0 register

Bit 7-6 - A/D Clock select bits
ADCS1:ADCS0
00 = fosc/2
01 = fosc/8
10 = fosc/32
11 = fRC- clock derived from an internal RC oscillator
Bit 5-3 - A/D Channel Select
CHS2:CHS0

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000 - Channel 0 - AN0

001 - Channel 1 - AN1
010 - Channel 2 - AN2
011 - Channel 3 - AN3
100 - Channel 4 - AN4
101 - Channel 5 - AN5
110 - Channel 6 - AN6
111 - Channel 7 - AN7
Bit 2 - A/D conversion status bit
GO /
if A/D Converter is enabled (ie. ADON = 1) then
If GO /
= 1, A/D conversion is in progress
(setting this bit starts A/D conversion)
If GO /
= 0, A/D conversion is not in progress
(This bit is automatically cleared by hardware when A/D
conversion is complete)
Bit1 - Unimplemented
Bit 0 - ADON: A/D On bit
1. A/D Converter module is ON
2. A/D Converter module is OFF
ADCON1 Register
This register specifies the analog inputs

Fig 23.4 ADCON1 register

PCFG2:P
CFG0
000
001
010
011
100
101
11X

RA0 RA1

RA2

RA5

RA3

RE0

RE1 RE2 VREF

A
A
A
A
A
A
D

A
A
A
A
D
D
D

A
A
A
A
D
D
D

A
VREF
A
VREF
A
VREF
D

A
A
D
D
D
D
D

A
A
D
D
D
D
D

A
A
A
A
A
A
D

38

A
A
D
D
D
D
D

VDD
RA3
VDD
RA3
VDD
RA3
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Fig 23.5 PCFG2:PCFG0 = A/D Port configuration control bits

A = Analog input
D = Digital I/O

Fig 23.6 Schematic diagram of A/D convertor analog inputs and reference
voltage
Steps for A/D conversion

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1. Configure A/D module

Configure analog inputs/voltage reference and digital I/O
(ADCON1)
Select A/D Channel (ADCON0)
Select A/D Conversion Clock (ADCON0)
Turn on A/D Module (ADCON0)
2. Configure A/D Interrupt (Optional)
Clear ADIF bit in PIR1 register
Set ADIE bit in PIE1 register
Set GIE bit
3. Wait for required acquisition time
4. Start Conversion - set GO/
bit (ADCON0)
5. Wait for A/D conversion to complete, by either polling GO/
bit or by
waiting for the A/D interrupt
6. Read A/D result registers (ADRES). Clear ADIF if required.
Example Program
A/D conversion with interrupt
org 000H
goto Mainline
org 020H
bsf STATUS, RP0
;
Select Bank 1
clrf ADCON 1
;
Configure A/D inputs
bsf PIE1, ADIE
;
Enable A/D interrupt
bcf STATUS, RP0
;
Select Bank 0
movlw 081H
;
Select fosc/32, channel 0, A/D on
movwf ADCON0
bcf
PIR1, ADIF
bsf
INTCON, PEIE
;
Enable peripheral and global interrupt bits
bsf
INTCON, GIE
;
interrupt bits
; Ensure that the required sampling time of the selected input channel has been
elapsed.
; Then conversion may be started.
; bsf ADCON0, GO
; Start A/D conversion.
; ADIF bit will be set and GO/
; bit is cleared upon completion of A/D conversion.
Interrupt Service Routine
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Org 004H
Movf ADRES, W ; Result of A/D conversion in W
Most of mid range PIC microcontrollers include a Synchronous Serial Port (SSP)
Module. The discussion in this section is relevant to PIC16C74A only. SSP Module
section can be configured in either of the following two modes.
Serial Peripheral Interface (SPI)
Inter Integrated Circuit (I2C)
Either of these modes can be used to interconnect two or more PIC chips to each other
using a minimal number of wires for communication. Alternatively, either can be used
to connect a PIC microcontroller to a peripheral chip. When I 2C mode is selected, the
peripheral chip must also have an I 2C interface. On the other hand, the SPI mode
provides the clock and serial data lines for direct connection to shift registers. This
leads to increased I/O interface capability and an arbitrary number of I/O devices can
be connected to a PIC microcontroller. SPI can also achieve data rate significantly
higher than I2C. Both the communication methods are synchronous, i.e., the data
transfer is synchronized with an explicit clock signal.
Two special purpose registers control the synchronous serial port (SSP) operations.
These registers are:
SSPCON (Synchronous Serial Port Control Register), Address: 14H
SSPSTAT(Synchronous Serial Port status Register), Address: 94H
Serial Peripheral Interface (SPI)
Port-C three pins, viz., RC5/SDO, RC4/SDI and RC3/SCK/SCL are mainly used for
SPI mode. In addition, one Port-A pin, viz., RA5/ /AN4 is used for slave select.
The schematic block diagram of SPI is shown in the figure

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Fig 24.1 Schematic diagram under SPI Mode

The SPI port requires RC3/SCK pin to be an output that generates the clock signal
used by the external shift registers. When SPI is configured in the slave mode,
RC3/SCK pin works as the input for the clock.

When a byte is written to SSPBUF register, it is shifted out of RC5/SDO pin in

synchronous with the emitted clock pulses on RC3/SCK pin. The MSB of SSPBUF is
the first bit to appear on RC5/SDO pin. Simultaneously, the same write to SSPBUF
also initiates the 8 bit data reception into SSPBUF of whatever appears on RC4/SDI
pin at the time of rising edges of the clock on SCK pin. Hence shifting-in and shiftingout of data occur simultaneously.

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Fig 24.2 SPI Master / Slave Connection

The schematic diagram of SPI Master/Slave connection is shown in the figure.
Timing diagram for data transfer in 'Master mode' :
SSPIF interrupt flag is cleared by the user software if already in the set mode. The
interrupt is enabled. Any write to SSPBUF initiates the data transfer, i.e., transmission
and reception. The clock pulses (8 clock pulses) are output through SCK pin. The data
is received through SDI. When CKP=1 (SSPCON<4>), data changes at SDO at
negative clock transition and is read through SDI at positive clock transition. The idle
state of clock is high. If CKP=0, data appears at SDO at positive clock transition and
is read through SDI at negative clock transition. The idle state of the clock is low.
These are shown in the following diagrams.

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(i) Timing diagram for CKP=1

(ii) Timing diagram for CKP=0

Fig 24.3 Timing Diagram under SPI mode
Though SPI is a serial communication interface, it can be used to realize multiple
output parallel ports and multiple input parallel ports. We will consider this
realization of an output parallel port and an input port separately.
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Parallel Output Port Realization

A parallel 8-bit output port can be realized through SPI with the help of a shift
register chip (74HC595) as shown in Fig 25.1. RC5/SD0 pin outputs serial data
while RC3/SCK oin outputs the serial clock. Since input data transfer is not required,
port pin RC4/SDI is used to latch the shift register data to the output pins of the shift
register. Hence RC4 is configured as an output pin.

Fig 25.1 PIC connection (in SPI mode) with a shift register
When an 8-bit data is written to SSPBUF, the data is shifted out of RC5/SD0 pin.
With CKP = 1, the data is stable at the positive transition but changes at the negative
transition. The shift shifts the data at the positive clock transition. After 8 clock
pulses, all 8-bits are shifted in the shift register. The completion of data transfer is
indicated by SSPIF interrupt flag becoming ' 1' . The interrupt service routine make
RC4 ' 1' , thus latching the 8-bit data to the output of the shift register. The

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configuration of various registers are shown in Fig 25.2

Port configurations

Fig 25.2 Various Register Configurations

Parallel Input Port Realization
A shift register (74HC165) is connected to the PIC microcontroller as shown in Fig
25.3. Pin RD7 is configured as an output and is used to load 8-bit data to the shift
register. A dummy write to SSPBUF initiates data transfer. Data bit is read into
RC4/SDI at the negative clock transition (CKP = 0) where the data bit is stable. Data
is shifted in the shift register at the position clock transition as shown in the timing
diagram. After the completion of data transfer, SSPIF interrupt flag goes high.
Therafter the 8-bit data can be read by reading SSPBUF.

Port configurations
Fig 25.4 gives the configurations various registers for inputs parallel port
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realization.

Fig 25.4 Configurations of various registers for parallel input port

I2C Communication in PIC Microcontroller
I 2C stands for Inter-Integrated circuit. I 2C communication is a two wire bidirectional interface for connecting one or more master processors with one or
more slave devices, such as an EEPROM, ADC, RAM, LCD display, DAC, etc.
I 2C interface requires two open drain I/O pins, viz. SDA (Serial Data) and SCL
(Serial Clock).
The reason for open drain connection is that the data transfer is bi-directional and
any of the devices connected to the I 2C bus can drive the data line (SDA). The
serial clock line (SCL) is usually driven by the master. Since SDA and SCL pins
are open drain pins, external pull-up resistances are required for operation of I 2C
bus.
A typical I2C bus showing the connection of multi-master and multi-slave
configuration is shown in the following figure.

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Fig 26.1 Multimaster Multislave Connection

Some conventions are followed in I2C communication. Let us assume that there is
one master and one slave and 8-data bits are sent. We will initially assume that the
master is the transmitter and the slave is the receiver. The clock is driven by the
master. On receiving 8-bits, an acknowledgement bit is driven by the receiver on
SDA line. The acknowledgement bit is usually Low (0). The following diagram
shows the data communication pattern having 8 data bits and one
acknowledgement bit.

Fig 26.2 Timing diagram for data transfer

The following features are to be noted 1. SDA line transmits/ receives data bits. MSB is sent first.
2. Data in SDA line is stable during clock (SCL) high. A new bit is initiated at
the negative clock transition after a specified hold time.
3. Serial clock (SCL) is driven by the master.
4. An acknowledgement bit (0) is driven by the receiver after the end of
reception. If the receiver does not acknowledge, SDA line remains high (1).
I2C bus transfer consists of a number of byte transfers within a START condition
and either another START condition or a STOP condition. During the idle state
when no data transfer is taking place, both SDA and SCL lines are released by all
the devices and remains high. When a master wants to initiate a data transfer, it
pulls SDA low followed by SCL being pulled low. This is called START
condition. Similarly, when the processor wants to terminate the data transfer it first
releases SCL (SCL becomes high) and then SDA. This is called a STOP condition.
START and STOP conditions are shown in the diagram as follows.

Fig 26.3 Timing diagram for START and STOP Conditions

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START and STOP conditions are unique and they never happen within a data
transfer.
Data Communication Protocol:
In I2C communication both 7-bit and 10-bit slave addressing are possible. In 7-bit
addressing mode 128 slaves can be interfaced with a single master. Similarly, in
10-bit addressing mode, 1024 slaves can be interfaced with the master. We will
discuss here 7-bit addressing mode only. 10-bit addressing mode is similar to 7-bit
addressing except from the fact that the number of address bits is more.
Following a 'start' condition, the master sends a 7-bit address of the slave on SDA
line. The MSB is sent first. After sending 7-bit address of the slave peripheral, a
R/ (8th bit) bit is sent by the master. If R/ bit is '0', the following byte (after the
acknowledgement bit) is written by the master to the addressed slave peripheral. If
R/ =1, the following byte (after the acknowledgement bit) has to be read from the
slave by the master.
After sending the 7-bit address of the slave, the master sends the address (usually 8
bit) of the internal register of the slave wherefrom the data has to be read or
written to. The subsequent access is automatically directed to the next address of
the internal register.
The following diagrams give the general format to write and read from several
peripheral internal registers.

R/

Fig 26.4 Data transfer protocol for writing to a slave device

(Read / Write) bit indicates whether the data is to be written by the master or
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read by the master. If R/ is 1, the subsequent data are to be read by the master. If
R/ = 0, the subsequent data are to be written by the master to the addressed
slave. It has to be noted that the slave address is sent first, following a 'start'
condition. The addressed slave responds by acknowledging and gets ready for data
transfer.
If data has to be read from a specific address of the slave device, the master sends
the 7-bit address of the slave first following a 'start' condition. R/ bit is sent as
'low'. The addressed slave acknowledges by pulling the ACK line low. The master
then sends the 8-bit internal address of the slave from which data has to be read.
The slave acknowledges. Since R/ bit was initially 0, the master is in the write
mode. To change this to read mode, the 'start' condition is again generated
followed by 7-bit address of the slave with R/ = 1. The slave acknowledges. The
slave then sends data from previously specified internal address to the master. The
master acknowledges by pulling ACK bit low. The data transfer stops when the
master does not acknowledge the data reception and a 'stop' condition is generated.

Software for I2 C Communication

The data transfer in I2C mode is not automatically controlled by hardware unlike
UART. The Master has to be programmmed by suitable software to generate
'Start' / 'Stop' conditions, various data bits from sending / receving ,
acknowledgement bit and clock signal. Here, we will discuss some examples of
I2C software.
Since SDA (RC4) and SCL (RC3) are both open drain pins, they can be
configured either as an output or as an input. When a PIC Processor is
configured is I2C master, the SCL pin will function as open drain output while
the SDA pin can be either an input or an open drain output. Hence, the software
I 2C will repeatedly access TRISC, the data direction register for PORT C.
However, TRISC is located in bank-1 at an address 87H, which cannot be
accessed by direct addressing without changing RP0 bit to 1 as given in the
following instruction.
bsf STATUS, RP0
Then required bit of TRISC can be changed followed by clearing RP0 and
reverting back to Bank-0.
bcf STATUS, RP0
Alternately, the indirect pointer FSR can have the address of TRISC and the
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required bit setting and bit clearing can be done indirectly.

Consider the following definitions.
SCL equ 3
SDA equ 4
The instruction bsf INDF, SDA will release the SDA line(as RC4/SDA pin is
configured as an input, hence tristated), letting the external pullup resister pull it
high or some I 2C Slave device/Chip pull it low.
When FSR is used for indirect addressing, care should be taken to restore FSR
value when subroutine is completed and the program returns to the main line
program.
I 2 C Subroutine
SDA equ 4
SCL equ 3
The following subroutine DATA_OUT transfers out three bytes, i.e.,
ADDRDEV, ADDR8, and DATAWRTE
DATA_OUT:
call START
; Generate start condition
movf ADDRDEV, W ; Sends 7-bit peripheral
address with R/ =0
call TRBYTE
; Transmit
movf ADDR8, W
; Send 8-bit internal address
call TRBYTE
movf DATAWRTE, W ; Send data to be written
call TRBYTE
call STOP
; Generate Stop condition
return
The DATA_IN subroutine, which is given below transfers out ADDRDEV
(with R/ =0) and ADDR8, restarts and transfers out ADDRDEV (with R/
=1) and read one byte back into RAM variable DATARD.
DATA_IN:
call START
movf ADDRDEV, W
; Send 7-bit peripheral
address R/ =0
call TRBYTE
movf ADDR8, W
; Send int. address
call TRBYTE
call START1
; Restart
movf ADDRDEV, W
; Send 7-bit peripheral
address R/ =1
iorlwl 01H
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call TRBYTE
bsf TRBUF, 7
; Generate NO ACK
call RCVBYTE
movwf DATARD
call STOP
return
The 'START' subroutine initializes I2C bus and then generates START
condition on the I 2C bus. START1 bypasses the initialization of I 2C.
START:
movlw 3BH
;enables I2C master mode
by programming SSPCON
movwf SSPCON
bcf PORTC, SDA
; drive SDA low when it
is an o/p
movlw TRISC
;set indirect pointer to
TRISC
movwf FSR
START1:
bsf INDF, SDA
; SDA=1
bsf INDF , SCL
; SCL=1
call DELAY

; Generates a suitable

bcf INDF, SDA

call DELAY

; SDA=0
; Generate a suitable

bcf INDF, SCL

return

;SCL=0

bcf INDF, SDA

bsf INDF, SCL
call DELAY

;SDA=0
; SCL=1
; Generate a suitable

delay

delay

STOP:

delay
bsf INDF, SDA
;SDA=1
return
The subroutine 'TRBYTE' send out the byte available in w. It returns with Z=1
if ACK occurs. It returns with Z=0 if NOACK occurs.
TRBUF is an 8-bit RAM variable used for temporary storage. The bits are
shifted to carry flag (C) and the carry bit transmitted successively. Data transfer
is complete when all 8-bits are transmitted. Setting C = 1 initially sets an index
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for 8-bits to be transferred. C is rotated through TRBUF. After transmitting C,

C-bit is cleared. When TRBUF is completely cleared, all 8-bis are transmitted.
TRBYTE:
movwf TRBUF
bsf
STATUS,C
TR_1:

rlf
TRBUF, F
movf RBUF,F
btfss STATUS, Z
call out_bit
; Send a bit available in C
btfss STATUS, Z
goto TR_1
call
in_bit
; Get the ACK bit in RCBUF<0>
movlw 01H
;
andwf RCBUF, W ; Store the complement of ACK bit in Z flag
return
The RCVBYTE subroutine receives a byte from I2 C into W using a RAM
variable RCBUF buffer.
Call RCVBYTE with bit 7 of TRBUF clear for ACK
Call RCVBYTE with bit 7 of TRBUF set for NOACK
RCBUF is an 8-bit RAM variable used for recieving the data. the bit is recieved
in the RCBUF<0> and is rotated successively through RCBUF as shown. The
reception ends when all 8-bits are recieved.
RCVBYTE:
movlw 01H
movwf RCBUF
; Keep an index for 8-bits to be recieved.

RCV_1:
rlf
RCBUF, F
call In_bit
btfss STATUS, C
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goto RCV_1
rlf
TRBUF, F
call Out_bit
movf RCBUF,w
return
The out_bit subroutine transmits carry bit, then clears the carry bit.
Out_bit:
bcf INDF, SDA
btfsc STATUS, C
bsf INDF, SDA
; Send carry bit
bsf INDF, SCL
call DELAY
bcf INDF, SCL
bcf STATUS,C
; Clear carry bit
return
The in_bit subroutine receives one bit into bit-0 of RCBUF.
In_bit:
bsf INDF,SDA
bsf INDF, SCL
bcf RCBUF, 0
btfsc PORTC, SDA
; Check SDA line for data bit
bsf RCBUF, 0
bcf INDF, SCL
return
Example of I 2 C interfacing
DAC interfacing on I 2 C bus:
MAX518 is a dual 8-bit Digital to Analog Converter (DAC) with I2C interface.
The address of the device is selectable through two pins AD1 and AD0 . This
device works in I2C slave mode. The connection diagram is shown as follows.

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Fig 27.1 I2C Interface for DAC

The 7-bit device address is given as

For
the
present
connection
AD1
=
0
The
device
address
is
Three bytes are sent to output an analog voltage.
First byte (Address of the DAC and R/ bit )

Second byte (DAC Configuration)

55

and
AD0
010

1
1101

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Unit II

Third byte
(The 8-bit digital data(B) to be converted to analog voltage)
B
Analog output voltage = V DD x B/256

Special Features
ICSP

In Circuit Serial
Programming

WDT

Watch dog timer

BOR

Brown Out reset

POR

Power on reset

PWRT

PoWeR up Time

OST

Oscillator start up timer

SLEEP

PIC microcontroller
sleepmode

WDT
If your software goes haywire then this timer resets the processor. To stop the
reset the well behaved software must periodically issue the CLRWDT instruction
to stop a resert. The WDT runs using its own oscillator. It runs during sleep and
shares Timer 0 prescaler.
POR
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Power On Reset starts PIC microcontroller initialization when it detects a rising

edge on MCLR.
PWRT
If you enable this then 72ms after a POR the PIC microcontroller is started.

OST
Oscillator Startup Timer delays for 1024 oscillator cycles after PWRT (if PWRT is
enabled) ensuring that the oscillator has started and is stable. It is automatic and
only used for crystal oscillator modes and is active after POR or wake from sleep.
SLEEP
Sleep mode (or low power consumption mode) is entered by executing the 'SLEEP'
command. The device can wake from sleep caused by an external reset, Watch
Dog Timer timeout, INT pin RB port change or peripheral interrupt.

Parallel slave port (PSP)

PIC Microcontroller offers a mechanism by which an 8-bit parallel bidirectional
data transfer can be achieved between a PIC Microcontroller and a PC. PIC
Microcontroller's Port-D and Port-E are used in this data transfer. For this data
transfer, Port-D of PIC Microcontroller is configured as a Parallel slave Port
(PSP) by setting bit-4 of TRISE Register. The pins of Port-E function as control
pins
(
,
and
)
for
data
transfer.
The connection diagram between PC and the PIC Microcontroller in PSP Mode
is shown below.

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Fig 28.1 Interfacing a PIC-microcontroller with a PC using Parallel Slave

Port
Registers used for PSP Mode
ADCON1:
Three low significant bits (PCFG2-PCFG0) are set to enable Port-E pins for
digital I/O
ADCON1, ADD: 9F H

TRISE:
This register plays a crucial role in PSP configuration and control. The lower
three bits control the data direction of PortE. the upper four bits are used in
conjunction with parallel slave port as shown here.
TRISE, ADD: 89 H

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As explained, PSP Mode facilitates bidirectional 8-bit parallel data transfer.

After ADCON1<b2-b0> and TRISE<b4, b2-b0> bits are set by the user
program, PORTD and PORTE are configured for PSP. When PC wants to write
an 8-bit data to PIC, it addresses the PIC microcontroller and the I/O address
decoding circuit makes go low selecting the PIC chip. PC also makes
(I/O write) pin low and floats the data through its data bus (b7-b0). The data is
written to PORTD and IBF flag in TRISE Register is set indicating that a byte is
waiting at PORTD input buffer to be read by the PIC. Simultaneously PSPIF
flag bit of PIR1 register is set and an interrupt is generated if PSPIE, PEIE and
GIE bits have been set (i.e., the peripheral PSP interrupt is enabled.). After the
data is read from PORTD, IBF bit automatically becomes zero; however PSPIF
bit has to be cleared by software. If a second byte is written by the PC before the
first byte is read, the second byte is lost and the IBOV flag in TRISE register is
set indicating this loss.
Similarly a byte can also be read by the PC from the PIC microcontroller. When
PIC writes a byte to PORTD, OBF flag is set indicating that the byte is waiting
to be read by the PC. When the PC reads this bytes, OBF flag in TRISE Register
is automatically cleared and the interrupt flag bit PSPIF is set indicating that the
byte has been read by the PC from PIC microcontroller.

59