MM54HC4511/MM74HC4511 BCD-to-7 Segment Latch/Decoder/Driver

January 1988

MM54HC4511/MM74HC4511
BCD-to-7 Segment Latch/Decoder/Driver
General Description Features
This high speed latch/decoder/driver utilizes advanced sili- Y Latch storage of input data
con-gate CMOS technology. It has the high noise immunity Y Blanking input
and low power consumption of standard CMOS integrated Y Lamp test input
circuits, as well as the ability to drive 10 LS-TTL loads. The Y Low power consumption characteristics of CMOS
circuit provides the functions of a 4-bit storage latch, an devices
8421 BCD-to-seven segment decoder, and an output drive Y Wide operating voltage range: 2 to 6 volts
capability. Lamp test (LT), blanking (Bl), and latch enable Y Low input current: 1 mA maximum
(LE) inputs are used to test the display, to turn-off or pulse
modulate the brightness of the display, and to store a BCD
Y Low quiescent current: 80 mA maximum over full tem-
code, respectively. It can be used with seven-segment light perature range (74 Series)
emitting diodes (LED), incandescent, fluorescent, gas dis-
charge, or liquid crystal readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.)
display driver, computer/calculator display driver, cockpit
display driver, and various clock, watch, and timer uses.
The 54HC/74HC logic family is speed, function, and pinout
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to VCC and ground.

Connection Diagram Truth Table

Dual-In-Line Package
INPUTS OUTPUTS
LE BI LT D C B A a b c d e f g DISPLAY
x x L x x x x H H H H H H H 8
x L H x x x x L L L L L L L
L H H L L L L H H H H H H L 0
L H H L L L H L H H L L L L 1
L H H L L H L H H L H H L H 2
L H H L L H H H H H H L L H 3
L H H L H L L L H H L L H H 4
L H H L H L H H L H H L H H 5
L H H L H H L L L H H H H H 6
L H H L H H H H H H L L L L 7
L H H H L L L H H H H H H H 8
TL/F/5373 – 1 L H H H L L H H H H L L H H 9
L H H H L H L L L L L L L L
Order Number MM54HC4511 or MM74HC4511 L H H H L H H L L L L L L L
L H H H H L L L L L L L L L
L H H H H L H L L L L L L L
L H H H H H L L L L L L L L
L H H H H H H L L L L L L L
H H H x x x x * *
x e Don’t care
* e Depends upon the BCD code applied during the 0 to 1 transition of LE.

C1995 National Semiconductor Corporation TL/F/5373 RRD-B30M105/Printed in U. S. A.

 Absolute Maximum Ratings (Notes 1 and 2) Operating Conditions
If Military/Aerospace specified devices are required, Min Max Units
please contact the National Semiconductor Sales Supply Voltage (VCC) 2 6 V
Office/Distributors for availability and specifications. DC Input or Output Voltage 0 VCC V
Supply Voltage (VCC) b 0.5 to a 7.0V (VIN, VOUT)
DC Input Voltage (VIN) b 1.5 to VCC a 1.5V Operating Temp. Range (TA)
DC Output Voltage (VOUT) b 0.5 to VCC a 0.5V MM74HC b 40 a 85 §C
MM54HC b 55 a 125 §C
Clamp Diode Current (IIK, IOK) g 20 mA
Input Rise or Fall Times
DC Output Current, per pin (IOUT) g 25 mA
(tr, tf) VCC e 2.0V 1000 ns
DC VCC or GND Current, per pin (ICC) g 50 mA VCC e 4.5V 500 ns
Storage Temperature Range (TSTG) b 65§ C to a 150§ C VCC e 6.0V 400 ns
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temp. (TL) (Soldering 10 seconds) 260§ C

DC Electrical Characteristics (Note 4)

74HC 54HC
TA e 25§ C
Symbol Parameter Conditions VCC TA eb40 to 85§ C TA eb55 to 125§ C Units
Typ Guaranteed Limits
VIH Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
VOH Minimum High Level VIN e VIH or VIL
Output Voltage lIOUTl s20 mA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
VIN e VIH or VIL
lIOUTl s6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
lIOUTl s7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum Low Level VIN e VIH or VIL
Output Voltage lIOUTl s20 mA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
VIN e VIH or VIL
lIOUTl s4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
lIOUTl s5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
IIN Maximum Input VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA
Current
ICC Maximum Quiescent VIN e VCC or GND 6.0V 8.0 80 160 mA
Supply Current IOUT e 0 mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN,
ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.

2
 AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns
Guaranteed
Symbol Parameter Conditions Typ Units
Limit
tPHL, tPLH Maximum Propagation 60 120 ns
Delay from Inputs A thru D to any Output
tPHL, tPLH Maximum Propagation 60 120 ns
Delay from BI to any Output
tPHL, tPLH Maximum Propagation 60 120 ns
Delay from LT to any Output
tS Minimum Setup Time 10 20 ns
Inputs A thru D to LE
tH Minimum Hold Time b3 0 ns
Inputs A thru D to LE
tW Minimum Pulse Width 16 ns
for LE

AC Electrical Characteristics CL e 50 pF, tr e tf e 6 ns (unless otherwise specified)

74HC 54HC
TA e 25§ C
Symbol Parameter Conditions VCC TA eb40 to 85§ C TA eb55 to 125§ C Units
Typ Guaranteed Limits
tPHL, tPLH Maximum Propagation LE e 0V 2.0V 300 600 756 894 ns
Delay from Inputs LT e VCC 4.5V 60 120 151 179 ns
A thru D to any Output BI e VCC 6.0V 51 102 129 152 ns
tPHL, tPLH Maximum Propagation LT e VCC 2.0V 300 600 756 894 ns
Delay from BI to 4.5V 60 120 151 179 ns
any Output 6.0V 51 102 129 152 ns
tPHL, tPLH Maximum Propagation BI e 0V 2.0V 300 600 756 894 ns
Delay from LT to 4.5V 60 120 151 179 ns
any Output 6.0V 51 102 129 152 ns
tS Minimum Setup Time 2.0V 100 126 149 ns
Inputs A thru D to LE 4.5V 20 25 30 ns
6.0V 17 21 25 ns
tH Minimum Hold Time 2.0V 0 0 0 ns
Inputs A thru D to LE 4.5V 0 0 0 ns
6.0V 0 0 0 ns
tW Minimum Pulse Width 2.0V 80 100 120 ns
for LE 4.5V 16 20 24 ns
6.0V 14 17 20 ns
tr, tf Maximum Input Rise and 2.0V 1000 1000 1000 ns
Fall Time 4.5V 500 500 500 ns
6.0V 400 400 400 ns
CPD Power Dissipation pF
Capacitance (Note 5)
CIN Maximum Input 5 10 10 10 pF
Capacitance
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC.

3
INPUTS CONTROLS
A, B, C, D (Pins 7, 1, 2, 6)ÐBCD data inputs. A (pin 7) is the BI (Pin 4)ÐActive-low display blanking input. A logic low on
least-significant data bit and D (pin 6) is the most significant this input will cause all outputs to be held at a logic low,
bit. Hexadecimal data A–F at these inputs will cause the thereby blanking the display. LT is the only input that will
outputs to assume a logic low, offering an alternate method override the Bl input.
of blanking the display. LT (Pin 3)ÐActive-low lamp test. A low logic level on this
OUTPUTS input causes all outputs to assume a logic high. This input
allows the user to test all segments of a display, with a
a – gÐDecoded, buffered outputs. These outputs, unlike the
single control input. This input is independent of all other
4511, have CMOS drivers, which will produce typical CMOS
inputs.
output voltage levels.
LE (Pin 5)ÐLatch enable input. This input controls the 4-bit
transparent latch. A logic high on this input latches the data
present at the A, B, C and D inputs; a logic low allows the
data to be transmitted through the latch to the decoder.

Output Characteristics (VCC e 5V)

TL/F/5373 – 2 TL/F/5373 – 3
*The expected minimum curves are not guarantees, but are design aids.

Typical Applications

TL/F/5373 – 4 TL/F/5373 – 5
Typical Common Cathode LED Connection Incandescent Bulb Driving Circuit

4
Logic Diagram

TL/F/5373 – 6

Display

TL/F/5373 – 7

Segment Identification

TL/F/5373 – 8

5
MM54HC4511/MM74HC4511 BCD-to-7 Segment Latch/Decoder/Driver
Physical Dimensions inches (millimeters)

Dual-In-Line Package
Order Number MM54HC4511J or MM74HC4511J
NS Package J16A

Dual-In-Line Package
Order Number MM74HC4511N
NS Package N16E

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into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

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