Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                

74HC138

Download as pdf or txt
Download as pdf or txt
You are on page 1of 4

MM54HC138/MM74HC138 3-to-8 Line Decoder

January 1988

MM54HC138/MM74HC138
3-to-8 Line Decoder
General Description
This decoder utilizes advanced silicon-gate CMOS technol- The decoder’s outputs can drive 10 low power Schottky TTL
ogy, and is well suited to memory address decoding or data equivalent loads, and are functionally and pin equivalent to
routing applications. The circuit features high noise immuni- the 54LS138/74LS138. All inputs are protected from dam-
ty and low power consumption usually associated with age due to static discharge by diodes to VCC and ground.
CMOS circuitry, yet has speeds comparable to low power
Schottky TTL logic. Features
The MM54HC138/MM74HC138 has 3 binary select inputs Y Typical propagation delay: 20 ns
(A, B, and C). If the device is enabled these inputs deter- Y Wide power supply range: 2V – 6V
mine which one of the eight normally high outputs will go Y Low quiescent current: 80 mA maximum (74HC Series)
low. Two active low and one active high enables (G1, G2A Y Low input current: 1 mA maximum
and G2B) are provided to ease the cascading of decoders. Y Fanout of 10 LS-TTL loads

Connection and Logic Diagrams


Dual-In-Line Package

TL/F/5120–1

Order Number MM54HC138


or MM74HC138
TL/F/5120 – 2
Truth Table
Inputs
Outputs
Enable Select
G1 G2* C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H X X X H H H H H H H H
L X X X X H H H H H H H H
H L L L L L H H H H H H H
H L L L H H L H H H H H H
H L L H L H H L H H H H H
H L L H H H H H L H H H H
H L H L L H H H H L H H H
H L H L H H H H H H L H H
H L H H L H H H H H H L H
H L H H H H H H H H H H L
* G2 e G2A a G2B
H e high level, L e low level, X e don’t care

C1995 National Semiconductor Corporation TL/F/5120 RRD-B30M105/Printed in U. S. A.


Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions
If Military/Aerospace specified devices are required, Min Max Units
please contact the National Semiconductor Sales Supply Voltage (VCC) 2 6 V
Office/Distributors for availability and specifications. DC Input or Output Voltage 0 VCC V
Supply Voltage (VCC) b 0.5 to a 7.0V (VIN, VOUT)
DC Input Voltage (VIN) b 1.5 to VCC a 1.5V Operating Temp. Range (TA)
DC Output Voltage (VOUT) b 0.5 to VCC a 0.5V MM74HC b 40 a 85 §C
MM54HC b 55 a 125 §C
Clamp Diode Current (IIK, IOK) g 20 mA
Input Rise or Fall Times
DC Output Current, per pin (IOUT) g 25 mA
(tr, tf) VCC e 2.0V 1000 ns
DC VCC or GND Current, per pin (ICC) g 50 mA VCC e 4.5V 500 ns
Storage Temperature Range (TSTG) b 65§ C to a 150§ C VCC e 6.0V 400 ns
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temp. (TL) (Soldering 10 seconds) 260§ C

DC Electrical Characteristics (Note 4)


74HC 54HC
TA e 25§ C
Symbol Parameter Conditions VCC TA eb40 to 85§ C TA eb55 to 125§ C Units
Typ Guaranteed Limits
VIH Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
VOH Minimum High Level VIN e VIH or VIL
Output Voltage lIOUTl s20 mA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
VIN e VIH or VIL
lIOUTl s4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
lIOUTl s5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum Low Level VIN e VIH or VIL
Output Voltage lIOUTl s20 mA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
VIN e VIH or VIL
lIOUTl s4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
lIOUTl s5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
IIN Maximum Input VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA
Current
ICC Maximum Quiescent VIN e VCC or GND 6.0V 8.0 80 160 mA
Supply Current IOUT e 0 mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and
IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.

2
AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns
Guaranteed
Symbol Parameter Conditions Typ Units
Limit
tPLH Maximum Propagation 18 25 ns
Delay, Binary Select to any Output
tPHL Maximum Propagation 28 35 ns
Delay, Binary Select to any Output
tPHL, tPLH Maximum Propagation 18 25 ns
Delay, G1 to any Output
tPHL Maximum Propagation 23 30 ns
Delay G2A or G2B to
Output
tPLH Maximum Propagation 18 25 ns
Delay G2A or G2B to
Output

AC Electrical Characteristics CL e 50 pF, tr e tf e 6 ns (unless otherwise specified)


74HC 54HC
TA e 25§ C
Symbol Parameter Conditions VCC TA eb40 to 85§ C TA eb55 to 125§ C Units
Typ Guaranteed Limits
tPLH Maximum Propagation 2.0V 75 150 189 224 ns
Delay Binary Select to 4.5V 15 30 38 45 ns
any Output Low to High 6.0V 13 26 32 38 ns
tPHL Maximum Propagation 2.0V 100 200 252 298 ns
Delay Binary Select to any 4.5V 20 40 50 60 ns
Output High to Low 6.0V 17 34 43 51 ns
tPHL, tPLH Maximum Propagation 2.0V 75 150 189 224 ns
Delay G1 to any 4.5V 15 30 38 45 ns
Output 6.0V 13 26 32 38 ns
tPHL Maximum Propagation 2.0V 82 175 221 261 ns
Delay G2A or G2B to 4.5V 28 35 44 52 ns
Output 6.0V 22 30 37 44 ns
tPLH Maximum Propagation 2.0V 75 150 189 224 ns
Delay G2A or G2B to 4.5V 15 30 38 45 ns
Output 6.0V 13 26 32 38 ns
tTLH, tTHL Output Rise and 2.0V 30 75 95 110 ns
Fall Time 4.5V 8 15 19 22 ns
6.0V 7 13 16 19 ns
CIN Maximum Input 3 10 10 10 pF
Capacitance
CPD Power Dissipation (Note 5) 75 pF
Capacitance
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC.

3
MM54HC138/MM74HC138 3-to-8 Line Decoder
Physical Dimensions inches (millimeters)

Order Number MM54HC138J or MM74HC138J


NS Package Number J16A

Order Number MM74HC138N


NS Package Number N16E

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

National Semiconductor National Semiconductor National Semiconductor National Semiconductor


Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309
Arlington, TX 76017 Email: cnjwge @ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408
Tel: 1(800) 272-9959 Deutsch Tel: (a49) 0-180-530 85 85 Tsimshatsui, Kowloon
Fax: 1(800) 737-7018 English Tel: (a49) 0-180-532 78 32 Hong Kong
Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
Italiano Tel: (a49) 0-180-534 16 80 Fax: (852) 2736-9960

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

You might also like