mps430 Datasheet

MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526

MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
www.ti.com SLAS590L – MARCH 2009 – REVISED MAY 2013
MIXED SIGNAL MICROCONTROLLER

1FEATURES
2• Low Supply-Voltage Range: • 16-Bit Timer TA0, Timer_A With Five
3.6 V Down to 1.8 V Capture/Compare Registers
• Ultralow Power Consumption • 16-Bit Timer TA1, Timer_A With Three
– Active Mode (AM): Capture/Compare Registers
All System Clocks Active • 16-Bit Timer TA2, Timer_A With Three
290 µA/MHz at 8 MHz, 3.0 V, Flash Program Capture/Compare Registers
Execution (Typical) • 16-Bit Timer TB0, Timer_B With Seven
150 µA/MHz at 8 MHz, 3.0 V, RAM Program Capture/Compare Shadow Registers
Execution (Typical) • Two Universal Serial Communication
– Standby Mode (LPM3): Interfaces
Real-Time Clock With Crystal, Watchdog, – USCI_A0 and USCI_A1 Each Support:
and Supply Supervisor Operational, Full
RAM Retention, Fast Wake-Up: – Enhanced UART Supports Auto-
1.9 µA at 2.2 V, 2.1 µA at 3.0 V (Typical) Baudrate Detection
Low-Power Oscillator (VLO), General- – IrDA Encoder and Decoder
Purpose Counter, Watchdog, and Supply – Synchronous SPI
Supervisor Operational, Full RAM – USCI_B0 and USCI_B1 Each Support:
Retention, Fast Wake-Up: – I2CTM
1.4 µA at 3.0 V (Typical)
– Synchronous SPI
– Off Mode (LPM4):
Full RAM Retention, Supply Supervisor • Full-Speed Universal Serial Bus (USB)
Operational, Fast Wake-Up: – Integrated USB-PHY
1.1 µA at 3.0 V (Typical) – Integrated 3.3-V and 1.8-V USB Power
– Shutdown Mode (LPM4.5): System
0.18 µA at 3.0 V (Typical) – Integrated USB-PLL
• Wake-Up From Standby Mode in 3.5 µs – Eight Input, Eight Output Endpoints
(Typical) • 12-Bit Analog-to-Digital (A/D) Converter
• 16-Bit RISC Architecture, Extended Memory, (MSP430F552x Only) With Internal Reference,
up to 25-MHz System Clock Sample-and-Hold, and Autoscan Feature
• Flexible Power Management System • Comparator
– Fully Integrated LDO With Programmable • Hardware Multiplier Supporting 32-Bit
Regulated Core Supply Voltage Operations
– Supply Voltage Supervision, Monitoring, • Serial Onboard Programming, No External
and Brownout Programming Voltage Needed
• Unified Clock System • Three Channel Internal DMA
– FLL Control Loop for Frequency • Basic Timer With Real-Time Clock Feature
Stabilization • Family Members are Summarized in Table 1
– Low-Power Low-Frequency Internal Clock • For Complete Module Descriptions, See the
Source (VLO) MSP430x5xx and MSP430x6xx Family User's
– Low-Frequency Trimmed Internal Reference Guide (SLAU208)
Source (REFO)
– 32-kHz Watch Crystals (XT1)
– High-Frequency Crystals up to 32 MHz
1
(XT2)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 MSP430 is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SLAS590L – MARCH 2009 – REVISED MAY 2013 www.ti.com
DESCRIPTION
The Texas Instruments MSP430™ family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with extensive low-
power modes, is optimized to achieve extended battery life in portable measurement applications. The device
features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in 3.5
µs (typical).
The MSP430F5529, MSP430F5527, MSP430F5525, and MSP430F5521 are microcontroller configurations with
integrated USB and PHY supporting USB 2.0, four 16-bit timers, a high-performance 12-bit analog-to-digital
converter (ADC), two universal serial communication interfaces (USCI), hardware multiplier, DMA, real-time clock
module with alarm capabilities, and 63 I/O pins. The MSP430F5528, MSP430F5526, MSP430F5524, and
MSP430F5522 include all of these peripherals but have 47 I/O pins.
The MSP430F5519, MSP430F5517, and MSP430F5515 are microcontroller configurations with integrated USB
and PHY supporting USB 2.0, four 16-bit timers, two universal serial communication interfaces (USCI), hardware
multiplier, DMA, real time clock module with alarm capabilities, and 63 I/O pins. The MSP430F5514 and
MSP430FF5513 include all of these peripherals but have 47 I/O pins.
Typical applications include analog and digital sensor systems, data loggers, and others that require connectivity
to various USB hosts.
Family members available are summarized in Table 1.
Table 1. Family Members

USCI
Flash SRAM (2) (3) Channel A: Channel B: ADC12_A Comp_B Package
Device Timer_A Timer_B I/O
(KB) (KB) (1) UART, SPI, I2C (Ch) (Ch) Type
IrDA, SPI
MSP430F5529 128 8+2 5, 3, 3 7 2 2 14 ext, 2 int 12 63 80 PN
64 RGC,
MSP430F5528 128 8+2 5, 3, 3 7 2 2 10 ext, 2 int 8 47 64 YFF,
80 ZQE
MSP430F5527 96 6+2 5, 3, 3 7 2 2 14 ext, 2 int 12 63 80 PN
64 RGC,
MSP430F5526 96 6+2 5, 3, 3 7 2 2 10 ext, 2 int 8 47 64 YFF,
80 ZQE
MSP430F5525 64 4+2 5, 3, 3 7 2 2 14 ext, 2 int 12 63 80 PN
64 RGC,
MSP430F5524 64 4+2 5, 3, 3 7 2 2 10 ext, 2 int 8 47 64 YFF,
80 ZQE
64 RGC,
MSP430F5522 32 8+2 5, 3, 3 7 2 2 10 ext, 2 int 8 47
80 ZQE
MSP430F5521 32 6+2 5, 3, 3 7 2 2 14 ext, 2 int 12 63 80 PN
MSP430F5519 128 8+2 5, 3, 3 7 2 2 - 12 63 80 PN
MSP430F5517 96 6+2 5, 3, 3 7 2 2 - 12 63 80 PN
MSP430F5515 64 4+2 5, 3, 3 7 2 2 - 12 63 80 PN
64 RGC,
MSP430F5514 64 4+2 5, 3, 3 7 2 2 - 8 47
80 ZQE
64 RGC,
MSP430F5513 32 4+2 5, 3, 3 7 2 2 - 8 47
80 ZQE
(1) The additional 2 KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use.
(2) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(3) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
2 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524

MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513
Table 2. Ordering Information (1)

PACKAGED DEVICES (2)
TA PLASTIC 80-PIN LQFP PLASTIC 64-PIN VQFN PLASTIC 64-BALL DSBGA PLASTIC 80-BALL BGA
(PN) (RGC) (YFF) (ZQE)
MSP430F5529IPN MSP430F5528IRGC MSP430F5528IYFF MSP430F5528IZQE
–40°C to 85°C MSP430F5521IPN MSP430F5522IRGC MSP430F5522IZQE
MSP430F5519IPN MSP430F5514IRGC MSP430F5514IZQE
MSP430F5517IPN MSP430F5513IRGC MSP430F5513IZQE
MSP430F5515IPN
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 3

Functional Block Diagram – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN,

MSP430F5521IPN
XIN XOUT RST/NMI DVCC DVSS VCORE AVCC AVSS PA PB PC PD
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x DP,DM,PUR
XT2IN SYS
Unified ACLK Power I/O Ports I/O Ports I/O Ports I/O Ports
Management P1/P2 P3/P4 P5/P6 P7/P8 Full-speed
Clock 128KB 8KB+2KB Watchdog
XT2OUT 2×8 I/Os 2×8 I/Os 2×8 I/Os 1×8 I/Os USB
System SMCLK 96KB 6KB+2KB
Port Map Interrupt 1×3 I/Os
64KB 4KB+2KB LDO & Wakeup USB-PHY
32KB Control USB-LDO
SVM/SVS (P4)
MCLK USB-PLL
Brownout PA PB PC PD
Flash RAM 1×16 I/Os 1×16 I/Os 1×16 I/Os 1×11 I/Os
MAB
CPUXV2 DMA
and
Working MDB 3 Channel
Registers
EEM
(L: 8+2)
USCI0,1 ADC12_A
JTAG/ TA0 TA1 TA2 TB0 USCI_Ax: 12 Bit

UART, 200 KSPS REF COMP_B
SBW MPY32 RTC_A CRC16
Interface Timer_A Timer_A Timer_A Timer_B IrDA, SPI
5 CC 3 CC 3 CC 7 CC 16 Channels 12 Channels
Registers Registers Registers Registers USCI_Bx: (14 ext/2 int)
SPI, I2C Autoscan

Pin Designation – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN, MSP430F5521IPN

PN PACKAGE
(TOP VIEW)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.1/TDI/TCLK
P5.3/XT2OUT
P6.3/CB3/A3
P6.2/CB2/A2
P6.1/CB1/A1
P6.0/CB0/A0
P5.2/XT2IN
PJ.2/TMS
PJ.0/TDO
PJ.3/TCK
PU.1/DM
PU.0/DP
AVSS2
VSSU
VUSB
VBUS
PUR
V18
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P6.4/CB4/A4 1 60 P7.7/TB0CLK/MCLK
P6.5/CB5/A5 2 59 P7.6/TB0.4
P6.6/CB6/A6 3 58 P7.5/TB0.3
P6.7/CB7/A7 4 57 P7.4/TB0.2
P7.0/CB8/A12 5 56 P5.7/TB0.1
P7.1/CB9/A13 6 55 P5.6/TB0.0
P7.2/CB10/A14 7 54 P4.7/PM_NONE
P7.3/CB11/A15 8 53 P4.6/PM_NONE
P5.0/A8/VREF+/VeREF+ 9 52 P4.5/PM_UCA1RXD/PM_UCA1SOMI
MSP430F5529IPN
P5.1/A9/VREF−/VeREF− 10 MSP430F5527IPN 51 P4.4/PM_UCA1TXD/PM_UCA1SIMO
AVCC1 11 MSP430F5525IPN 50 DVCC2
P5.4/XIN 12 MSP430F5521IPN 49 DVSS2
P5.5/XOUT 13 48 P4.3/PM_UCB1CLK/PM_UCA1STE
AVSS1 14 47 P4.2/PM_UCB1SOMI/PM_UCB1SCL
P8.0 15 46 P4.1/PM_UCB1SIMO/PM_UCB1SDA
P8.1 16 45 P4.0/PM_UCB1STE/PM_UCA1CLK
P8.2 17 44 P3.7/TB0OUTH/SVMOUT
DVCC1 18 43 P3.6/TB0.6
DVSS1 19 42 P3.5/TB0.5
VCORE 20 41 P3.4/UCA0RXD/UCA0SOMI
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P1.2/TA0.1
P2.1/TA1.2
P1.3/TA0.2
P1.6/TA1CLK/CBOUT
P1.1/TA0.0
P1.7/TA1.0
P1.4/TA0.3
P1.5/TA0.4
P2.0/TA1.1
P2.3/TA2.0
P2.5/TA2.2
P3.2/UCB0CLK/UCA0STE
P2.2/TA2CLK/SMCLK
P2.6/RTCCLK/DMAE0
P3.3/UCA0TXD/UCA0SIMO
P3.1/UCB0SOMI/UCB0SCL
P1.0/TA0CLK/ACLK
P2.4/TA2.1
P2.7/UCB0STE/UCA0CLK
P3.0/UCB0SIMO/UCB0SDA

Functional Block Diagram –

MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC, MSP430F5522IRGC
MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE, MSP430F5522IZQE
MSP430F5528IYFF, MSP430F5526IYFF, MSP430F5524IYFF
XIN XOUT RST/NMI DVCC DVSS VCORE AVCC AVSS PA PB PC
P1.x P2.x P3.x P4.x P5.x P6.x DP,DM,PUR
XT2IN SYS
Unified ACLK Power I/O Ports I/O Ports I/O Ports
Management P1/P2 P3/P4 P5/P6 Full-speed
XT2OUT 2×8 I/Os 1×5 I/Os 1×6 I/Os USB
System SMCLK 96KB 6KB+2KB
Port Map Interrupt 1×8 I/Os 1×8 I/Os
64KB 4KB+2KB LDO & Wakeup USB-PHY
32KB Control USB-LDO
SVM/SVS (P4)
MCLK USB-PLL
Brownout PA PB PC
Flash RAM 1×16 I/Os 1×13 I/Os 1×14 I/Os
MAB
CPUXV2 DMA
and
Registers
EEM
(L: 8+2)
USCI0,1 ADC12_A
JTAG/ TA0 TA1 TA2 TB0 USCI_Ax: 12 Bit

UART, 200 KSPS REF COMP_B
SBW MPY32 RTC_A CRC16
5 CC 3 CC 3 CC 7 CC 12 Channels 8 Channels
Registers Registers Registers Registers USCI_Bx: (10 ext/2 int)
SPI, I2C Autoscan

Pin Designation – MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC,

MSP430F5522IRGC
RGC PACKAGE
(TOP VIEW)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.1/TDI/TCLK
P5.3/XT2OUT
P5.2/XT2IN
PJ.2/TMS
PJ.0/TDO
PJ.3/TCK
PU.1/DM
PU.0/DP
AVSS2
VSSU
VUSB
VBUS
PUR
V18
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P6.0/CB0/A0 1 48 P4.7/PM_NONE
P6.1/CB1/A1 2 47 P4.6/PM_NONE
P6.2/CB2/A2 3 46 P4.5/PM_UCA1RXD/PM_UCA1SOMI
P6.3/CB3/A3 4 45 P4.4/PM_UCA1TXD/PM_UCA1SIMO
P6.4/CB4/A4 5 44 P4.3/PM_UCB1CLK/PM_UCA1STE
P6.5/CB5/A5 6 43 P4.2/PM_UCB1SOMI/PM_UCB1SCL
P6.6/CB6/A6 7 42 P4.1/PM_UCB1SIMO/PM_UCB1SDA
MSP430F5528IRGC
P6.7/CB7/A7 8 MSP430F5526IRGC 41 P4.0/PM_UCB1STE/PM_UCA1CLK
P5.0/A8/VREF+/VeREF+ 9 MSP430F5524IRGC 40 DVCC2
P5.1/A9/VREF−/VeREF− 10 MSP430F5522IRGC 39 DVSS2
AVCC1 11 38 P3.4/UCA0RXD/UCA0SOMI
P5.4/XIN 12 37 P3.3/UCA0TXD/UCA0SIMO
P5.5/XOUT 13 36 P3.2/UCB0CLK/UCA0STE
AVSS1 14 35 P3.1/UCB0SOMI/UCB0SCL
DVCC1 15 34 P3.0/UCB0SIMO/UCB0SDA
DVSS1 16 33 P2.7/UCB0STE/UCA0CLK
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P1.2/TA0.1
P2.4/TA2.1
P1.3/TA0.2
P1.1/TA0.0
P1.4/TA0.3
VCORE
P1.0/TA0CLK/ACLK
P1.5/TA0.4
P2.5/TA2.2
P2.1/TA1.2
P1.7/TA1.0
P1.6/TA1CLK/CBOUT
P2.3/TA2.0
P2.6/RTCCLK/DMAE0
P2.0/TA1.1
P2.2/TA2CLK/SMCLK
Note: Power Pad connection

to VSS recommended.

Functional Block Diagram – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN

XIN XOUT RST/NMI DVCC DVSS VCORE AVCC AVSS PA PB PC PD
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x DP,DM,PUR
XT2IN SYS
Unified ACLK Power I/O Ports I/O Ports I/O Ports I/O Ports
Management P1/P2 P3/P4 P5/P6 P7/P8 Full-speed
XT2OUT 2×8 I/Os 2×8 I/Os 2×8 I/Os 1×8 I/Os USB
System SMCLK 96KB
Port Map Interrupt 1×3 I/Os
64KB LDO & Wakeup USB-PHY
Control USB-LDO
SVM/SVS (P4)
MCLK Flash RAM USB-PLL
Brownout PA PB PC PD
1×16 I/Os 1×16 I/Os 1×16 I/Os 1×11 I/Os
MAB
CPUXV2 DMA
and
Registers
EEM
(L: 8+2)
USCI0,1
JTAG/ TA0 TA1 TA2 TB0 USCI_Ax:

UART, COMP_B
SBW MPY32 RTC_A CRC16 REF
5 CC 3 CC 3 CC 7 CC 12 Channels
Registers Registers Registers Registers USCI_Bx:
SPI, I2C

Pin Designation – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN

PN PACKAGE
(TOP VIEW)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.1/TDI/TCLK
P5.3/XT2OUT
P5.2/XT2IN
PJ.2/TMS
PJ.0/TDO
P6.3/CB3
P6.2/CB2
P6.1/CB1
PJ.3/TCK
P6.0/CB0
PU.1/DM
PU.0/DP
AVSS2
VSSU
VUSB
VBUS
PUR
V18
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P6.4/CB4 1 60 P7.7/TB0CLK/MCLK
P6.5/CB5 2 59 P7.6/TB0.4
P6.6/CB6 3 58 P7.5/TB0.3
P6.7/CB7 4 57 P7.4/TB0.2
P7.0/CB8 5 56 P5.7/TB0.1
P7.1/CB9 6 55 P5.6/TB0.0
P7.2/CB10 7 54 P4.7/PM_NONE
P7.3/CB11 8 53 P4.6/PM_NONE
P5.0 9 52 P4.5/PM_UCA1RXD/PM_UCA1SOMI
P5.1 10 MSP430F5519IPN 51 P4.4/PM_UCA1TXD/PM_UCA1SIMO
AVCC1 11 MSP430F5517IPN 50 DVCC2
MSP430F5515IPN
P5.4/XIN 12 49 DVSS2
P5.5/XOUT 13 48 P4.3/PM_UCB1CLK/PM_UCA1STE
AVSS1 14 47 P4.2/PM_UCB1SOMI/PM_UCB1SCL
P8.0 15 46 P4.1/PM_UCB1SIMO/PM_UCB1SDA
P8.1 16 45 P4.0/PM_UCB1STE/PM_UCA1CLK
P8.2 17 44 P3.7/TB0OUTH/SVMOUT
DVCC1 18 43 P3.6/TB0.6
DVSS1 19 42 P3.5/TB0.5
VCORE 20 41 P3.4/UCA0RXD/UCA0SOMI
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P1.2/TA0.1
P2.1/TA1.2
P1.3/TA0.2
P1.6/TA1CLK/CBOUT
P1.1/TA0.0
P1.7/TA1.0
P1.4/TA0.3
P1.5/TA0.4
P2.0/TA1.1
P2.3/TA2.0
P2.5/TA2.2
P2.2/TA2CLK/SMCLK
P2.6/RTCCLK/DMAE0
P3.1/UCB0SOMI/UCB0SCL
P1.0/TA0CLK/ACLK
P2.4/TA2.1
P2.7/UCB0STE/UCA0CLK

Functional Block Diagram – MSP430F5514IRGC, MSP430F5513IRGC, MSP430F5514IZQE,

MSP430F5513IZQE
XIN XOUT RST/NMI DVCC DVSS VCORE AVCC AVSS PA PB PC
P1.x P2.x P3.x P4.x P5.x P6.x DP,DM,PUR
XT2IN SYS
Unified ACLK Power I/O Ports I/O Ports I/O Ports
Management P1/P2 P3/P4 P5/P6 Full-speed
XT2OUT 2×8 I/Os 1×5 I/Os 1×6 I/Os USB
System SMCLK 32KB
Port Map Interrupt 1×8 I/Os 1×8 I/Os
LDO & Wakeup USB-PHY
Control USB-LDO
SVM/SVS (P4)
MCLK Flash RAM USB-PLL
Brownout PA PB PC
1×16 I/Os 1×13 I/Os 1×14 I/Os
MAB
CPUXV2 DMA
and
Registers
EEM
(L: 8+2)
USCI0,1
JTAG/ TA0 TA1 TA2 TB0 USCI_Ax:

UART, COMP_B
SBW MPY32 RTC_A CRC16 REF
5 CC 3 CC 3 CC 7 CC 8 Channels
Registers Registers Registers Registers USCI_Bx:
SPI, I2C

Pin Designation – MSP430F5514IRGC, MSP430F5513IRGC

RGC PACKAGE
(TOP VIEW)
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.1/TDI/TCLK
P5.3/XT2OUT
P5.2/XT2IN
PJ.2/TMS
PJ.0/TDO
PJ.3/TCK
PU.1/DM
PU.0/DP
AVSS2
VSSU
VUSB
VBUS
PUR
V18
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P6.0/CB0 1 48 P4.7/PM_NONE
P6.1/CB1 2 47 P4.6/PM_NONE
P6.2/CB2 3 46 P4.5/PM_UCA1RXD/PM_UCA1SOMI
P6.3/CB3 4 45 P4.4/PM_UCA1TXD/PM_UCA1SIMO
P6.4/CB4 5 44 P4.3/PM_UCB1CLK/PM_UCA1STE
P6.5/CB5 6 43 P4.2/PM_UCB1SOMI/PM_UCB1SCL
P6.6/CB6 7 42 P4.1/PM_UCB1SIMO/PM_UCB1SDA
P6.7/CB7 8 MSP430F5514IRGC 41 P4.0/PM_UCB1STE/PM_UCA1CLK
P5.0 9 MSP430F5513IRGC 40 DVCC2
P5.1 10 39 DVSS2
AVCC1 11 38 P3.4/UCA0RXD/UCA0SOMI
P5.4/XIN 12 37 P3.3/UCA0TXD/UCA0SIMO
P5.5/XOUT 13 36 P3.2/UCB0CLK/UCA0STE
AVSS1 14 35 P3.1/UCB0SOMI/UCB0SCL
DVCC1 15 34 P3.0/UCB0SIMO/UCB0SDA
DVSS1 16 33 P2.7/UCB0STE/UCA0CLK
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P1.2/TA0.1
P2.4/TA2.1
P1.3/TA0.2
P1.1/TA0.0
P1.4/TA0.3
VCORE
P1.0/TA0CLK/ACLK
P1.5/TA0.4
P2.5/TA2.2
P2.1/TA1.2
P1.7/TA1.0
P1.6/TA1CLK/CBOUT
P2.3/TA2.0
P2.6/RTCCLK/DMAE0
P2.0/TA1.1
P2.2/TA2CLK/SMCLK
Note: Power Pad connection

to VSS recommended.

Pin Designation – MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE,

MSP430F5522IZQE, MSP430F5514IZQE, MSP430F5513IZQE
ZQE PACKAGE
(TOP VIEW)
P6.0 RST/NMI PJ.2 TEST AVSS2 VUSB VBUS PU.1 PU.0

A1 A2 A3 A4 A5 A6 A7 A8 A9
P6.2 P6.1 PJ.3 P5.3 P5.2 V18 PUR VSSU VSSU

B1 B2 B3 B4 B5 B6 B7 B8 B9
P6.4 P6.3 PJ.1 PJ.0 Rsvd P4.7 P4.6 P4.5

C1 C2 C4 C5 C6 C7 C8 C9
P6.6 P6.5 P6.7 Rsvd Rsvd Rsvd P4.4 P4.3 P4.2

D1 D2 D3 D4 D5 D6 D7 D8 D9
P5.0 P5.1 Rsvd Rsvd Rsvd Rsvd P4.1 P4.0 DVCC2

E1 E2 E3 E4 E5 E6 E7 E8 E9
P5.4 AVCC1 Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd DVSS2

F1 F2 F3 F4 F5 F6 F7 F8 F9
P5.5 AVSS1 Rsvd P1.3 P1.6 P2.1 P3.4 P3.2 P3.3

G1 G2 G3 G4 G5 G6 G7 G8 G9
DVCC1 P1.0 P1.1 P1.4 P1.7 P2.3 P2.7 P3.0 P3.1

H1 H2 H3 H4 H5 H6 H7 H8 H9
DVSS1 VCORE P1.2 P1.5 P2.0 P2.2 P2.4 P2.5 P2.6

J1 J2 J3 J4 J5 J6 J7 J8 J9

Pin Designation – MSP430F5528IYFF, MSP430F5526IYFF, MSP430F5524IYFF

YFF PACKAGE YFF PACKAGE
(TOP VIEW) (BALL-SIDE VIEW)
H8 H7 H6 H5 H4 H3 H2 H1 H1 H2 H3 H4 H5 H6 H7 H8
P2.7 P3.1 DVSS2 DVCC2 P4.1 P4.4 VSSU PU.0 PU.0 VSSU P4.4 P4.1 DVCC2 DVSS2 P3.1 P2.7
G8 G7 G6 G5 G4 G3 G2 G1 G1 G2 G3 G4 G5 G6 G7 G8
P3.0 P3.2 P3.3 P3.4 P4.2 P4.5 PUR PU.1 PU.1 PUR P4.5 P4.2 P3.4 P3.3 P3.2 P3.0
F8 F7 F6 F5 F4 F3 F2 F1 F1 F2 F3 F4 F5 F6 F7 F8
P2.4 P2.5 P2.6 P4.0 P4.3 P4.6 VBUS VUSB VUSB VBUS P4.6 P4.3 P4.0 P2.6 P2.5 P2.4
E8 E7 E6 E5 E4 E3 E2 E1 E1 E2 E3 E4 E5 E6 E7 E8
D P2.1 P2.2 P2.3 P2.0 P4.7 TEST V18 P5.2 D P5.2 V18 TEST P4.7 P2.0 P2.3 P2.2 P2.1
D8 D7 D6 D5 D4 D3 D2 D1 D1 D2 D3 D4 D5 D6 D7 D8
P1.7 P1.6 P1.5 RST/NMI PJ.1 PJ.0 AVSS2 P5.3 P5.3 AVSS2 PJ.0 PJ.1 RST/NMI P1.5 P1.6 P1.7
C8 C7 C6 C5 C4 C3 C2 C1 C1 C2 C3 C4 C5 C6 C7 C8
P1.3 P1.4 P1.2 P6.7 P6.3 P6.1 PJ.3 PJ.2 PJ.2 PJ.3 P6.1 P6.3 P6.7 P1.2 P1.4 P1.3
B8 B7 B6 B5 B4 B3 B2 B1 B1 B2 B3 B4 B5 B6 B7 B8
VCORE P1.0 P1.1 P5.1 P5.0 P6.5 P6.4 P6.0 P6.0 P6.4 P6.5 P5.0 P5.1 P1.1 P1.0 VCORE
A8 A7 A6 A5 A4 A3 A2 A1 A1 A2 A3 A4 A5 A6 A7 A8
DVSS1 DVCC1 P5.5 P5.4 AVSS1 AVCC1 P6.6 P6.2 P6.2 P6.6 AVCC1 AVSS1 P5.4 P5.5 DVCC1 DVSS1
E E

Table 3. Terminal Functions

TERMINAL
NO. I/O (1) DESCRIPTION
NAME
PN RGC YFF ZQE
General-purpose digital I/O

P6.4/CB4/A4 1 5 B2 C1 I/O Comparator_B input CB4
Analog input A4 – ADC (not available on F551x devices)

P6.5/CB5/A5 2 6 B3 D2 I/O Comparator_B input CB5

P6.6/CB6/A6 3 7 A2 D1 I/O Comparator_B input CB6

P6.7/CB7/A7 4 8 C5 D3 I/O Comparator_B input CB7
General-purpose digital I/O (not available on F5528, F5526, F5524,

F5522, F5514, F5513 devices)
P7.0/CB8/A12 5 N/A N/A N/A I/O Comparator_B input CB8 (not available on F5528, F5526, F5524, F5522,
F5514, F5513 devices)

F5522, F5514, F5513 devices)

F5522, F5514, F5513 devices)

F5522, F5514, F5513 devices)

Output of reference voltage to the ADC (not available on F551x devices)
P5.0/A8/VREF+/VeREF+ 9 9 B4 E1 I/O Input for an external reference voltage to the ADC (not available on F551x
devices)

Negative terminal for the ADC reference voltage for both sources, the
P5.1/A9/VREF-/VeREF- 10 10 B5 E2 I/O internal reference voltage, or an external applied reference voltage (not
available on F551x devices)
AVCC1 11 11 A3 F2 Analog power supply

P5.4/XIN 12 12 A5 F1 I/O
Input terminal for crystal oscillator XT1

P5.5/XOUT 13 13 A6 G1 I/O
Output terminal of crystal oscillator XT1
(1) I = input, O = output, N/A = not available


Table 3. Terminal Functions (continued)

TERMINAL
NAME
PN RGC YFF ZQE
AVSS1 14 14 A4 G2 Analog ground supply
P8.0 15 N/A N/A N/A I/O General-purpose digital I/O
DVCC1 18 15 A7 H1 Digital power supply
DVSS1 19 16 A8 J1 Digital ground supply
VCORE (2) 20 17 B8 J2 Regulated core power supply output (internal use only, no external current loading)
General-purpose digital I/O with port interrupt

P1.0/TA0CLK/ACLK 21 18 B7 H2 I/O TA0 clock signal TA0CLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)

P1.1/TA0.0 22 19 B6 H3 I/O TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output

P1.2/TA0.1 23 20 C6 J3 I/O TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input

P1.3/TA0.2 24 21 C8 G4 I/O
TA0 CCR2 capture: CCI2A input, compare: Out2 output

P1.4/TA0.3 25 22 C7 H4 I/O
TA0 CCR3 capture: CCI3A input compare: Out3 output

P1.5/TA0.4 26 23 D6 J4 I/O

P1.6/TA1CLK/CBOUT 27 24 D7 G5 I/O TA1 clock signal TA1CLK input
Comparator_B output

P1.7/TA1.0 28 25 D8 H5 I/O

P2.0/TA1.1 29 26 E5 J5 I/O

P2.1/TA1.2 30 27 E8 G6 I/O

P2.2/TA2CLK/SMCLK 31 28 E7 J6 I/O TA2 clock signal TA2CLK input
SMCLK output

P2.3/TA2.0 32 29 E6 H6 I/O

P2.4/TA2.1 33 30 F8 J7 I/O

P2.5/TA2.2 34 31 F7 J8 I/O

P2.6/RTCCLK/DMAE0 35 32 F6 J9 I/O RTC clock output for calibration
DMA external trigger input
(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, CVCORE.

TERMINAL
NAME
PN RGC YFF ZQE

Slave transmit enable – USCI_B0 SPI mode
P2.7/UCB0STE/UCA0CLK 36 33 H8 H7 I/O
Clock signal input – USCI_A0 SPI slave mode
Clock signal output – USCI_A0 SPI master mode

P3.0/UCB0SIMO/UCB0SDA 37 34 G8 H8 I/O Slave in, master out – USCI_B0 SPI mode
I2C data – USCI_B0 I2C mode

P3.1/UCB0SOMI/UCB0SCL 38 35 H7 H9 I/O Slave out, master in – USCI_B0 SPI mode
I2C clock – USCI_B0 I2C mode

Clock signal input – USCI_B0 SPI slave mode
P3.2/UCB0CLK/UCA0STE 39 36 G7 G8 I/O
Clock signal output – USCI_B0 SPI master mode
Slave transmit enable – USCI_A0 SPI mode

P3.3/UCA0TXD/UCA0SIMO 40 37 G6 G9 I/O Transmit data – USCI_A0 UART mode
Slave in, master out – USCI_A0 SPI mode

P3.4/UCA0RXD/UCA0SOMI 41 38 G5 G7 I/O Receive data – USCI_A0 UART mode
Slave out, master in – USCI_A0 SPI mode

P3.5/TB0.5 42 N/A N/A N/A I/O F5522, F5514, F5513 devices)
TB0 CCR5 capture: CCI5A input, compare: Out5 output

P3.6/TB0.6 43 N/A N/A N/A I/O F5522, F5514, F5513 devices)
TB0 CCR6 capture: CCI6A input, compare: Out6 output

F5522, F5514, F5513 devices)
P3.7/TB0OUTH/SVMOUT 44 N/A N/A N/A I/O Switch all PWM outputs high impedance input – TB0 (not available on
F5528, F5526, F5524, F5522, F5514, F5513 devices)
SVM output (not available on F5528, F5526, F5524, F5522, F5514, F5513
devices)
General-purpose digital I/O with reconfigurable port mapping secondary

function
P4.0/PM_UCB1STE/
PM_UCA1CLK
45 41 F5 E8 I/O Default mapping: Slave transmit enable – USCI_B1 SPI mode
Default mapping: Clock signal input – USCI_A1 SPI slave mode
Default mapping: Clock signal output – USCI_A1 SPI master mode

P4.1/PM_UCB1SIMO/ function
46 42 H4 E7 I/O
PM_UCB1SDA Default mapping: Slave in, master out – USCI_B1 SPI mode
Default mapping: I2C data – USCI_B1 I2C mode

P4.2/PM_UCB1SOMI/ function
47 43 G4 D9 I/O
PM_UCB1SCL Default mapping: Slave out, master in – USCI_B1 SPI mode
Default mapping: I2C clock – USCI_B1 I2C mode


TERMINAL
NAME
PN RGC YFF ZQE

function
P4.3/PM_UCB1CLK/
PM_UCA1STE
48 44 F4 D8 I/O Default mapping: Clock signal input – USCI_B1 SPI slave mode
Default mapping: Clock signal output – USCI_B1 SPI master mode
Default mapping: Slave transmit enable – USCI_A1 SPI mode
DVSS2 49 39 H6 F9 Digital ground supply
DVCC2 50 40 H5 E9 Digital power supply

P4.4/PM_UCA1TXD/ function
51 45 H3 D7 I/O
PM_UCA1SIMO Default mapping: Transmit data – USCI_A1 UART mode
Default mapping: Slave in, master out – USCI_A1 SPI mode

P4.5/PM_UCA1RXD/ function
52 46 G3 C9 I/O
PM_UCA1SOMI Default mapping: Receive data – USCI_A1 UART mode
Default mapping: Slave out, master in – USCI_A1 SPI mode

P4.6/PM_NONE 53 47 F3 C8 I/O function
Default mapping: no secondary function.

P4.7/PM_NONE 54 48 E4 C7 I/O function
Default mapping: no secondary function.

F5522, F5514, F5513 devices)
P5.6/TB0.0 55 N/A N/A N/A I/O
TB0 CCR0 capture: CCI0A input, compare: Out0 output (not available on
F5528, F5526, F5524, F5522, F5514, F5513 devices)

F5522, F5514, F5513 devices)
P5.7/TB0.1 56 N/A N/A N/A I/O
F5528, F5526, F5524, F5522, F5514, F5513 devices)

F5522, F5514, F5513 devices)
P7.4/TB0.2 57 N/A N/A N/A I/O
F5528, F5526, F5524, F5522, F5514, F5513 devices)

F5522, F5514, F5513 devices)
P7.5/TB0.3 58 N/A N/A N/A I/O
F5528, F5526, F5524, F5522, F5514, F5513 devices)

F5522, F5514, F5513 devices)
P7.6/TB0.4 59 N/A N/A N/A I/O
F5528, F5526, F5524, F5522, F5514, F5513 devices)

F5522, F5514, F5513 devices)
P7.7/TB0CLK/MCLK 60 N/A N/A N/A I/O TB0 clock signal TBCLK input (not available on F5528, F5526, F5524,
F5522, F5514, F5513 devices)
MCLK output (not available on F5528, F5526, F5524, F5522, F5514,
F5513 devices)
B8,
VSSU 61 49 H2 USB PHY ground supply
B9
General-purpose digital I/O - controlled by USB control register

PU.0/DP 62 50 H1 A9 I/O
USB data terminal DP


TERMINAL
NAME
PN RGC YFF ZQE
USB pullup resistor pin (open drain). The voltage level at the PUR pin is used to
PUR 63 51 G2 B7 I/O invoke the default USB BSL. Recommended 1-MΩ resistor to ground. See USB BSL
for more information.
General-purpose digital I/O - controlled by USB control register

PU.1/DM 64 52 G1 A8 I/O
USB data terminal DM
VBUS 65 53 F2 A7 USB LDO input (connect to USB power source)
VUSB 66 54 F1 A6 USB LDO output
V18 67 55 E2 B6 USB regulated power (internal use only, no external current loading)
AVSS2 68 56 D2 A5 Analog ground supply

P5.2/XT2IN 69 57 E1 B5 I/O
Input terminal for crystal oscillator XT2

P5.3/XT2OUT 70 58 D1 B4 I/O
Output terminal of crystal oscillator XT2
Test mode pin – Selects four wire JTAG operation.

TEST/SBWTCK (3) 71 59 E3 A4 I
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated

PJ.0/TDO (4) 72 60 D3 C5 I/O
JTAG test data output port

PJ.1/TDI/TCLK (4) 73 61 D4 C4 I/O
JTAG test data input or test clock input

PJ.2/TMS (4) 74 62 C1 A3 I/O
JTAG test mode select

PJ.3/TCK (4) 75 63 C2 B3 I/O
JTAG test clock
Reset input active low (6)

RST/NMI/SBWTDIO (5) 76 64 D5 A2 I/O Non-maskable interrupt input
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated

P6.0/CB0/A0 77 1 B1 A1 I/O Comparator_B input CB0

P6.1/CB1/A1 78 2 C3 B2 I/O Comparator_B input CB1

P6.2/CB2/A2 79 3 A1 B1 I/O Comparator_B input CB2

P6.3/CB3/A3 80 4 C4 C2 I/O Comparator_B input CB3
(7)
Reserved N/A N/A N/A
QFN Pad N/A Pad N/A N/A QFN package pad connection to VSS recommended.
(3) See Bootstrap Loader (BSL) and JTAG Operation for use with BSL and JTAG functions.
(4) See JTAG Operation for use with JTAG function.
(5) See Bootstrap Loader (BSL) and JTAG Operation for use with BSL and JTAG functions.
(6) When this pin is configured as reset, the internal pullup resistor is enabled by default.
(7) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.

SHORT-FORM DESCRIPTION
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All Program Counter PC/R0
operations, other than program-flow instructions, are
performed as register operations in conjunction with Stack Pointer SP/R1
seven addressing modes for source operand and four Status Register SR/CG1/R2
addressing modes for destination operand.
The CPU is integrated with 16 registers that provide Constant Generator CG2/R3
reduced instruction execution time. The register-to- General-Purpose Register R4
register operation execution time is one cycle of the
CPU clock. General-Purpose Register R5
Four of the registers, R0 to R3, are dedicated as General-Purpose Register R6
program counter, stack pointer, status register, and
constant generator, respectively. The remaining General-Purpose Register R7
registers are general-purpose registers.
General-Purpose Register R8
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled with General-Purpose Register R9
all instructions.
The instruction set consists of the original 51
instructions with three formats and seven address General-Purpose Register R11
modes and additional instructions for the expanded
address range. Each instruction can operate on word General-Purpose Register R12
and byte data. General-Purpose Register R13

Operating Modes
The MSP430 has one active mode and six software selectable low-power modes of operation. An interrupt event
can wake up the device from any of the low-power modes, service the request, and restore back to the low-
power mode on return from the interrupt program.
The following seven operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– CPU is disabled
– MCLK and FLL loop control and DCOCLK are disabled
– DCO's dc-generator remains enabled
– ACLK remains active
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– ACLK remains active
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc generator is disabled
– Crystal oscillator is stopped
– Complete data retention
• Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– Wakeup from RST/NMI, P1, and P2

Interrupt Vector Addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 4. Interrupt Sources, Flags, and Vectors

SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
System Reset
Power-Up
External Reset
WDTIFG, KEYV (SYSRSTIV) (1) (2) Reset 0FFFEh 63, highest
Watchdog Timeout, Password
Violation
Flash Memory Password Violation
System NMI
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
PMM
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62
Vacant Memory Access
JMBOUTIFG (SYSSNIV) (1)
JTAG Mailbox
User NMI
NMI NMIIFG, OFIFG, ACCVIFG, BUSIFG
(Non)maskable 0FFFAh 61
Oscillator Fault (SYSUNIV) (1) (2)
Flash Memory Access Violation
Comp_B Comparator B interrupt flags (CBIV) (1) (3) Maskable 0FFF8h 60
TB0 TB0CCR0 CCIFG0 (3) Maskable 0FFF6h 59
TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0 Maskable 0FFF4h 58
TB0IFG (TB0IV) (1) (3)
Watchdog Timer_A Interval Timer
WDTIFG Maskable 0FFF2h 57
Mode
USCI_A0 Receive or Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV) (1) (3) Maskable 0FFF0h 56
USCI_B0 Receive or Transmit UCB0RXIFG, UCB0TXIFG (UCB0IV) (1) (3) Maskable 0FFEEh 55
ADC12_A ADC12IFG0 to ADC12IFG15 (ADC12IV) (1) (3) (4) Maskable 0FFECh 54
TA0 TA0CCR0 CCIFG0 (3) Maskable 0FFEAh 53
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0 Maskable 0FFE8h 52
TA0IFG (TA0IV) (1) (3)
USB_UBM USB interrupts (USBIV) (1) (3) Maskable 0FFE6h 51
(1) (3)
DMA DMA0IFG, DMA1IFG, DMA2IFG (DMAIV) Maskable 0FFE4h 50
TA1 TA1CCR0 CCIFG0 (3) Maskable 0FFE2h 49
TA1 Maskable 0FFE0h 48
I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV) (1) (3) Maskable 0FFDEh 47
USCI_A1 Receive or Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV) (1) (3) Maskable 0FFDCh 46
USCI_B1 Receive or Transmit UCB1RXIFG, UCB1TXIFG (UCB1IV) (1) (3) Maskable 0FFDAh 45
(3)
TA2 TA2CCR0 CCIFG0 Maskable 0FFD8h 44
TA2 Maskable 0FFD6h 43
I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV) (1) (3) Maskable 0FFD4h 42
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RTC_A Maskable 0FFD2h 41
RT0PSIFG, RT1PSIFG (RTCIV) (1) (3)
0FFD0h 40
Reserved Reserved (5)
⋮ ⋮
0FF80h 0, lowest
(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3) Interrupt flags are located in the module.
(4) Only on devices with ADC, otherwise reserved.
(5) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.

Memory Organization
Table 5. Memory Organization (1)

MSP430F5525
MSP430F5522 MSP430F5527 MSP430F5529
MSP430F5524
MSP430F5521 MSP430F5526 MSP430F5528
MSP430F5515
MSP430F5513 MSP430F5517 MSP430F5519
MSP430F5514
Memory (flash) Total Size 32 KB 64 KB 96 KB 128 KB
Main: interrupt vector 00FFFFh–00FF80h 00FFFFh–00FF80h 00FFFFh–00FF80h 00FFFFh–00FF80h
N/A N/A N/A 32 KB
Bank D
0243FFh–01C400h
N/A N/A 32 KB 32 KB
Bank C
01C3FFh–014400h 01C3FFh–014400h
Main: code memory
15 KB 32 KB 32 KB 32 KB
Bank B
00FFFFh–00C400h 0143FFh–00C400h 0143FFh–00C400h 0143FFh–00C400h
17 KB 32 KB 32 KB 32 KB
Bank A
00C3FFh–008000h 00C3FFh–004400h 00C3FFh–004400h 00C3FFh–004400h
Sector 3 2 KB (2) N/A N/A 2 KB
0043FFh–003C00h 0043FFh–003C00h
Sector 2 2 KB (3) N/A 2 KB 2 KB
003BFFh–003400h 003BFFh–003400h 003BFFh–003400h
RAM
Sector 1 2 KB 2 KB 2 KB 2 KB
0033FFh–002C00h 0033FFh–002C00h 0033FFh–002C00h 0033FFh–002C00h
002BFFh–002400h 002BFFh–002400h 002BFFh–002400h 002BFFh–002400h
USB RAM (4)
0023FFh–001C00h 0023FFh–001C00h 0023FFh–001C00h 0023FFh–001C00h
Info A 128 B 128 B 128 B 128 B
0019FFh–001980h 0019FFh–001980h 0019FFh–001980h 0019FFh–001980h
Info B 128 B 128 B 128 B 128 B
Information memory 00197Fh–001900h 00197Fh–001900h 00197Fh–001900h 00197Fh–001900h
(flash) Info C 128 B 128 B 128 B 128 B
Info D 128 B 128 B 128 B 128 B
00187Fh–001800h 00187Fh–001800h 00187Fh–001800h 00187Fh–001800h
BSL 3 512 B 512 B 512 B 512 B
BSL 2 512 B 512 B 512 B 512 B
Bootstrap loader (BSL) 0015FFh–001400h 0015FFh–001400h 0015FFh–001400h 0015FFh–001400h
memory (flash) BSL 1 512 B 512 B 512 B 512 B
BSL 0 512 B 512 B 512 B 512 B
Size 4 KB 4 KB 4 KB 4 KB
Peripherals
000FFFh–0h 000FFFh–0h 000FFFh–0h 000FFFh–0h
(1) N/A = Not available

(2) MSP430F5522 only
(3) MSP430F5522, MSP430F5521 only
(4) USB RAM can be used as general purpose RAM when not used for USB operation.

Bootstrap Loader (BSL)

The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the
device memory by the BSL is protected by an user-defined password. For further details on interfacing to
development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For
complete description of the features of the BSL and its implementation, see the MSP430 Programming Via the
Bootstrap Loader User's Guide (SLAU319).
USB BSL
All devices come pre-programmed with the USB BSL. Use of the USB BSL requires external access to the six
pins shown in Table 6. In addition to these pins, the application must support external components necessary for
normal USB operation; for example, the proper crystal on XT2IN and XT2OUT, proper decoupling, and so on.
Table 6. USB BSL Pin Requirements and Functions

DEVICE SIGNAL BSL FUNCTION
PU.0/DP USB data terminal DP
PU.1/DM USB data terminal DM
PUR USB pullup resistor terminal
VBUS USB bus power supply
VSSU USB ground supply
NOTE
The default USB BSL evaluates the logic level of the PUR pin after a BOR reset. If it is
pulled high externally, then the BSL is invoked. Therefore, unless the application is
invoking the BSL, it is important to keep PUR pulled low after a BOR reset, even if BSL or
USB is never used. Applying a 1-MΩ resistor to ground is recommended.
UART BSL
A UART BSL is also available that can be programmed by the user into the BSL memory by replacing the pre-
programmed, factory supplied, USB BSL. Use of the UART BSL requires external access to the six pins shown
in Table 7.
Table 7. UART BSL Pin Requirements and Functions

DEVICE SIGNAL BSL FUNCTION
RST/NMI/SBWTDIO Entry sequence signal
TEST/SBWTCK Entry sequence signal
P1.1 Data transmit
P1.2 Data receive
VCC Power supply
VSS Ground supply

JTAG Operation
JTAG Standard Interface

The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. The JTAG pin requirements are shown in Table 8. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's
Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see
MSP430 Programming Via the JTAG Interface (SLAU320).
Table 8. JTAG Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION
PJ.3/TCK IN JTAG clock input
PJ.2/TMS IN JTAG state control
PJ.1/TDI/TCLK IN JTAG data input, TCLK input
PJ.0/TDO OUT JTAG data output
TEST/SBWTCK IN Enable JTAG pins
RST/NMI/SBWTDIO IN External reset
VCC Power supply
VSS Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-
Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire
interface pin requirements are shown in Table 9. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of
the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface
(SLAU320).
Table 9. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION
TEST/SBWTCK IN Spy-Bi-Wire clock input
RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input/output
VCC Power supply
VSS Ground supply

Flash Memory (Link to User's Guide)

The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually. Segments A to D are also called information memory.
• Segment A can be locked separately.
RAM Memory (Link to User's Guide)

The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,
however all data is lost. Features of the RAM memory include:
• RAM memory has n sectors. The size of a sector can be found in Memory Organization.
• Each sector 0 to n can be complete disabled, however data retention is lost.
• Each sector 0 to n automatically enters low power retention mode when possible.
• For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide
(SLAU208).
Digital I/O (Link to User's Guide)

There are up to eight 8-bit I/O ports implemented: For 80 pin options, P1, P2, P3, P4, P5, P6, and P7 are
complete, and P8 is reduced to 3-bit I/O. For 64 pin options, P3 and P5 are reduced to 5-bit I/O and 6-bit I/O,
respectively, and P7 and P8 are completely removed. Port PJ contains four individual I/O ports, common to all
devices.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Pullup or pulldown on all ports is programmable.
• Drive strength on all ports is programmable.
• Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P8) or word-wise in pairs (PA through PD).

Port Mapping Controller (Link to User's Guide)

The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4 (see
Table 10). Table 11 shows the default mappings.
Table 10. Port Mapping Mnemonics and Functions

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
0 PM_NONE None DVSS
PM_CBOUT0 - Comparator_B output
1
PM_TB0CLK TB0 clock input
PM_ADC12CLK - ADC12CLK
2
PM_DMAE0 DMAE0 input
PM_SVMOUT - SVM output
3
PM_TB0OUTH TB0 high impedance input TB0OUTH
4 PM_TB0CCR0A TB0 CCR0 capture input CCI0A TB0 CCR0 compare output Out0
PM_UCA1RXD USCI_A1 UART RXD (Direction controlled by USCI - input)
11
PM_UCA1SOMI USCI_A1 SPI slave out master in (direction controlled by USCI)
PM_UCA1TXD USCI_A1 UART TXD (Direction controlled by USCI - output)
12
PM_UCA1SIMO USCI_A1 SPI slave in master out (direction controlled by USCI)
PM_UCA1CLK USCI_A1 clock input/output (direction controlled by USCI)
13
PM_UCB1STE USCI_B1 SPI slave transmit enable (direction controlled by USCI)
PM_UCB1SOMI USCI_B1 SPI slave out master in (direction controlled by USCI)
14
PM_UCB1SCL USCI_B1 I2C clock (open drain and direction controlled by USCI)
PM_UCB1SIMO USCI_B1 SPI slave in master out (direction controlled by USCI)
15
PM_UCB1SDA USCI_B1 I2C data (open drain and direction controlled by USCI)
PM_UCB1CLK USCI_B1 clock input/output (direction controlled by USCI)
16
PM_UCA1STE USCI_A1 SPI slave transmit enable (direction controlled by USCI)
17 PM_CBOUT1 None Comparator_B output
18 PM_MCLK None MCLK
19 - 30 Reserved None DVSS
Disables the output driver as well as the input Schmitt-trigger to prevent
31 (0FFh) (1) PM_ANALOG
parasitic cross currents when applying analog signals.
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored
resulting in a read out value of 31.

Table 11. Default Mapping

PIN PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
USCI_B1 SPI slave transmit enable (direction controlled by USCI)
P4.0/P4MAP0 PM_UCB1STE/PM_UCA1CLK
USCI_A1 clock input/output (direction controlled by USCI)
USCI_B1 SPI slave in master out (direction controlled by USCI)
P4.1/P4MAP1 PM_UCB1SIMO/PM_UCB1SDA
USCI_B1 I2C data (open drain and direction controlled by USCI)
USCI_B1 SPI slave out master in (direction controlled by USCI)
P4.2/P4MAP2 PM_UCB1SOMI/PM_UCB1SCL
USCI_B1 I2C clock (open drain and direction controlled by USCI)
USCI_A1 SPI slave transmit enable (direction controlled by USCI)
P4.3/P4MAP3 PM_UCB1CLK/PM_UCA1STE
USCI_B1 clock input/output (direction controlled by USCI)
USCI_A1 UART TXD (Direction controlled by USCI - output)
P4.4/P4MAP4 PM_UCA1TXD/PM_UCA1SIMO
USCI_A1 SPI slave in master out (direction controlled by USCI)
USCI_A1 UART RXD (Direction controlled by USCI - input)
P4.5/P4MAP5 PM_UCA1RXD/PM_UCA1SOMI
USCI_A1 SPI slave out master in (direction controlled by USCI)
P4.6/P4MAP6 PM_NONE None DVSS
P4.7/P4MAP7 PM_NONE None DVSS
Oscillator and System Clock (Link to User's Guide)

The clock system in the MSP430F552x and MSP430F551x family of devices is supported by the Unified Clock
System (UCS) module that includes support for a 32-kHz watch crystal oscillator (XT1 LF mode) (XT1 HF mode
is not supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency
oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal
oscillator (XT2). The UCS module is designed to meet the requirements of both low system cost and low power
consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a
digital modulator, stabilizes the DCO frequency to a programmable multiple of the selected FLL reference
frequency. The internal DCO provides a fast turn-on clock source and stabilizes in 3.5 µs (typical). The UCS
module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally
controlled oscillator DCO.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
Power Management Module (PMM) (Link to User's Guide)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS
and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (SVS) (the device is automatically reset) and supply voltage monitoring (SVM) (the device is
not automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
Hardware Multiplier (Link to User's Guide)

The multiplication operation is supported by a dedicated peripheral module. The module performs operations with
32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations.

Real-Time Clock (RTC_A) (Link to User's Guide)

The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated real-
time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that
can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar mode
integrates an internal calendar which compensates for months with less than 31 days and includes leap year
correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.
Watchdog Timer (WDT_A) (Link to User's Guide)

The primary function of the WDT_A module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
System Module (SYS) (Link to User's Guide)

The SYS module handles many of the system functions within the device. These include power-on reset and
power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootstrap
loader entry mechanisms, and configuration management (device descriptors). It also includes a data exchange
mechanism through JTAG called a JTAG mailbox that can be used in the application.
Table 12. System Module Interrupt Vector Registers

INTERRUPT VECTOR REGISTER ADDRESS INTERRUPT EVENT VALUE PRIORITY
SYSRSTIV, System Reset 019Eh No interrupt pending 00h
Brownout (BOR) 02h Highest
RST/NMI (POR) 04h
PMMSWBOR (BOR) 06h
Wakeup from LPMx.5 08h
Security violation (BOR) 0Ah
SVSL (POR) 0Ch
SVSH (POR) 0Eh
SVML_OVP (POR) 10h
SVMH_OVP (POR) 12h
PMMSWPOR (POR) 14h
WDT timeout (PUC) 16h
WDT password violation (PUC) 18h
KEYV flash password violation (PUC) 1Ah
Reserved 1Ch
Peripheral area fetch (PUC) 1Eh
PMM password violation (PUC) 20h
Reserved 22h to 3Eh Lowest
SYSSNIV, System NMI 019Ch No interrupt pending 00h
SVMLIFG 02h Highest
SVMHIFG 04h
SVSMLDLYIFG 06h
SVSMHDLYIFG 08h
VMAIFG 0Ah
JMBINIFG 0Ch
JMBOUTIFG 0Eh
SVMLVLRIFG 10h
SVMHVLRIFG 12h
Reserved 14h to 1Eh Lowest

Table 12. System Module Interrupt Vector Registers (continued)

INTERRUPT VECTOR REGISTER ADDRESS INTERRUPT EVENT VALUE PRIORITY
SYSUNIV, User NMI 019Ah No interrupt pending 00h
NMIFG 02h Highest
OFIFG 04h
ACCVIFG 06h
BUSIFG 08h
Reserved 0Ah to 1Eh Lowest
DMA Controller (Link to User's Guide)

The DMA controller allows movement of data from one memory address to another without CPU intervention. For
example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or
from a peripheral.
The USB timestamp generator also utilizes the DMA trigger assignments described in Table 13.
Table 13. DMA Trigger Assignments (1)

CHANNEL
TRIGGER
0 1 2
0 DMAREQ DMAREQ DMAREQ
1 TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG
7 TB0CCR0 CCIFG TB0CCR0 CCIFG TB0CCR0 CCIFG
8 TB0CCR2 CCIFG TB0CCR2 CCIFG TB0CCR2 CCIFG
9 Reserved Reserved Reserved
16 UCA0RXIFG UCA0RXIFG UCA0RXIFG
17 UCA0TXIFG UCA0TXIFG UCA0TXIFG
18 UCB0RXIFG UCB0RXIFG UCB0RXIFG
19 UCB0TXIFG UCB0TXIFG UCB0TXIFG
20 UCA1RXIFG UCA1RXIFG UCA1RXIFG
21 UCA1TXIFG UCA1TXIFG UCA1TXIFG
22 UCB1RXIFG UCB1RXIFG UCB1RXIFG
23 UCB1TXIFG UCB1TXIFG UCB1TXIFG
24 ADC12IFGx (2) ADC12IFGx (2) ADC12IFGx (2)
27 USB FNRXD USB FNRXD USB FNRXD
(1) If a reserved trigger source is selected, no Trigger1 is generated.

(2) Only on devices with ADC. Reserved on devices without ADC.
Table 13. DMA Trigger Assignments(1) (continued)

CHANNEL
TRIGGER
0 1 2
28 USB ready USB ready USB ready
29 MPY ready MPY ready MPY ready
30 DMA2IFG DMA0IFG DMA1IFG
31 DMAE0 DMAE0 DMAE0
Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode,
I2C Mode)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions,
A and B.
The USCI_An module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3 pin or 4 pin) or I2C.
The MSP430F55xx series includes two complete USCI modules (n = 0, 1).

TA0 (Link to User's Guide)

TA0 is a 16-bit timer and counter (Timer_A type) with five capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 14. TA0 Signal Connections

INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER
MODULE
RGC, YFF, INPUT INPUT OUTPUT OUTPUT
PN BLOCK RGC, YFF, ZQE PN
ZQE SIGNAL SIGNAL SIGNAL SIGNAL
18, H2-P1.0 21-P1.0 TA0CLK TACLK
ACLK
ACLK
(internal)
Timer NA NA
SMCLK
SMCLK
(internal)
18, H2-P1.0 21-P1.0 TA0CLK TACLK
19, H3-P1.1 22-P1.1 TA0.0 CCI0A 19, H3-P1.1 22-P1.1
DVSS CCI0B
CCR0 TA0 TA0.0
DVSS GND
DVCC VCC
20, J3-P1.2 23-P1.2 TA0.1 CCI1A 20, J3-P1.2 23-P1.2
ADC12 ADC12
CBOUT (internal) (1) (internal) (1)
CCI1B
(internal) CCR1 TA1 TA0.1 ADC12SHSx = ADC12SHSx =
{1} {1}
DVSS GND
DVCC VCC
21, G4-P1.3 24-P1.3 TA0.2 CCI2A 21, G4-P1.3 24-P1.3
ACLK
CCI2B
(internal) CCR2 TA2 TA0.2
DVSS GND
DVCC VCC
22, H4-P1.4 25-P1.4 TA0.3 CCI3A 22, H4-P1.4 25-P1.4
DVSS CCI3B
CCR3 TA3 TA0.3
DVSS GND
DVCC VCC
23, J4-P1.5 26-P1.5 TA0.4 CCI4A 23, J4-P1.5 26-P1.5
DVSS CCI4B
CCR4 TA4 TA0.4
DVSS GND
DVCC VCC
(1) Only on devices with ADC.


TA1 is a 16-bit timer and counter (Timer_A type) with three capture/compare registers. It can support multiple

MODULE
RGC, YFF, INPUT INPUT OUTPUT OUTPUT RGC, YFF,
PN BLOCK PN
ZQE SIGNAL SIGNAL SIGNAL SIGNAL ZQE
24, G5-P1.6 27-P1.6 TA1CLK TACLK
ACLK
ACLK
(internal)
Timer NA NA
SMCLK
SMCLK
(internal)
24, G5-P1.6 27-P1.6 TA1CLK TACLK
25, H5-P1.7 28-P1.7 TA1.0 CCI0A 25, H5-P1.7 28-P1.7
DVSS CCI0B
CCR0 TA0 TA1.0
DVSS GND
DVCC VCC
26, J5-P2.0 29-P2.0 TA1.1 CCI1A 26, J5-P2.0 29-P2.0
CBOUT
CCI1B
DVSS GND
DVCC VCC
27, G6-P2.1 30-P2.1 TA1.2 CCI2A 27, G6-P2.1 30-P2.1
ACLK
CCI2B
DVSS GND
DVCC VCC


TA2 is a 16-bit timer and counter (Timer_A type) with three capture/compare registers. It can support multiple

MODULE
PN BLOCK PN
ZQE SIGNAL SIGNAL SIGNAL SIGNAL ZQE
28, J6-P2.2 31-P2.2 TA2CLK TACLK
ACLK
ACLK
(internal)
Timer NA NA
SMCLK
SMCLK
(internal)
28, J6-P2.2 31-P2.2 TA2CLK TACLK
29, H6-P2.3 32-P2.3 TA2.0 CCI0A 29, H6-P2.3 32-P2.3
DVSS CCI0B
CCR0 TA0 TA2.0
DVSS GND
DVCC VCC
30, J7-P2.4 33-P2.4 TA2.1 CCI1A 30, J7-P2.4 33-P2.4
CBOUT
CCI1B
DVSS GND
DVCC VCC
31, J8-P2.5 34-P2.5 TA2.2 CCI2A 31, J8-P2.5 34-P2.5
ACLK
CCI2B
DVSS GND
DVCC VCC

TB0 (Link to User's Guide)

TB0 is a 16-bit timer and counter (Timer_B type) with seven capture/compare registers. It can support multiple
Table 17. TB0 Signal Connections

MODULE
PN BLOCK PN
ZQE (1) SIGNAL SIGNAL SIGNAL SIGNAL ZQE (1)
60-P7.7 TB0CLK TBCLK
ACLK
ACLK
(internal)
Timer NA NA
SMCLK
SMCLK
(internal)
60-P7.7 TB0CLK TBCLK
55-P5.6 TB0.0 CCI0A 55-P5.6
ADC12 ADC12
(internal) (2) (internal) (2)
55-P5.6 TB0.0 CCI0B
CCR0 TB0 TB0.0 ADC12SHSx = ADC12SHSx =
{2} {2}
DVSS GND
DVCC VCC
56-P5.7 TB0.1 CCI1A 56-P5.7
ADC12 (internal) ADC12 (internal)
CBOUT
CCI1B ADC12SHSx = ADC12SHSx =
(internal) CCR1 TB1 TB0.1 {3} {3}
DVSS GND
DVCC VCC
57-P7.4 TB0.2 CCI2A 57-P7.4
57-P7.4 TB0.2 CCI2B
CCR2 TB2 TB0.2
DVSS GND
DVCC VCC
58-P7.5 TB0.3 CCI3A 58-P7.5
58-P7.5 TB0.3 CCI3B
CCR3 TB3 TB0.3
DVSS GND
DVCC VCC
59-P7.6 TB0.4 CCI4A 59-P7.6
59-P7.6 TB0.4 CCI4B
CCR4 TB4 TB0.4
DVSS GND
DVCC VCC
42-P3.5 TB0.5 CCI5A 42-P3.5
42-P3.5 TB0.5 CCI5B
CCR5 TB5 TB0.5
DVSS GND
DVCC VCC
43-P3.6 TB0.6 CCI6A 43-P3.6
ACLK
CCI6B
(internal) CCR6 TB6 TB0.6
DVSS GND
DVCC VCC
(1) Timer functions are selectable through the port mapping controller.
(2) Only on devices with ADC

Comparator_B (Link to User's Guide)

The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,
battery voltage supervision, and monitoring of external analog signals.
ADC12_A (Link to User's Guide)

The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-
and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU
intervention.
CRC16 (Link to User's Guide)

The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
REF Voltage Reference (Link to User's Guide)

The reference module (REF) is responsible for generation of all critical reference voltages that can be used by
the various analog peripherals in the device.
USB Universal Serial Bus (Link to User's Guide)

The USB module is a fully integrated USB interface that is compliant with the USB 2.0 specification. The module
supports full-speed operation of control, interrupt, and bulk transfers. The module includes an integrated LDO,
PHY, and PLL. The PLL is highly-flexible and can support a wide range of input clock frequencies. USB RAM,
when not used for USB communication, can be used by the system.
Embedded Emulation Module (EEM) (Link to User's Guide)

The Embedded Emulation Module (EEM) supports real-time in-system debugging. The L version of the EEM
implemented on all devices has the following features:
• Eight hardware triggers or breakpoints on memory access
• Two hardware triggers or breakpoints on CPU register write access
• Up to ten hardware triggers can be combined to form complex triggers or breakpoints
• Two cycle counters
• Sequencer
• State storage
• Clock control on module level

Peripheral File Map
Table 18. Peripherals

OFFSET ADDRESS
MODULE NAME BASE ADDRESS
RANGE
Special Functions (see Table 19) 0100h 000h-01Fh
PMM (see Table 20) 0120h 000h-010h
Flash Control (see Table 21) 0140h 000h-00Fh
CRC16 (see Table 22) 0150h 000h-007h
RAM Control (see Table 23) 0158h 000h-001h
Watchdog (see Table 24) 015Ch 000h-001h
UCS (see Table 25) 0160h 000h-01Fh
SYS (see Table 26) 0180h 000h-01Fh
Shared Reference (see Table 27) 01B0h 000h-001h
Port Mapping Control (see Table 28) 01C0h 000h-002h
Port Mapping Port P4 (see Table 28) 01E0h 000h-007h
Port P1 and P2 (see Table 29) 0200h 000h-01Fh
Port P3 and P4 (see Table 30) 0220h 000h-00Bh
Port PJ (see Table 33) 0320h 000h-01Fh
TA0 (see Table 34) 0340h 000h-02Eh
TB0 (see Table 36) 03C0h 000h-02Eh
Real-Time Clock (RTC_A) (see Table 38) 04A0h 000h-01Bh
32-Bit Hardware Multiplier (see Table 39) 04C0h 000h-02Fh
DMA General Control (see Table 40) 0500h 000h-00Fh
DMA Channel 0 (see Table 40) 0510h 000h-00Ah
USCI_A0 (see Table 41) 05C0h 000h-01Fh
USCI_B0 (see Table 42) 05E0h 000h-01Fh
USCI_A1 (see Table 43) 0600h 000h-01Fh
USCI_B1 (see Table 44) 0620h 000h-01Fh
ADC12_A (see Table 45) 0700h 000h-03Eh
Comparator_B (see Table 46) 08C0h 000h-00Fh
USB Configuration (see Table 47) 0900h 000h-014h
USB Control (see Table 48) 0920h 000h-01Fh

Table 19. Special Function Registers (Base Address: 0100h)

REGISTER DESCRIPTION REGISTER OFFSET
SFR interrupt enable SFRIE1 00h
SFR interrupt flag SFRIFG1 02h
SFR reset pin control SFRRPCR 04h
Table 20. PMM Registers (Base Address: 0120h)

PMM Control 0 PMMCTL0 00h
PMM control 1 PMMCTL1 02h
SVS high side control SVSMHCTL 04h
SVS low side control SVSMLCTL 06h
PMM interrupt flags PMMIFG 0Ch
PMM interrupt enable PMMIE 0Eh
PMM power mode 5 control PM5CTL0 10h
Table 21. Flash Control Registers (Base Address: 0140h)

Flash control 1 FCTL1 00h
Table 22. CRC16 Registers (Base Address: 0150h)

CRC data input CRC16DI 00h
CRC data input reverse byte CRCDIRB 02h
CRC initialization and result CRCINIRES 04h
CRC result reverse byte CRCRESR 06h
Table 23. RAM Control Registers (Base Address: 0158h)

RAM control 0 RCCTL0 00h
Table 24. Watchdog Registers (Base Address: 015Ch)

Watchdog timer control WDTCTL 00h
Table 25. UCS Registers (Base Address: 0160h)

UCS control 0 UCSCTL0 00h
UCS control 5 UCSCTL5 0Ah
UCS control 6 UCSCTL6 0Ch
UCS control 7 UCSCTL7 0Eh

Table 26. SYS Registers (Base Address: 0180h)

System control SYSCTL 00h
Bootstrap loader configuration area SYSBSLC 02h
JTAG mailbox control SYSJMBC 06h
JTAG mailbox input 0 SYSJMBI0 08h
JTAG mailbox input 1 SYSJMBI1 0Ah
JTAG mailbox output 0 SYSJMBO0 0Ch
JTAG mailbox output 1 SYSJMBO1 0Eh
Bus Error vector generator SYSBERRIV 18h
User NMI vector generator SYSUNIV 1Ah
System NMI vector generator SYSSNIV 1Ch
Reset vector generator SYSRSTIV 1Eh
Table 27. Shared Reference Registers (Base Address: 01B0h)

Shared reference control REFCTL 00h
Table 28. Port Mapping Registers

(Base Address of Port Mapping Control: 01C0h, Port P4: 01E0h)
Port mapping key and ID register PMAPKEYID 00h
Port mapping control register PMAPCTL 02h
Port P4.0 mapping register P4MAP0 00h

Table 29. Port P1 and P2 Registers (Base Address: 0200h)

Port P1 input P1IN 00h
Port P1 output P1OUT 02h
Port P1 direction P1DIR 04h
Port P1 pullup or pulldown enable P1REN 06h
Port P1 drive strength P1DS 08h
Port P1 selection P1SEL 0Ah
Port P1 interrupt vector word P1IV 0Eh
Port P1 interrupt edge select P1IES 18h
Port P1 interrupt enable P1IE 1Ah
Port P1 interrupt flag P1IFG 1Ch
Port P2 selection P2SEL 0Bh
Port P2 interrupt vector word P2IV 1Eh
Port P2 interrupt edge select P2IES 19h
Port P2 interrupt enable P2IE 1Bh
Port P2 interrupt flag P2IFG 1Dh




Table 33. Port J Registers (Base Address: 0320h)

Port PJ input PJIN 00h
Port PJ output PJOUT 02h
Port PJ direction PJDIR 04h
Port PJ pullup or pulldown enable PJREN 06h
Port PJ drive strength PJDS 08h

Table 34. TA0 Registers (Base Address: 0340h)

TA0 control TA0CTL 00h
Capture/compare control 0 TA0CCTL0 02h
Capture/compare control 4 TA0CCTL4 0Ah
TA0 counter register TA0R 10h
Capture/compare register 0 TA0CCR0 12h
Capture/compare register 4 TA0CCR4 1Ah
TA0 expansion register 0 TA0EX0 20h
TA0 interrupt vector TA0IV 2Eh


Table 36. TB0 Registers (Base Address: 03C0h)

TB0 control TB0CTL 00h
Capture/compare control 0 TB0CCTL0 02h
Capture/compare control 4 TB0CCTL4 0Ah
Capture/compare control 5 TB0CCTL5 0Ch
Capture/compare control 6 TB0CCTL6 0Eh
TB0 register TB0R 10h
Capture/compare register 0 TB0CCR0 12h
Capture/compare register 4 TB0CCR4 1Ah
Capture/compare register 5 TB0CCR5 1Ch
Capture/compare register 6 TB0CCR6 1Eh
TB0 expansion register 0 TB0EX0 20h
TB0 interrupt vector TB0IV 2Eh


Table 38. Real-Time Clock Registers (Base Address: 04A0h)

RTC control 0 RTCCTL0 00h
RTC prescaler 0 control RTCPS0CTL 08h
RTC prescaler 1 control RTCPS1CTL 0Ah
RTC prescaler 0 RTCPS0 0Ch
RTC prescaler 1 RTCPS1 0Dh
RTC interrupt vector word RTCIV 0Eh
RTC seconds, RTC counter register 1 RTCSEC, RTCNT1 10h
RTC minutes, RTC counter register 2 RTCMIN, RTCNT2 11h
RTC hours, RTC counter register 3 RTCHOUR, RTCNT3 12h
RTC day of week, RTC counter register 4 RTCDOW, RTCNT4 13h
RTC days RTCDAY 14h
RTC month RTCMON 15h
RTC year low RTCYEARL 16h
RTC year high RTCYEARH 17h
RTC alarm minutes RTCAMIN 18h
RTC alarm hours RTCAHOUR 19h
RTC alarm day of week RTCADOW 1Ah
RTC alarm days RTCADAY 1Bh

Table 39. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)

16-bit operand 1 – multiply MPY 00h
16-bit operand 1 – signed multiply MPYS 02h
16-bit operand 1 – multiply accumulate MAC 04h
16-bit operand 1 – signed multiply accumulate MACS 06h
16-bit operand 2 OP2 08h
16 × 16 result low word RESLO 0Ah
16 × 16 result high word RESHI 0Ch
16 × 16 sum extension register SUMEXT 0Eh
32-bit operand 1 – multiply low word MPY32L 10h
32-bit operand 1 – multiply high word MPY32H 12h
32-bit operand 1 – signed multiply low word MPYS32L 14h
32-bit operand 1 – signed multiply high word MPYS32H 16h
32-bit operand 1 – multiply accumulate low word MAC32L 18h
32-bit operand 1 – multiply accumulate high word MAC32H 1Ah
32-bit operand 1 – signed multiply accumulate low word MACS32L 1Ch
32-bit operand 1 – signed multiply accumulate high word MACS32H 1Eh
32-bit operand 2 – low word OP2L 20h
32-bit operand 2 – high word OP2H 22h
32 × 32 result 0 – least significant word RES0 24h
32 × 32 result 1 RES1 26h
32 × 32 result 2 RES2 28h
32 × 32 result 3 – most significant word RES3 2Ah
MPY32 control register 0 MPY32CTL0 2Ch

Table 40. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h)
DMA channel 0 control DMA0CTL 00h
DMA channel 0 source address low DMA0SAL 02h
DMA channel 0 source address high DMA0SAH 04h
DMA channel 0 destination address low DMA0DAL 06h
DMA channel 0 destination address high DMA0DAH 08h
DMA channel 0 transfer size DMA0SZ 0Ah
DMA module control 0 DMACTL0 00h
DMA interrupt vector DMAIV 0Eh
Table 41. USCI_A0 Registers (Base Address: 05C0h)

USCI control 1 UCA0CTL1 00h
USCI baud rate 0 UCA0BR0 06h
USCI modulation control UCA0MCTL 08h
USCI status UCA0STAT 0Ah
USCI receive buffer UCA0RXBUF 0Ch
USCI transmit buffer UCA0TXBUF 0Eh
USCI LIN control UCA0ABCTL 10h
USCI IrDA transmit control UCA0IRTCTL 12h
USCI IrDA receive control UCA0IRRCTL 13h
USCI interrupt enable UCA0IE 1Ch
USCI interrupt flags UCA0IFG 1Dh
USCI interrupt vector word UCA0IV 1Eh

Table 42. USCI_B0 Registers (Base Address: 05E0h)

USCI synchronous control 1 UCB0CTL1 00h
USCI synchronous bit rate 0 UCB0BR0 06h
USCI synchronous status UCB0STAT 0Ah
USCI synchronous receive buffer UCB0RXBUF 0Ch
USCI synchronous transmit buffer UCB0TXBUF 0Eh
USCI I2C own address UCB0I2COA 10h
USCI I2C slave address UCB0I2CSA 12h
USCI interrupt enable UCB0IE 1Ch
USCI interrupt flags UCB0IFG 1Dh
USCI interrupt vector word UCB0IV 1Eh
Table 43. USCI_A1 Registers (Base Address: 0600h)

USCI modulation control UCA1MCTL 08h
USCI status UCA1STAT 0Ah
USCI receive buffer UCA1RXBUF 0Ch
USCI transmit buffer UCA1TXBUF 0Eh
USCI LIN control UCA1ABCTL 10h
USCI IrDA transmit control UCA1IRTCTL 12h
USCI IrDA receive control UCA1IRRCTL 13h
USCI interrupt enable UCA1IE 1Ch
USCI interrupt flags UCA1IFG 1Dh
USCI interrupt vector word UCA1IV 1Eh

Table 44. USCI_B1 Registers (Base Address: 0620h)

USCI synchronous status UCB1STAT 0Ah
USCI synchronous receive buffer UCB1RXBUF 0Ch
USCI synchronous transmit buffer UCB1TXBUF 0Eh
USCI I2C own address UCB1I2COA 10h
USCI I2C slave address UCB1I2CSA 12h
USCI interrupt enable UCB1IE 1Ch
USCI interrupt flags UCB1IFG 1Dh
USCI interrupt vector word UCB1IV 1Eh

Table 45. ADC12_A Registers (Base Address: 0700h)

Control register 0 ADC12CTL0 00h
Interrupt-flag register ADC12IFG 0Ah
Interrupt-enable register ADC12IE 0Ch
Interrupt-vector-word register ADC12IV 0Eh
ADC memory-control register 0 ADC12MCTL0 10h
ADC memory-control register 10 ADC12MCTL10 1Ah
ADC memory-control register 11 ADC12MCTL11 1Bh
ADC memory-control register 12 ADC12MCTL12 1Ch
ADC memory-control register 13 ADC12MCTL13 1Dh
ADC memory-control register 14 ADC12MCTL14 1Eh
ADC memory-control register 15 ADC12MCTL15 1Fh
Conversion memory 0 ADC12MEM0 20h
Conversion memory 5 ADC12MEM5 2Ah
Conversion memory 6 ADC12MEM6 2Ch
Conversion memory 7 ADC12MEM7 2Eh
Conversion memory 13 ADC12MEM13 3Ah
Conversion memory 14 ADC12MEM14 3Ch
Conversion memory 15 ADC12MEM15 3Eh

Table 46. Comparator_B Registers (Base Address: 08C0h)

Comp_B control register 0 CBCTL0 00h
Comp_B interrupt register CBINT 0Ch
Comp_B interrupt vector word CBIV 0Eh
Table 47. USB Configuration Registers (Base Address: 0900h)

USB key and ID USBKEYID 00h
USB module configuration USBCNF 02h
USB PHY control USBPHYCTL 04h
USB power control USBPWRCTL 08h
USB PLL control USBPLLCTL 10h
USB PLL divider USBPLLDIV 12h
USB PLL interrupts USBPLLIR 14h
Table 48. USB Control Registers (Base Address: 0920h)

Input endpoint#0 configuration IEPCNF_0 00h
Input endpoint #0 byte count IEPCNT_0 01h
Output endpoint#0 configuration OEPCNF_0 02h
Output endpoint #0 byte count OEPCNT_0 03h
Input endpoint interrupt enables IEPIE 0Eh
Output endpoint interrupt enables OEPIE 0Fh
Input endpoint interrupt flags IEPIFG 10h
Output endpoint interrupt flags OEPIFG 11h
USB interrupt vector USBIV 12h
USB maintenance MAINT 16h
Time stamp TSREG 18h
USB frame number USBFN 1Ah
USB control USBCTL 1Ch
USB interrupt enables USBIE 1Dh
USB interrupt flags USBIFG 1Eh
Function address FUNADR 1Fh

Absolute Maximum Ratings (1)

over operating free-air temperature range (unless otherwise noted)
Voltage applied at VCC to VSS –0.3 V to 4.1 V
(2)
Voltage applied to any pin (excluding VCORE, VBUS, V18) –0.3 V to VCC + 0.3 V
Diode current at any device pin ±2 mA
Storage temperature range, Tstg (3) –55°C to 150°C
Maximum operating junction temperature, TJ 95°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Thermal Packaging Characteristics

PARAMETER VALUE UNIT
LQFP (PN) 70
Low-K board (JESD51-3) VQFN (RGC) 55
BGA (ZQE) 84
θJA Junction-to-ambient thermal resistance, still air °C/W
LQFP (PN) 45
High-K board (JESD51-7) VQFN (RGC) 25
BGA (ZQE) 46
LQFP (PN) 12
θJC Junction-to-case thermal resistance VQFN (RGC) 12 °C/W
BGA (ZQE) 30
LQFP (PN) 22
θJB Junction-to-board thermal resistance VQFN (RGC) 6 °C/W
BGA (ZQE) 20

Recommended Operating Conditions

Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN NOM MAX UNIT
PMMCOREVx = 0 1.8 3.6 V
Supply voltage during program execution and flash PMMCOREVx = 0, 1 2.0 3.6 V
VCC
programming (AVCC = DVCC1/2 = DVCC) (1) (2) PMMCOREVx = 0, 1, 2 2.2 3.6 V
PMMCOREVx = 0, 1, 2, 3 2.4 3.6 V
PMMCOREVx = 0 1.8 3.6 V
Supply voltage during USB operation, USB PLL disabled, PMMCOREVx = 0, 1 2.0 3.6 V
USB_EN = 1, UPLLEN = 0 PMMCOREVx = 0, 1, 2 2.2 3.6 V
VCC, USB
PMMCOREVx = 0, 1, 2, 3 2.4 3.6 V
Supply voltage during USB operation, USB PLL enabled (3), PMMCOREVx = 2 2.2 3.6 V
USB_EN = 1, UPLLEN = 1 PMMCOREVx = 2, 3 2.4 3.6 V
VSS Supply voltage (AVSS = DVSS1/2 = DVSS) 0 V
TA Operating free-air temperature I version -40 85 °C
TJ Operating junction temperature I version -40 85 °C
CVCORE Recommended capacitor at VCORE 470 nF
CDVCC/
Capacitor ratio of DVCC to VCORE 10
CVCORE
PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V 0 8.0
(default condition)
PMMCOREVx = 1,
Processor frequency (maximum MCLK frequency) (4) 0 12.0
fSYSTEM 2.0 V ≤ VCC ≤ 3.6 V MHz
(see Figure 1)
PMMCOREVx = 2,
0 20.0
2.2 V ≤ VCC ≤ 3.6 V
PMMCOREVx = 3,
0 25.0
2.4 V ≤ VCC ≤ 3.6 V
fSYSTEM_USB Minimum processor frequency for USB operation 1.5 MHz
USB_wait Wait state cycles during USB operation 16 cycles
(1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold
parameters for the exact values and further details.
(3) USB operation with USB PLL enabled requires PMMCOREVx ≥ 2 for proper operation.
(4) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

25
20
System Frequency - MHz

2 2, 3
12
1 1, 2 1, 2, 3
0 0, 1 0, 1, 2 0, 1, 2, 3
0
1.8 2.0 2.2 2.4 3.6
Supply Voltage - V
The numbers within the fields denote the supported PMMCOREVx settings.
Figure 1. Maximum System Frequency
Electrical Characteristics
Active Mode Supply Current Into VCC Excluding External Current

over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK)

EXECUTION
PARAMETER VCC PMMCOREVx 1 MHz 8 MHz 12 MHz 20 MHz 25 MHz UNIT
MEMORY
TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX
0 0.36 0.47 2.32 2.60
1 0.40 2.65 4.0 4.4
IAM, Flash Flash 3.0 V mA
2 0.44 2.90 4.3 7.1 7.7
3 0.46 3.10 4.6 7.6 10.1 11.0
0 0.20 0.24 1.20 1.30
1 0.22 1.35 2.0 2.2
IAM, RAM RAM 3.0 V mA
2 0.24 1.50 2.2 3.7 4.2
3 0.26 1.60 2.4 3.9 5.3 6.2
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing. USB disabled (VUSBEN = 0, SLDOEN = 0).
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.

Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)
-40°C 25°C 60°C 85°C

PARAMETER VCC PMMCOREVx UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
2.2 V 0 73 77 85 80 85 97
ILPM0,1MHz Low-power mode 0 (3) (4) µA
3.0 V 3 79 83 92 88 95 105
2.2 V 0 6.5 6.5 12 10 11 17
ILPM2 Low-power mode 2 (5) (4) µA
3.0 V 3 7.0 7.0 13 11 12 18
0 1.60 1.90 2.6 5.6
2.2 V 1 1.65 2.00 2.7 5.9
2 1.75 2.15 2.9 6.1
Low-power mode 3,
ILPM3,XT1LF 0 1.8 2.1 2.9 2.8 5.8 8.3 µA
crystal mode (6) (4)
1 1.9 2.3 2.9 6.1
3.0 V
2 2.0 2.4 3.0 6.3
3 2.0 2.5 3.9 3.1 6.4 9.3
0 1.1 1.4 2.7 1.9 4.9 7.4
Low-power mode 3, 1 1.1 1.4 2.0 5.2
ILPM3,VLO 3.0 V µA
VLO mode (7) (4) 2 1.2 1.5 2.1 5.3
3 1.3 1.6 3.0 2.2 5.4 8.5
0 0.9 1.1 1.5 1.8 4.8 7.3
1 1.1 1.2 2.0 5.1
ILPM4 Low-power mode 4 (8) (4) 3.0 V µA
2 1.2 1.2 2.1 5.2
3 1.3 1.3 1.6 2.2 5.3 8.1
(9)
ILPM4.5 Low-power mode 4.5 3.0 V 0.15 0.18 0.35 0.26 0.5 1.0 µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0).
(4) Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor and monitor disabled (SVSL, SVML).
High-side monitor disabled (SVMH). RAM retention enabled.
(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting = 1
MHz operation, DCO bias generator enabled.
USB disabled (VUSBEN = 0, SLDOEN = 0)
(6) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
(7) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(9) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz

Schmitt-Trigger Inputs – General Purpose I/O (1)

(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)
(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
1.8 V 0.80 1.40
VIT+ Positive-going input threshold voltage V
3V 1.50 2.10
1.8 V 0.45 1.00
VIT– Negative-going input threshold voltage V
3V 0.75 1.65
1.8 V 0.3 0.85
Vhys Input voltage hysteresis (VIT+ – VIT–) V
3V 0.4 1.0
For pullup: VIN = VSS
RPull Pullup and pulldown resistor (2) 20 35 50 kΩ
For pulldown: VIN = VCC
CI Input capacitance VIN = VSS or VCC 5 pF
(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
(2) Also applies to RST pin when pullup or pulldown resistor is enabled.
Inputs – Ports P1 and P2 (1)

(P1.0 to P1.7, P2.0 to P2.7)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
(2)
t(int) External interrupt timing External trigger pulse duration to set interrupt flag 2.2 V, 3 V 20 ns
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).
Leakage Current – General Purpose I/O

(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
(1) (2)
Ilkg(Px.x) High-impedance leakage current 1.8 V, 3 V -50 50 nA
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
Outputs – General Purpose I/O (Full Drive Strength)

(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
I(OHmax) = –3 mA (1) VCC – 0.25 VCC
1.8 V
I(OHmax) = –10 mA (2) VCC – 0.60 VCC
VOH High-level output voltage V
3V
I(OHmax) = –15 mA (2) VCC – 0.60 VCC
I(OLmax) = 3 mA (1) VSS VSS + 0.25
1.8 V
VOL Low-level output voltage (1)
V
I(OLmax) = 5 mA VSS VSS + 0.25
3V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.

Outputs – General Purpose I/O (Reduced Drive Strength)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
1.8 V
VOH High-level output voltage (2)
V
I(OHmax) = –2 mA VCC – 0.25 VCC
3.0 V
1.8 V
VOL Low-level output voltage V
3.0 V
(1) Selecting reduced drive strength may reduce EMI.

(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
(3) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
Output Frequency – General Purpose I/O

PARAMETER TEST CONDITIONS MIN MAX UNIT
VCC = 1.8 V,
16
Port output frequency (1) (2)
PMMCOREVx = 0
fPx.y See MHz
(with load) VCC = 3 V,
25
PMMCOREVx = 3
ACLK, VCC = 1.8 V,
16
SMCLK, PMMCOREVx = 0
fPort_CLK Clock output frequency MHz
MCLK, VCC = 3 V,
CL = 20 pF (2) 25
PMMCOREVx = 3
(1) A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full
drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)

TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT
vs vs
LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
25.0 8.0
VCC = 3.0 V VCC = 1.8 V TA = 25°C
IOL – Typical Low-Level Output Current – mA

Px.y 7.0 Px.y

TA = 25°C
20.0
6.0 TA = 85°C
TA = 85°C
5.0
15.0
4.0
10.0
3.0
2.0
5.0
1.0
0.0 0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0
VOL – Low-Level Output Voltage – V VOL – Low-Level Output Voltage – V
Figure 2. Figure 3.
TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs vs
HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE
0.0 0.0
VCC = 3.0 V VCC = 1.8 V
IOH – Typical High-Level Output Current – mA
Px.y Px.y
-1.0
-5.0
-2.0
-3.0
-10.0
-4.0
TA = 85°C
-15.0
TA = 85°C -5.0
-6.0 TA = 25°C
-20.0 TA = 25°C
-7.0
-25.0 -8.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0
VOH – High-Level Output Voltage – V VOH – High-Level Output Voltage – V
Figure 4. Figure 5.

Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)

TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT
vs vs
LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
60.0
TA = 25°C 24
VCC = 3.0 V VCC = 1.8 V

55.0
Px.y Px.y TA = 25°C
50.0
TA = 85°C 20
45.0
40.0 TA = 85°C
16
35.0
30.0 12
25.0
20.0 8
15.0
10.0 4
5.0
0.0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0
VOL – Low-Level Output Voltage – V VOL – Low-Level Output Voltage – V
Figure 6. Figure 7.
TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs vs
HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE
0.0 0
VCC = 3.0 V VCC = 1.8 V
-5.0 Px.y
Px.y
-10.0
-4
-15.0
-20.0
-25.0 -8
-30.0
-35.0 -12
-40.0
-45.0 TA = 85°C
TA = 85°C -16
-50.0
-55.0 TA = 25°C
TA = 25°C
-60.0 -20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0
VOH – High-Level Output Voltage – V VOH – High-Level Output Voltage – V
Figure 8. Figure 9.

Crystal Oscillator, XT1, Low-Frequency Mode (1)

fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
0.075
XT1DRIVEx = 1, TA = 25°C
Differential XT1 oscillator
crystal current consumption fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0,
ΔIDVCC.LF 3.0 V 0.170 µA
from lowest drive setting, LF XT1DRIVEx = 2, TA = 25°C
mode
0.290
XT1 oscillator crystal
fXT1,LF0 XTS = 0, XT1BYPASS = 0 32768 Hz
frequency, LF mode
XT1 oscillator logic-level
fXT1,LF,SW square-wave input frequency, XTS = 0, XT1BYPASS = 1 (2) (3)
10 32.768 50 kHz
LF mode
XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0,
210
Oscillation allowance for fXT1,LF = 32768 Hz, CL,eff = 6 pF
OALF kΩ
LF crystals (4) XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1,
300
fXT1,LF = 32768 Hz, CL,eff = 12 pF
XTS = 0, XCAPx = 0 (6) 2
Integrated effective load XTS = 0, XCAPx = 1 5.5
CL,eff pF
capacitance, LF mode (5) XTS = 0, XCAPx = 2 8.5
XTS = 0, XCAPx = 3 12.0
XTS = 0, Measured at ACLK,
Duty cycle, LF mode 30 70 %
fXT1,LF = 32768 Hz
Oscillator fault frequency,
fFault,LF XTS = 0 (8) 10 10000 Hz
LF mode (7)
1000
XT1DRIVEx = 0, TA = 25°C, CL,eff = 6 pF
tSTART,LF Startup time, LF mode 3.0 V ms
500
XT1DRIVEx = 3, TA = 25°C, CL,eff = 12 pF
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, XT1 circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this data sheet.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
(a) For XT1DRIVEx = 0, CL,eff ≤ 6 pF.
(b) For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF.
(c) For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF.
(d) For XT1DRIVEx = 3, CL,eff ≥ 6 pF.
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.

Crystal Oscillator, XT2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2)

fOSC = 4 MHz, XT2OFF = 0, XT2BYPASS = 0,
200
260
XT2 oscillator crystal XT2DRIVEx = 1, TA = 25°C
IDVCC.XT2 3.0 V µA
current consumption fOSC = 20 MHz, XT2OFF = 0, XT2BYPASS = 0,
325
450
fXT2,HF0 XT2DRIVEx = 0, XT2BYPASS = 0 (3) 4 8 MHz
frequency, mode 0
frequency, mode 1
frequency, mode 2
frequency, mode 3
XT2 oscillator logic-level
fXT2,HF,SW square-wave input XT2BYPASS = 1 (4) (3)
0.7 32 MHz
frequency, bypass mode
XT2DRIVEx = 0, XT2BYPASS = 0,
450
fXT2,HF0 = 6 MHz, CL,eff = 15 pF
320
Oscillation allowance for fXT2,HF1 = 12 MHz, CL,eff = 15 pF
OAHF Ω
HF crystals (5) XT2DRIVEx = 2, XT2BYPASS = 0,
200
200
fOSC = 6 MHz, XT2BYPASS = 0, XT2DRIVEx = 0,
0.5
TA = 25°C, CL,eff = 15 pF
tSTART,HF Startup time 3.0 V ms
fOSC = 20 MHz, XT2BYPASS = 0, XT2DRIVEx = 2,
0.3
TA = 25°C, CL,eff = 15 pF
Integrated effective load
CL,eff capacitance, HF 1 pF
mode (6) (1)
Duty cycle Measured at ACLK, fXT2,HF2 = 20 MHz 40 50 60 %
Oscillator fault (8)
fFault,HF XT2BYPASS = 1 30 300 kHz
frequency (7)
(1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. In general, an effective load capacitance
of up to 18 pF can be supported.
(2) To improve EMI on the XT2 oscillator the following guidelines should be observed.
(a) Keep the traces between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
(d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(3) This represents the maximum frequency that can be input to the device externally. Maximum frequency achievable on the device
operation is based on the frequencies present on ACLK, MCLK, and SMCLK cannot be exceed for a given range of operation.
(4) When XT2BYPASS is set, the XT2 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined
in the Schmitt-trigger Inputs section of this data sheet.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.

Internal Very-Low-Power Low-Frequency Oscillator (VLO)

fVLO VLO frequency Measured at ACLK 1.8 V to 3.6 V 6 9.4 14 kHz
dfVLO/dT VLO frequency temperature drift Measured at ACLK (1) 1.8 V to 3.6 V 0.5 %/°C
dfVLO/dVCC VLO frequency supply voltage drift Measured at ACLK (2) 1.8 V to 3.6 V 4 %/V
Duty cycle Measured at ACLK 1.8 V to 3.6 V 40 50 60 %
(1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V)
Internal Reference, Low-Frequency Oscillator (REFO)

IREFO REFO oscillator current consumption TA = 25°C 1.8 V to 3.6 V 3 µA
REFO frequency calibrated Measured at ACLK 1.8 V to 3.6 V 32768 Hz
fREFO Full temperature range 1.8 V to 3.6 V -3.5 3.5 %
REFO absolute tolerance calibrated
TA = 25°C 3V -1.5 1.5 %
dfREFO/dT REFO frequency temperature drift Measured at ACLK (1) 1.8 V to 3.6 V 0.01 %/°C
dfREFO/dVCC REFO frequency supply voltage drift Measured at ACLK (2) 1.8 V to 3.6 V 1.0 %/V
Duty cycle Measured at ACLK 1.8 V to 3.6 V 40 50 60 %
tSTART REFO startup time 40%/60% duty cycle 1.8 V to 3.6 V 25 µs

DCO Frequency
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1)
fDCO(0,0) DCO frequency (0, 0) DCORSELx = 0, DCOx = 0, MODx = 0 0.07 0.20 MHz
fDCO(0,31) DCO frequency (0, 31) (1) DCORSELx = 0, DCOx = 31, MODx = 0 0.70 1.70 MHz
(1)
(1)
(1)
(1)
fDCO(7,31) DCO frequency (7, 31) (1) DCORSELx = 7, DCOx = 31, MODx = 0 60 135 MHz
Frequency step between range
SDCORSEL SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO) 1.2 2.3 ratio
DCORSEL and DCORSEL + 1
Frequency step between tap
SDCO SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO) 1.02 1.12 ratio
DCO and DCO + 1
Duty cycle Measured at SMCLK 40 50 60 %
DCO frequency temperature
dfDCO/dT fDCO = 1 MHz 0.1 %/°C
drift (2)
(3)
dfDCO/dVCC DCO frequency voltage drift fDCO = 1 MHz 1.9 %/V
(1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31
(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual
fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the
selected range is at its minimum or maximum tap setting.
Typical DCO Frequency, VCC = 3.0 V, TA = 25°C

100
10
fDCO – MHz
DCOx = 31
1
DCOx = 0
0.1
0 1 2 3 4 5 6 7
DCORSEL
Figure 10. Typical DCO Frequency

PMM, Brown-Out Reset (BOR)

V(DVCC_BOR_IT–) BORH on voltage, DVCC falling level | dDVCC/dt | < 3 V/s 1.45 V
V(DVCC_BOR_IT+) BORH off voltage, DVCC rising level | dDVCC/dt | < 3 V/s 0.80 1.30 1.50 V
V(DVCC_BOR_hys) BORH hysteresis 60 250 mV
Pulse duration required at RST/NMI pin
tRESET 2 µs
to accept a reset
PMM, Core Voltage

VCORE3(AM) Core voltage, active mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V 1.90 V
Core voltage, low-current mode,
VCORE3(LPM) 2.4 V ≤ DVCC ≤ 3.6 V 1.94 V
PMMCOREV = 3
PMMCOREV = 2
PMMCOREV = 1
PMMCOREV = 0
PMM, SVS High Side

SVSHE = 0, DVCC = 3.6 V 0 nA
I(SVSH) SVS current consumption SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0 200 nA
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1 1.5 µA
SVSHE = 1, SVSHRVL = 0 1.57 1.68 1.78
SVSHE = 1, SVSHRVL = 1 1.79 1.88 1.98
V(SVSH_IT–) SVSH on voltage level (1) V
SVSHE = 1, SVSHRVL = 2 1.98 2.08 2.21
SVSHE = 1, SVSHRVL = 3 2.10 2.18 2.31
SVSHE = 1, SVSMHRRL = 0 1.62 1.74 1.85
SVSHE = 1, SVSMHRRL = 1 1.88 1.94 2.07
SVSHE = 1, SVSMHRRL = 2 2.07 2.14 2.28
SVSHE = 1, SVSMHRRL = 3 2.20 2.30 2.42
V(SVSH_IT+) SVSH off voltage level (1) V
SVSHE = 1, SVSMHRRL = 4 2.32 2.40 2.55
SVSHE = 1, SVSMHRRL = 5 2.52 2.70 2.88
SVSHE = 1, SVSMHRRL = 6 2.90 3.10 3.23
SVSHE = 1, SVSMHRRL = 7 2.90 3.10 3.23
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1 2.5
tpd(SVSH) SVSH propagation delay µs
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0 20
SVSHE = 0 → 1, SVSHFP = 1 12.5
t(SVSH) SVSH on or off delay time µs
SVSHE = 0 → 1, SVSHFP = 0 100
dVDVCC/dt DVCC rise time 0 1000 V/s
(1) The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and use.

PMM, SVM High Side

SVMHE = 0, DVCC = 3.6 V 0 nA
I(SVMH) SVMH current consumption SVMHE= 1, DVCC = 3.6 V, SVMHFP = 0 200 nA
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 1.5 µA
SVMHE = 1, SVSMHRRL = 0 1.62 1.74 1.85
SVMHE = 1, SVSMHRRL = 1 1.88 1.94 2.07
SVMHE = 1, SVSMHRRL = 2 2.07 2.14 2.28
SVMHE = 1, SVSMHRRL = 3 2.20 2.30 2.42
(1)
V(SVMH) SVMH on or off voltage level SVMHE = 1, SVSMHRRL = 4 2.32 2.40 2.55 V
SVMHE = 1, SVSMHRRL = 5 2.52 2.70 2.88
SVMHE = 1, SVSMHRRL = 6 2.90 3.10 3.23
SVMHE = 1, SVSMHRRL = 7 2.90 3.10 3.23
SVMHE = 1, SVMHOVPE = 1 3.75
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1 2.5
tpd(SVMH) SVMH propagation delay µs
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0 20
SVMHE = 0 → 1, SVMHFP = 1 12.5
t(SVMH) SVMH on or off delay time µs
SVMHE = 0 → 1, SVMHFP = 0 100
(1) The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and use.
PMM, SVS Low Side

SVSLE = 0, PMMCOREV = 2 0 nA
I(SVSL) SVSL current consumption SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 200 nA
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 1.5 µA
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1 2.5
tpd(SVSL) SVSL propagation delay µs
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0 20
SVSLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1 12.5
t(SVSL) SVSL on or off delay time µs
SVSLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0 100
PMM, SVM Low Side

SVMLE = 0, PMMCOREV = 2 0 nA
I(SVML) SVML current consumption SVMLE= 1, PMMCOREV = 2, SVMLFP = 0 200 nA
SVMLE= 1, PMMCOREV = 2, SVMLFP = 1 1.5 µA
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 2.5
tpd(SVML) SVML propagation delay µs
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 20
SVMLE = 0 → 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 12.5
t(SVML) SVML on or off delay time µs
SVMLE = 0 → 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 100

Wake-Up From Low-Power Modes and Reset

Wake-up time from LPM2, PMMCOREV = SVSMLRRL = n fMCLK ≥ 4.0 MHz 3.5 7.5
tWAKE-UP-FAST LPM3, or LPM4 to active (where n = 0, 1, 2, or 3), 1.0 MHz < fMCLK µs
mode (1) SVSLFP = 1 4.5 9
< 4.0 MHz
Wake-up time from LPM2,
PMMCOREV = SVSMLRRL = n
tWAKE-UP-SLOW LPM3 or LPM4 to active 150 165 µs
(where n = 0, 1, 2, or 3), SVSLFP = 0
mode (2)
Wake-up time from LPM4.5 to
tWAKE-UP-LPM5 2 3 ms
active mode (3)
Wake-up time from RST or
tWAKE-UP-RESET 2 3 ms
BOR event to active mode (3)
(1) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVML in full
performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while
operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx
and MSP430x6xx Family User's Guide (SLAU208).
(2) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance
mode of the low side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current)
mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and
LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208).
(3) This value represents the time from the wakeup event to the reset vector execution.
Timer_A
Internal: SMCLK, ACLK,
fTA Timer_A input clock frequency External: TACLK, 1.8 V, 3 V 25 MHz
Duty cycle = 50% ± 10%
All capture inputs, minimum pulse
tTA,cap Timer_A capture timing 1.8 V, 3 V 20 ns
duration required for capture
Timer_B
fTB Timer_B input clock frequency External: TBCLK, 1.8 V, 3 V 25 MHz
All capture inputs, minimum pulse
tTB,cap Timer_B capture timing 1.8 V, 3 V 20 ns
duration required for capture

USCI (UART Mode) Recommended Operating Conditions

PARAMETER CONDITIONS VCC MIN TYP MAX UNIT
fUSCI USCI input clock frequency External: UCLK, fSYSTEM MHz
BITCLK clock frequency
fBITCLK 1 MHz
(equals baud rate in MBaud)
USCI (UART Mode)

2.2 V 50 600
tt UART receive deglitch time (1) ns
3V 50 600
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode) Recommended Operating Conditions

PARAMETER CONDITIONS VCC MIN TYP MAX UNIT
fUSCI USCI input clock frequency fSYSTEM MHz
USCI (SPI Master Mode)

(see Note (1), Figure 11 and Figure 12)
SMCLK, ACLK,
fUSCI USCI input clock frequency fSYSTEM MHz
1.8 V 55
PMMCOREV = 0 ns
3.0 V 38
tSU,MI SOMI input data setup time
2.4 V 30
PMMCOREV = 3 ns
3.0 V 25
1.8 V 0
PMMCOREV = 0 ns
3.0 V 0
tHD,MI SOMI input data hold time
2.4 V 0
PMMCOREV = 3 ns
3.0 V 0
UCLK edge to SIMO valid, 1.8 V 20
ns
CL = 20 pF, PMMCOREV = 0 3.0 V 18
(2)
tVALID,MO SIMO output data valid time
UCLK edge to SIMO valid, 2.4 V 16
ns
CL = 20 pF, PMMCOREV = 3 3.0 V 15
1.8 V -10
CL = 20 pF, PMMCOREV = 0 ns
3.0 V -8
tHD,MO SIMO output data hold time (3)
2.4 V -10
3.0 V -8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).

For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 11 and Figure 12.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in
Figure 11 and Figure 12.

1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI tLO/HI
tSU,MI
tHD,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 11. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI tLO/HI
tHD,MI
tSU,MI
SOMI
tHD,MO
tVALID,MO
SIMO
Figure 12. SPI Master Mode, CKPH = 1

USCI (SPI Slave Mode)

(see Note (1), Figure 13 and Figure 14)
1.8 V 11
PMMCOREV = 0 ns
3.0 V 8
tSTE,LEAD STE lead time, STE low to clock
2.4 V 7
PMMCOREV = 3 ns
3.0 V 6
1.8 V 3
PMMCOREV = 0 ns
3.0 V 3
tSTE,LAG STE lag time, Last clock to STE high
2.4 V 3
PMMCOREV = 3 ns
3.0 V 3
1.8 V 66
PMMCOREV = 0 ns
STE access time, STE low to SOMI data 3.0 V 50
tSTE,ACC
out 2.4 V 36
PMMCOREV = 3 ns
3.0 V 30
1.8 V 30
PMMCOREV = 0 ns
STE disable time, STE high to SOMI high 3.0 V 23
tSTE,DIS
impedance 2.4 V 16
PMMCOREV = 3 ns
3.0 V 13
1.8 V 5
PMMCOREV = 0 ns
3.0 V 5
tSU,SI SIMO input data setup time
2.4 V 2
PMMCOREV = 3 ns
3.0 V 2
1.8 V 5
PMMCOREV = 0 ns
3.0 V 5
tHD,SI SIMO input data hold time
2.4 V 5
PMMCOREV = 3 ns
3.0 V 5
UCLK edge to SOMI valid, 1.8 V 76
ns
CL = 20 pF, PMMCOREV = 0 3.0 V 60
tVALID,SO SOMI output data valid time (2)
UCLK edge to SOMI valid, 2.4 V 44
ns
CL = 20 pF, PMMCOREV = 3 3.0 V 40
1.8 V 18
(3)
3.0 V 12
tHD,SO SOMI output data hold time
2.4 V 10
3.0 V 8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).

For the master's parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 11 and Figure 12.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 11
and Figure 12.

tSTE,LEAD tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI tLO/HI tSU,SI

tHD,SI
SIMO
tHD,SO
tSTE,ACC tVALID,SO tSTE,DIS
SOMI
Figure 13. SPI Slave Mode, CKPH = 0
tSTE,LEAD tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI tLO/HI
tHD,SI
tSU,SI
SIMO
tHD,MO
tSTE,ACC tVALID,SO tSTE,DIS
SOMI
Figure 14. SPI Slave Mode, CKPH = 1

USCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 15)
Internal: SMCLK, ACLK
fUSCI USCI input clock frequency External: UCLK fSYSTEM MHz
fSCL SCL clock frequency 2.2 V, 3 V 0 400 kHz
fSCL ≤ 100 kHz 4.0
tHD,STA Hold time (repeated) START 2.2 V, 3 V µs
fSCL > 100 kHz 0.6
fSCL ≤ 100 kHz 4.7
tSU,STA Setup time for a repeated START 2.2 V, 3 V µs
fSCL > 100 kHz 0.6
tHD,DAT Data hold time 2.2 V, 3 V 0 ns
tSU,DAT Data setup time 2.2 V, 3 V 250 ns
fSCL ≤ 100 kHz 4.0
tSU,STO Setup time for STOP 2.2 V, 3 V µs
fSCL > 100 kHz 0.6
Pulse duration of spikes suppressed by input 2.2 V 50 600
tSP ns
filter 3V 50 600
tHD,STA tSU,STA tHD,STA tBUF
SDA
tLOW tHIGH tSP

SCL
tSU,DAT tSU,STO
tHD,DAT
Figure 15. I2C Mode Timing

12-Bit ADC, Power Supply and Input Range Conditions

AVCC and DVCC are connected together,
AVCC Analog supply voltage AVSS and DVSS are connected together, 2.2 3.6 V
V(AVSS) = V(DVSS) = 0 V
V(Ax) Analog input voltage range (2) All ADC12 analog input pins Ax 0 AVCC V
Operating supply current into 2.2 V 125 155
IADC12_A fADC12CLK = 5.0 MHz (4) µA
AVCC terminal (3) 3V 150 220
Only one terminal Ax can be selected at one
CI Input capacitance 2.2 V 20 25 pF
time
RI Input MUX ON resistance 0 V ≤ VAx ≤ AVCC 10 200 1900 Ω
(1) The leakage current is specified by the digital I/O input leakage.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the
reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling
capacitors are required. See REF, External Reference andREF, Built-In Reference.
(3) The internal reference supply current is not included in current consumption parameter IADC12_A.
(4) ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0
12-Bit ADC, Timing Parameters

For specified performance of ADC12 linearity
parameters using an external reference voltage or 0.45 4.8 5.0
AVCC as reference (1)
fADC12CLK ADC conversion clock For specified performance of ADC12 linearity 2.2 V, 3 V MHz
0.45 2.4 4.0
parameters using the internal reference (2)
For specified performance of ADC12 linearity
0.45 2.4 2.7
parameters using the internal reference (3)
Internal ADC12
fADC12OSC ADC12DIV = 0, fADC12CLK = fADC12OSC 2.2 V, 3 V 4.2 4.8 5.4 MHz
oscillator (4)
REFON = 0, internal oscillator,
2.2 V, 3 V 2.4 3.1
ADC12OSC used for ADC conversion clock
tCONVERT Conversion time µs
External fADC12CLK from ACLK, MCLK, or SMCLK, (5)
ADC12SSEL ≠ 0
RS = 400 Ω, RI = 1000 Ω, CI = 20 pF,
tSample Sampling time 2.2 V, 3 V 1000 ns
t = [RS + RI] × CI (6)
(1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0,
SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the
specified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5.0 MHz.
(2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1
(3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when
using the ADC12OSC divided by 2.
(4) The ADC12OSC is sourced directly from MODOSC inside the UCS.
(5) 13 × ADC12DIV × 1/fADC12CLK
(6) Approximately ten Tau (t) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance

12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference
Voltage
1.4 V ≤ dVREF ≤ 1.6 V (2) ±2.0
EI Integral linearity error (1) 2.2 V, 3 V LSB
1.6 V < dVREF (2) ±1.7
ED Differential linearity error (1) (2)
2.2 V, 3 V ±1.0 LSB
dVREF ≤ 2.2 V (2) 2.2 V, 3 V ±1.0 ±2.0
EO Offset error (3) LSB
dVREF > 2.2 V (2) 2.2 V, 3 V ±1.0 ±2.0
EG Gain error (3) (2)
2.2 V, 3 V ±1.0 ±2.0 LSB
dVREF ≤ 2.2 V (2) 2.2 V, 3 V ±1.4 ±3.5
ET Total unadjusted error LSB
dVREF > 2.2 V (2) 2.2 V, 3 V ±1.4 ±3.5
(1) Parameters are derived using the histogram method.

(2) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+ - VR-, VR+ < AVCC, VR- > AVSS.
Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω, and two decoupling capacitors,
10 µF and 100 nF, should be connected to VREF+ and VREF- to decouple the dynamic current. Also see the MSP430x5xx and
MSP430x6xx Family User's Guide (SLAU208).
(3) Parameters are derived using a best fit curve.
12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage

PARAMETER TEST CONDITIONS (1) VCC MIN TYP MAX UNIT
Integral linearity ADC12SR = 0, REFOUT = 1 fADC12CLK = 4.0 MHz ±1.7
EI 2.2 V, 3 V LSB
error (2) ADC12SR = 0, REFOUT = 0 fADC12CLK = 2.7 MHz ±2.5
ADC12SR = 0, REFOUT = 1 fADC12CLK = 4.0 MHz -1.0 +2.0
Differential
ED ADC12SR = 0, REFOUT = 1 fADC12CLK = 2.7 MHz 2.2 V, 3 V -1.0 +1.5 LSB
linearity error (2)
ADC12SR = 0, REFOUT = 0 fADC12CLK = 2.7 MHz -1.0 +2.5
ADC12SR = 0, REFOUT = 1 fADC12CLK = 4.0 MHz ±1.0 ±2.0
EO Offset error (3) 2.2 V, 3 V LSB
ADC12SR = 0, REFOUT = 0 fADC12CLK = 2.7 MHz ±1.0 ±2.0
ADC12SR = 0, REFOUT = 1 fADC12CLK = 4.0 MHz ±1.0 ±2.0 LSB
EG Gain error (3) 2.2 V, 3 V
ADC12SR = 0, REFOUT = 0 fADC12CLK = 2.7 MHz ±1.5% (4) VREF
Total unadjusted ADC12SR = 0, REFOUT = 1 fADC12CLK = 4.0 MHz ±1.4 ±3.5 LSB
ET 2.2 V, 3 V
error ADC12SR = 0, REFOUT = 0 fADC12CLK = 2.7 MHz ±1.5% (4)
VREF
(1) The internal reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 1. dVREF = VR+ - VR-.
(2) Parameters are derived using the histogram method.
(3) Parameters are derived using a best fit curve.
(4) The gain error and total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In this
mode the reference voltage used by the ADC12_A is not available on a pin.

12-Bit ADC, Temperature Sensor and Built-In VMID (1)

(2) ADC12ON = 1, INCH = 0Ah, 2.2 V 680

VSENSOR See mV
TA = 0°C 3V 680
2.2 V 2.25
TCSENSOR ADC12ON = 1, INCH = 0Ah mV/°C
3V 2.25
Sample time required if ADC12ON = 1, INCH = 0Ah, 2.2 V 100
tSENSOR(sample) µs
channel 10 is selected (3) Error of conversion result ≤ 1 LSB 3V 100
AVCC divider at channel 11,
ADC12ON = 1, INCH = 0Bh 0.48 0.5 0.52 VAVCC
VAVCC factor
VMID
2.2 V 1.06 1.1 1.14
AVCC divider at channel 11 ADC12ON = 1, INCH = 0Bh V
3V 1.44 1.5 1.56
Sample time required if ADC12ON = 1, INCH = 0Bh,
tVMID(sample) 2.2 V, 3 V 1000 ns
channel 11 is selected (4) Error of conversion result ≤ 1 LSB
(1) The temperature sensor is provided by the REF module. See the REF module parametric, IREF+, regarding the current consumption of
the temperature sensor.
(2) The temperature sensor offset can be significant. A single-point calibration is recommended to minimize the offset error of the built-in
temperature sensor. The TLV structure contains calibration values for 30°C ± 3°C and 85°C ± 3°C for each of the available reference
voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature,°C) + VSENSOR, where TCSENSOR and
VSENSOR can be computed from the calibration values for higher accuracy. See also the MSP430x5xx and MSP430x6xx Family User's
Guide (SLAU208).
(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
(4) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
1000
Typical Temperature Sensor Voltage - mV
950
900
850
800
750
700
650
600
550
500
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Ambient Temperature - ˚C
Figure 16. Typical Temperature Sensor Voltage

REF, External Reference

Positive external reference (2)
VeREF+ VeREF+ > VREF– and VeREF– 1.4 AVCC V
voltage input
Negative external reference (3)
VREF–, VeREF– VeREF+ > VREF– and VeREF– 0 1.2 V
voltage input
(VeREF+ – Differential external reference (4)
VeREF+ > VREF– and VeREF– 1.4 AVCC V
VREF- or VeREF-) voltage input
1.4 V ≤ VeREF+ ≤ VAVCC,
VeREF– = 0 V, fADC12CLK = 5 MHz,
2.2 V, 3 V -26 26 µA
ADC12SHTx = 1h,
IVeREF+, IVREF-, Conversion rate 200 ksps
Static input current
VeREF- 1.4 V ≤ VeREF+ ≤ VAVCC,
VeREF– = 0 V, fADC12CLK = 5 MHz,
2.2 V, 3 V -1 1 µA
ADC12SHTx = 8h,
Conversion rate 20 ksps
Capacitance at VVREF+, VVREF- (5)
CVREF+, CVREF- 10 µF
terminal
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance (Ci) is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external
reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208).
REF, Built-In Reference

REFVSEL = {2} for 2.5 V,
3V 2.4625 2.50 2.5375
REFON = REFOUT = 1, IVREF+ = 0 A
Positive built-in reference REFVSEL = {1} for 2.0 V,
VREF+ 3V 1.9503 1.98 2.0097 V
voltage output REFON = REFOUT = 1, IVREF+ = 0 A
REFVSEL = {0} for 1.5 V,
2.2 V, 3 V 1.4677 1.49 1.5124
REFON = REFOUT = 1, IVREF+ = 0 A
REFVSEL = {0} for 1.5 V 2.2
AVCC minimum voltage,
AVCC(min) Positive built-in reference REFVSEL = {1} for 2.0 V 2.3 V
active
REFVSEL = {2} for 2.5 V 2.8
ADC12SR = 1 (4), REFON = 1, REFOUT = 0,
3V 70 100 µA
REFBURST = 0
(4)
ADC12SR = 1 , REFON = 1, REFOUT = 1,
3V 0.45 0.75 mA
Operating supply current into REFBURST = 0
IREF+
AVCC terminal (2) (3) ADC12SR = 0 (4), REFON = 1, REFOUT = 0,
3V 210 310 µA
REFBURST = 0
ADC12SR = 0 (4), REFON = 1, REFOUT = 1,
3V 0.95 1.7 mA
REFBURST = 0
(1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one
smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal, as well as,
used as the reference for the conversion and utilizes the larger buffer. When REFOUT = 0, the reference is only used as the reference
for the conversion and utilizes the smaller buffer.
(2) The internal reference current is supplied by terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current
contribution of the larger buffer without external load.
(3) The temperature sensor is provided by the REF module. Its current is supplied via terminal AVCC and is equivalent to IREF+ with
REFON =1 and REFOUT = 0.
(4) For devices without the ADC12, the parametrics with ADC12SR = 0 are applicable.
REF, Built-In Reference (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
REFVSEL = (0, 1, 2)
Load-current regulation, IVREF+ = +10 µA, –1000 µA
IL(VREF+) 2500 µV/mA
VREF+ terminal (5) AVCC = AVCC (min) for each reference level,
REFVSEL = (0, 1, 2), REFON = REFOUT = 1
Capacitance at VREF+
CVREF+ REFON = REFOUT = 1 20 100 pF
terminal
IVREF+ = 0 A,
Temperature coefficient of ppm/
TCREF+ REFVSEL = (0, 1, 2), REFON = 1, 30 50
built-in reference (6) °C
REFOUT = 0 or 1
AVCC = AVCC (min) - AVCC(max),
Power supply rejection ratio TA = 25°C,
PSRR_DC 120 300 µV/V
(DC) REFVSEL = (0, 1, 2), REFON = 1,
REFOUT = 0 or 1
TA = 25°C,
Power supply rejection ratio
PSRR_AC f = 1 kHz, ΔVpp = 100 mV, 6.4 mV/V
(AC)
REFVSEL = (0, 1, 2), REFON = 1,
REFOUT = 0 or 1
REFVSEL = (0, 1, 2), REFOUT = 0, 75
REFON = 0 → 1
Settling time of reference
tSETTLE AVCC = AVCC (min) - AVCC(max), µs
voltage (7)
CVREF = CVREF(max),
75
REFVSEL = (0, 1, 2), REFOUT = 1,
REFON = 0 → 1
(5) Contribution only due to the reference and buffer including package. This does not include resistance due to PCB trace.
(6) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C – (–40°C)).
(7) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load when REFOUT = 1.

Comparator_B
VCC Supply voltage 1.8 3.6 V
1.8 V 40
CBPWRMD = 00 2.2 V 30 50
Comparator operating supply
IAVCC_COMP current into AVCC, excludes 3.0 V 40 65 µA
reference resistor ladder
CBPWRMD = 01 2.2 V, 3 V 10 30
CBPWRMD = 10 2.2 V, 3 V 0.1 0.5
Quiescent current of local
CBREFACC = 1,
IAVCC_REF reference voltage amplifier into 22 µA
CBREFLx = 01
AVCC
VIC Common mode input range 0 VCC-1 V
CBPWRMD = 00 -20 20 mV
VOFFSET Input offset voltage
CBPWRMD = 01, 10 -10 10 mV
CIN Input capacitance 5 pF
ON - switch closed 3 4 kΩ
RSIN Series input resistance
OFF - switch open 30 MΩ
CBPWRMD = 00, CBF = 0 450 ns
Propagation delay, response
tPD CBPWRMD = 01, CBF = 0 600 ns
time
CBPWRMD = 10, CBF = 0 50 µs
CBPWRMD = 00, CBON = 1,
0.35 0.6 1.0 µs
CBF = 1, CBFDLY = 00
0.6 1.0 1.8 µs
Propagation delay with filter CBF = 1, CBFDLY = 01
tPD,filter
active CBPWRMD = 00, CBON = 1,
1.0 1.8 3.4 µs
1.8 3.4 6.5 µs
Comparator enable time, CBON = 0 to CBON = 1,
tEN_CMP 1 2 µs
settling time CBPWRMD = 00, 01, 10
tEN_REF Resistor reference enable time CBON = 0 to CBON = 1 1 1.5 µs
VIN × VIN × VIN ×
Reference voltage for a given VIN = reference into resistor
VCB_REF (n+0.5) (n+1) (n+1.5) V
tap ladder (n = 0 to 31)
/ 32 / 32 / 32
Ports PU.0 and PU.1

VUSB = 3.3 V ± 10%, IOH = -25 mA,
VOH High-level output voltage 2.4 V
See Figure 18 for typical characteristics
VUSB = 3.3 V ± 10%, IOL = 25 mA,
VOL Low-level output voltage 0.4 V
VUSB = 3.3 V ± 10%,
VIH High-level input voltage 2.0 V
VUSB = 3.3 V ± 10%,
VIL Low-level input voltage 0.8 V

TYPICAL LOW-LEVEL OUTPUT CURRENT

vs
LOW-LEVEL OUTPUT VOLTAGE
90
VCC = 3.0 V VCC = 3.0 V
80 TA = 25 ºC TA = 85 ºC
IOL - Typical Low-Level Output Current - mA

70 VCC = 1.8 V
TA = 25 ºC
60
50
40 VCC = 1.8 V
TA = 85 ºC
30
20
10
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
VOL - Low-Level Output Voltage - V
Figure 17. Ports PU.0, PU.1 Typical Low-Level Output Characteristics
TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs
HIGH-LEVEL OUTPUT VOLTAGE
0
-10
IOH - Typical High-Level Output Current - mA
-20
-30
VCC = 1.8 V
-40 TA = 85 ºC
-50
VCC = 3.0 V
-60 TA = 85 ºC
VCC = 1.8 V
-70 TA = 25 ºC VCC = 3.0 V
TA = 25 ºC
-80
-90
0.5 1 1.5 2 2.5 3
VOH - High-Level Output Voltage - V
Figure 18. Ports PU.0, PU.1 Typical High-Level Output Characteristics
TYPICAL PU.0, PU.1 INPUT THRESHOLD
2.0
T A = 25 !C, 85 !C
1.8
1.6 VIT+ , postive-going input threshold
1.4
Input Threshold - V
1.2
VIT- , negative-going input threshold

1.0
0.8
0.6
0.4
0.2
0.0
1.8 2.2 2.6 3 3.4
VUSB Supply Voltage, V USB - V
Figure 19. Ports PU.0, PU.1 Typical Input Threshold Characteristics

USB Output Ports DP and DM

VOH D+, D- single ended USB 2.0 load conditions 2.8 3.6 V
VOL D+, D- single ended USB 2.0 load conditions 0 0.3 V
Z(DRV) D+, D- impedance Including external series resistor of 27 Ω 28 44 Ω
Full speed, differential, CL = 50 pF,
tRISE Rise time 4 20 ns
10%/90%, Rpu on D+
Full speed, differential, CL = 50 pF,
tFALL Fall time 4 20 ns
10%/90%, Rpu on D+
USB Input Ports DP and DM

V(CM) Differential input common mode range 0.8 2.5 V
Z(IN) Input impedance 300 kΩ
VCRS Crossover voltage 1.3 2.0 V
VIL Static SE input logic low level 0.8 V
VIH Static SE input logic high level 2.0 V
VDI Differential input voltage 0.2 V

USB-PWR (USB Power System)

VLAUNCH VBUS detection threshold 3.75 V
VBUS USB bus voltage Normal operation 3.76 5.5 V
VUSB USB LDO output voltage 3.003 3.3 3.597 V
V18 Internal USB voltage (1) 1.8 V
Maximum external current from VUSB
IUSB_EXT USB LDO is on 12 mA
terminal (2)
(3)
IDET USB LDO current overload detection 60 100 mA
USB LDO is on,
ISUSPEND Operating supply current into VBUS terminal (4) 250 µA
USB PLL disabled
USB LDO is on,
Operating supply current into VBUS terminal, USB 1.8-V LDO is disabled,
IUSB_LDO 1.8 V, 3 V 60 µA
represents the current of the 3.3-V LDO only VBUS = 5.0 V,
USBDETEN = 0 or 1
USB LDO is disabled,
Operating supply current into VBUS terminal,
IVBUS_DETE USB 1.8-V LDO is disabled,
represents the current of the VBUS detection 1.8 V, 3 V 30 µA
CT VBUS > VLAUNCH,
logic
USBDETEN = 1
CBUS VBUS terminal recommended capacitance 4.7 µF
CUSB VUSB terminal recommended capacitance 220 nF
C18 V18 terminal recommended capacitance 220 nF
Within 2%,
tENABLE Settling time VUSB and V18 2 ms
recommended capacitances
RPUR Pullup resistance of PUR terminal (5) 70 110 150 Ω
(1) This voltage is for internal uses only. No external DC loading should be applied.
(2) This represents additional current that can be supplied to the application from the VUSB terminal beyond the needs of the USB
operation.
(3) A current overload will be detected when the total current supplied from the USB LDO, including IUSB_EXT, exceeds this value.
(4) Does not include current contribution of Rpu and Rpd as outlined in the USB specification.
(5) This value, in series with an external resistor between PUR and D+, produces the Rpu as outlined in the USB specification.
USB-PLL (USB Phase Locked Loop)

IPLL Operating supply current 7 mA
fPLL PLL frequency 48 MHz
fUPD PLL reference frequency 1.5 3 MHz
tLOCK PLL lock time 2 ms
tJitter PLL jitter 1000 ps

Flash Memory
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
DVCC(PGM,ERASE) Program and erase supply voltage 1.8 3.6 V
IPGM Average supply current from DVCC during program (1) 3 5 mA
IERASE Average supply current from DVCC during erase (1) 6 11 mA
Average supply current from DVCC during mass erase or bank
IMERASE, IBANK 6 11 mA
erase (1)
(2)
tCPT Cumulative program time See 16 ms
4 5
Program and erase endurance 10 10 cycles
tRetention Data retention duration TJ = 25°C 100 years
(3)
tWord Word or byte program time See 64 85 µs
(3)
tBlock, 0 Block program time for first byte or word See 49 65 µs
Block program time for each additional byte or word, except for last (3)
tBlock, 1–(N–1) See 37 49 µs
byte or word
(3)
tBlock, N Block program time for last byte or word See 55 73 µs
Erase time for segment, mass erase, and bank erase when (3)
tErase See 23 32 ms
available.
MCLK frequency in marginal read mode
fMCLK,MGR 0 1 MHz
(FCTL4.MGR0 = 1 or FCTL4. MGR1 = 1)
(1) Default clock system frequency of MCLK = 1 MHz, ACLK = 32768 Hz, SMCLK = 1 MHz. No peripherals are enabled or active.
(2) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word- or byte-write and block-write modes.
(3) These values are hardwired into the flash controller's state machine.
JTAG and Spy-Bi-Wire Interface

TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz
tSBW,Low Spy-Bi-Wire low clock pulse duration 2.2 V, 3 V 0.025 15 µs
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
tSBW, 2.2 V, 3 V 1 µs
En edge) (1)
tSBW,Rst Spy-Bi-Wire return to normal operation time 15 100 µs
2.2 V 0 5 MHz
fTCK TCK input frequency, 4-wire JTAG (2)
3V 0 10 MHz
Rinternal Internal pulldown resistance on TEST 2.2 V, 3 V 45 60 80 kΩ
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.

INPUT/OUTPUT SCHEMATICS
Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
Pad Logic
P1REN.x
DVSS 0
DVCC 1 1
P1DIR.x 0
Direction
From module 1 0: Input
1: Output
P1OUT.x 0
From module 1
P1.0/TA0CLK/ACLK
P1DS.x
P1SEL.x P1.1/TA0.0
0: Low drive
P1.2/TA0.1
1: High drive
P1.3/TA0.2
P1IN.x P1.4/TA0.3
P1.5/TA0.4
P1.6/TA1CLK/CBOUT
EN
P1.7/TA1.0
To module D
P1IE.x
EN
P1IRQ.x
Q
P1IFG.x Set
P1SEL.x Interrupt
Edge
P1IES.x Select

Table 49. Port P1 (P1.0 to P1.7) Pin Functions

CONTROL BITS/SIGNALS
PIN NAME (P1.x) x FUNCTION
P1DIR.x P1SEL.x
P1.0/TA0CLK/ACLK 0 P1.0 (I/O) I: 0; O: 1 0
TA0CLK 0 1
ACLK 1 1
P1.1/TA0.0 1 P1.1 (I/O) I: 0; O: 1 0
TA0.CCI0A 0 1
TA0.0 1 1
P1.2/TA0.1 2 P1.2 (I/O) I: 0; O: 1 0
TA0.CCI1A 0 1
TA0.1 1 1
P1.3/TA0.2 3 P1.3 (I/O) I: 0; O: 1 0
TA0.CCI2A 0 1
TA0.2 1 1
P1.4/TA0.3 4 P1.4 (I/O) I: 0; O: 1 0
TA0.CCI3A 0 1
TA0.3 1 1
P1.5/TA0.4 5 P1.5 (I/O) I: 0; O: 1 0
TA0.CCI4A 0 1
TA0.4 1 1
P1.6/TA1CLK/CBOUT 6 P1.6 (I/O) I: 0; O: 1 0
TA1CLK 0 1
CBOUT comparator B 1 1
P1.7/TA1.0 7 P1.7 (I/O) I: 0; O: 1 0
TA1.CCI0A 0 1
TA1.0 1 1

Pad Logic
P2REN.x
DVSS 0
DVCC 1 1
P2DIR.x 0
Direction
1: Output
P2OUT.x 0
From module 1
P2.0/TA1.1
P2DS.x
P2SEL.x P2.1/TA1.2
0: Low drive
P2.2/TA2CLK/SMCLK
1: High drive
P2.3/TA2.0
P2IN.x P2.4/TA2.1
P2.5/TA2.2
P2.6/RTCCLK/DMAE0
EN
P2.7/UB0STE/UCA0CLK
To module D
P2IE.x
EN
To module
Q
P2IFG.x Set
P2SEL.x Interrupt
Edge
P2IES.x Select


CONTROL BITS/SIGNALS (1)
P2DIR.x P2SEL.x
P2.0/TA1.1 0 P2.0 (I/O) I: 0; O: 1 0
TA1.CCI1A 0 1
TA1.1 1 1
P2.1/TA1.2 1 P2.1 (I/O) I: 0; O: 1 0
TA1.CCI2A 0 1
TA1.2 1 1
P2.2/TA2CLK/SMCLK 2 P2.2 (I/O) I: 0; O: 1 0
TA2CLK 0 1
SMCLK 1 1
P2.3/TA2.0 3 P2.3 (I/O) I: 0; O: 1 0
TA2.CCI0A 0 1
TA2.0 1 1
P2.4/TA2.1 4 P2.4 (I/O) I: 0; O: 1 0
TA2.CCI1A 0 1
TA2.1 1 1
P2.5/TA2.2 5 P2.5 (I/O) I: 0; O: 1 0
TA2.CCI2A 0 1
TA2.2 1 1
P2.6/RTCCLK/DMAE0 6 P2.6 (I/O) I: 0; O: 1 0
DMAE0 0 1
RTCCLK 1 1
P2.7/UCB0STE/UCA0CLK 7 P2.7 (I/O) I: 0; O: 1 0
UCB0STE/UCA0CLK (2) (3)
X 1
(1) X = Don't care

(2) The pin direction is controlled by the USCI module.
(3) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.

Pad Logic
P3REN.x
DVSS 0
DVCC 1 1
P3DIR.x 0
Direction
1: Output
P3OUT.x 0
From module 1
P3DS.x
P3SEL.x P3.1/UCB0SOMI/UCB0SCL
0: Low drive
1: High drive
P3IN.x P3.4/UCA0RXD/UCA0SOMI
P3.5/TB0.5
P3.6/TB0.6
EN
P3.7/TB0OUTH/SVMOUT
To module D

P3DIR.x P3SEL.x
P3.0/UCB0SIMO/UCB0SDA 0 P3.0 (I/O) I: 0; O: 1 0
(2) (3)
UCB0SIMO/UCB0SDA X 1
P3.1/UCB0SOMI/UCB0SCL 1 P3.1 (I/O) I: 0; O: 1 0
UCB0SOMI/UCB0SCL (2) (3)
X 1
P3.2/UCB0CLK/UCA0STE 2 P3.2 (I/O) I: 0; O: 1 0
(2) (4)
UCB0CLK/UCA0STE X 1
P3.3/UCA0TXD/UCA0SIMO 3 P3.3 (I/O) I: 0; O: 1 0
UCA0TXD/UCA0SIMO (2) X 1
P3.4/UCA0RXD/UCA0SOMI 4 P3.4 (I/O) I: 0; O: 1 0
UCA0RXD/UCA0SOMI (2) X 1
P3.5/TB0.5 (5) 5 P3.5 (I/O) I: 0; O: 1 0
TB0.CCI5A 0 1
TB0.5 1 1
P3.6/TB0.6 (5) 6 P3.6 (I/O) I: 0; O: 1 0
TB0.CCI6A 0 1
TB0.6 1 1
P3.7/TB0OUTH/SVMOUT (5) 7 P3.7 (I/O) I: 0; O: 1 0
TB0OUTH 0 1
SVMOUT 1 1
(1) X = Don't care

(2) The pin direction is controlled by the USCI module.
(3) If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
(4) UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI A0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
(5) F5529, F5527, F5525, F5521, F5519, F5517, F5515 devices only.

Pad Logic
P4REN.x
DVSS 0
DVCC 1 1
P4DIR.x 0
Direction
from Port Mapping Control 1 0: Input
1: Output
P4OUT.x 0
from Port Mapping Control 1

P4.0/P4MAP0
P4DS.x
P4SEL.x P4.1/P4MAP1
0: Low drive
P4.2/P4MAP2
1: High drive
P4.3/P4MAP3
P4IN.x P4.4/P4MAP4
P4.5/P4MAP5
P4.6/P4MAP6
EN
P4.7/P4MAP7
to Port Mapping Control D

P4DIR.x (1) P4SEL.x P4MAPx
P4.0/P4MAP0 0 P4.0 (I/O) I: 0; O: 1 0 X
Mapped secondary digital function X 1 ≤ 30
P4.1/P4MAP1 1 P4.1 (I/O) I: 0; O: 1 0 X
P4.2/P4MAP2 2 P4.2 (I/O) I: 0; O: 1 0 X
P4.3/P4MAP3 3 P4.3 (I/O) I: 0; O: 1 0 X
P4.4/P4MAP4 4 P4.4 (I/O) I: 0; O: 1 0 X
P4.5/P4MAP5 5 P4.5 (I/O) I: 0; O: 1 0 X
P4.6/P4MAP6 6 P4.6 (I/O) I: 0; O: 1 0 X
P4.7/P4MAP7 7 P4.7 (I/O) I: 0; O: 1 0 X
(1) The direction of some mapped secondary functions are controlled directly by the module. See Table 10 for specific direction control
information of mapped secondary functions.

Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
Pad Logic
to/from Reference
(n/a MSP430F551x)
(n/a MSPF430F551x)
to ADC12
(n/a MSPF430F551x)
INCHx = x
P5REN.x
DVSS 0
DVCC 1 1
P5DIR.x 0
P5OUT.x 0
From module 1
P5.0/(A8/VREF+/VeREF+)
P5DS.x
P5SEL.x P5.1/(A9/VREF–/VeREF–)
0: Low drive
1: High drive
P5IN.x
EN Bus
Keeper
To module D
Table 53. Port P5 (P5.0 and P5.1) Pin Functions

P5DIR.x P5SEL.x REFOUT
P5.0/A8/VREF+/VeREF+ (2) 0 P5.0 (I/O) (3) I: 0; O: 1 0 X
A8/VeREF+ (4) X 1 0
(5)
A8/VREF+ X 1 1
P5.1/A9/VREF–/VeREF– (6) 1 P5.1 (I/O) (3) I: 0; O: 1 0 X
A9/VeREF– (7) X 1 0
A9/VREF– (8) X 1 1
(1) X = Don't care

(2) VREF+/VeREF+ available on MSP430F552x devices only.
(3) Default condition
(4) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A when available. Channel A8,
when selected with the INCHx bits, is connected to the VREF+/VeREF+ pin.
analog signals. The VREF+ reference is available at the pin. Channel A8, when selected with the INCHx bits, is connected to the
VREF+/VeREF+ pin.
(6) VREF-/VeREF- available on MSP430F552x devices only.
analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A when available. Channel A9,
when selected with the INCHx bits, is connected to the VREF-/VeREF- pin.
analog signals. The VREF– reference is available at the pin. Channel A9, when selected with the INCHx bits, is connected to the VREF-
/VeREF- pin.

Port P5, P5.2, Input/Output With Schmitt Trigger
Pad Logic
To XT2
P5REN.2
DVSS 0
DVCC 1 1
P5DIR.2 0
P5OUT.2 0
Module X OUT 1
P5.2/XT2IN
P5DS.2
P5SEL.2 0: Low drive
1: High drive
P5IN.2
EN Bus
Keeper
Module X IN D

Port P5, P5.3, Input/Output With Schmitt Trigger
Pad Logic
To XT2
P5REN.3
DVSS 0
DVCC 1 1
P5DIR.3 0
P5OUT.3 0
Module X OUT 1
P5.3/XT2OUT
P5DS.3
1: High drive
P5IN.3
EN Bus
Keeper
Module X IN D
Table 54. Port P5 (P5.2, P5.3) Pin Functions

P5DIR.x P5SEL.2 P5SEL.3 XT2BYPASS
P5.2/XT2IN 2 P5.2 (I/O) I: 0; O: 1 0 X X
XT2IN crystal mode (2) X 1 X 0
XT2IN bypass mode (2) X 1 X 1
P5.3/XT2OUT 3 P5.3 (I/O) I: 0; O: 1 0 X X
XT2OUT crystal mode (3) X 1 X 0
P5.3 (I/O) (3) X 1 X 1
(1) X = Don't care

(2) Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal
mode or bypass mode.
(3) Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as
general-purpose I/O.

Port P5, P5.4 and P5.5 Input/Output With Schmitt Trigger
Pad Logic
to XT1
P5REN.4
DVSS 0
DVCC 1 1
P5DIR.4 0
P5OUT.4 0
Module X OUT 1
P5.4/XIN
P5DS.4
1: High drive
P5IN.4
EN Bus
Keeper
Module X IN D

Pad Logic
to XT1
P5REN.5
DVSS 0
DVCC 1 1
P5DIR.5 0
P5OUT.5 0
Module X OUT 1
P5.5/XOUT
P5SEL.5 P5DS.5
0: Low drive
XT1BYPASS 1: High drive
P5IN.5
EN Bus
Keeper
Module X IN D
Table 55. Port P5 (P5.4 and P5.5) Pin Functions

P5DIR.x P5SEL.4 P5SEL.5 XT1BYPASS
P5.4/XIN 4 P5.4 (I/O) I: 0; O: 1 0 X X
(2)
XIN crystal mode X 1 X 0
XIN bypass mode (2) X 1 X 1
P5.5/XOUT 5 P5.5 (I/O) I: 0; O: 1 0 X X
XOUT crystal mode (3) X 1 X 0
P5.5 (I/O) (3) X 1 X 1
(1) X = Don't care

(2) Setting P5SEL.4 causes the general-purpose I/O to be disabled. Pending the setting of XT1BYPASS, P5.4 is configured for crystal
mode or bypass mode.
(3) Setting P5SEL.4 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.5 can be used as
general-purpose I/O.

Pad Logic
P5REN.x
DVSS 0
DVCC 1 1
P5DIR.x 0
Direction
From Module 1 0: Input
1: Output
P5OUT.x 0
P5DS.x
P5SEL.x P5.6/TB0.0
0: Low drive
P5.7/TB0.1
1: High drive
P5IN.x
EN
To module D

P5DIR.x P5SEL.x
(1)
P5.6/TB0.0 6 P5.6 (I/O) I: 0; O: 1 0
TB0.CCI0A 0 1
TB0.0 1 1
(1)
P5.7/TB0.1 7 TB0.CCI1A 0 1
TB0.1 1 1
(1) F5529, F5527, F5525, F5521, F5519, F5517, F5515 devices only.

Pad Logic
to ADC12
(n/a MSPF430F551x)
INCHx = x
(n/a MSPF430F551x)
to Comparator_B
from Comparator_B
CBPD.x
P6REN.x
DVSS 0
DVCC 1 1
P6DIR.x 0
Direction
1 0: Input
1: Output
P6OUT.x 0
From module 1
P6.0/CB0/(A0)
P6DS.x
P6SEL.x P6.1/CB1/(A1)
0: Low drive
P6.2/CB2/(A2)
1: High drive
P6.3/CB3/(A3)
P6IN.x P6.4/CB4/(A4)
P6.5/CB5/(A5)
EN Bus P6.6/CB6/(A6)
Keeper P6.7/CB7/(A7)
To module D


P6DIR.x P6SEL.x CBPD
P6.0/CB0/(A0) 0 P6.0 (I/O) I: 0; O: 1 0 0
A0 (only MSP430F552x) X 1 X
CB0 (1) X X 1
P6.1/CB1/(A1) 1 P6.1 (I/O) I: 0; O: 1 0 0
CB1 (1) X X 1
P6.2/CB2/(A2) 2 P6.2 (I/O) I: 0; O: 1 0 0
CB2 (1) X X 1
P6.3/CB3/(A3) 3 P6.3 (I/O) I: 0; O: 1 0 0
CB3 (1) X X 1
P6.4/CB4/(A4) 4 P6.4 (I/O) I: 0; O: 1 0 0
CB4 (1) X X 1
P6.5/CB5/(A5) 5 P6.5 (I/O) I: 0; O: 1 0 0
CB5 (1) X X 1
P6.6/CB6/(A6) 6 P6.6 (I/O) I: 0; O: 1 0 0
CB6 (1) X X 1
P6.7/CB7/(A7) 7 P6.7 (I/O) I: 0; O: 1 0 0
CB7 (1) X X 1
(1) Setting the CBPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input
buffer for that pin, regardless of the state of the associated CBPD.x bit.

Pad Logic
to ADC12
(n/a MSPF430F551x)
INCHx = x
(n/a MSPF430F551x)
to Comparator_B
from Comparator_B
CBPD.x
P7REN.x
DVSS 0
DVCC 1 1
P7DIR.x 0
Direction
1 0: Input
1: Output
P7OUT.x 0
From module 1
P7.0/CB8/(A12)
P7DS.x
P7SEL.x P7.1/CB9/(A13)
0: Low drive
P7.2/CB10/(A14)
1: High drive
P7.3/CB11/(A15)
P7IN.x
EN Bus
Keeper
To module D


P7DIR.x P7SEL.x CBPD
(1)
P7.0/CB8/(A12) 0 P7.0 (I/O) I: 0; O: 1 0 0
(2)
A12 X 1 X
CB8 (3) (1)
X X 1
P7.1/CB9/(A13) 1 P7.1 (I/O) (1) I: 0; O: 1 0 0
(2)
A13 X 1 X
CB9 (3) (1)
X X 1
P7.2/CB10/(A14) 2 P7.2 (I/O) (1) I: 0; O: 1 0 0
(2)
A14 X 1 X
CB10 (3) (1)
X X 1
P7.3/CB11/(A15) 3 P7.3 (I/O) (1) I: 0; O: 1 0 0
(2)
A15 X 1 X
CB11 (3) (1)
X X 1
(1) F5529, F5527, F5525, F5521, F5519, F5517, F5515 devices only
(2) F5529, F5527, F5525, F5521 devices only
(3) Setting the CBPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CBx input pin to the comparator multiplexer with the CBx bits automatically disables output driver and input
buffer for that pin, regardless of the state of the associated CBPD.x bit.

Pad Logic
P7REN.x
DVSS 0
DVCC 1 1
P7DIR.x 0
Direction
1: Output
P7OUT.x 0
P7DS.x
P7SEL.x P7.4/TB0.2
0: Low drive
P7.5/TB0.3
1: High drive
P7.6/TB0.4
P7IN.x P7.7/TB0CLK/MCLK
EN
To module D

P7DIR.x P7SEL.x
(1)
P7.4/TB0.2 4 P7.4 (I/O) I: 0; O: 1 0
TB0.CCI2A 0 1
TB0.2 1 1
(1)
P7.5/TB0.3 5 P7.5 (I/O) I: 0; O: 1 0
TB0.CCI3A 0 1
TB0.3 1 1
P7.6/TB0.4 (1) 6 P7.6 (I/O) I: 0; O: 1 0
TB0.CCI4A 0 1
TB0.4 1 1
P7.7/TB0CLK/MCLK (1) 7 P7.7 (I/O) I: 0; O: 1 0
TB0CLK 0 1
MCLK 1 1

Pad Logic
P8REN.x
DVSS 0
DVCC 1 1
P8DIR.x 0
Direction
from Port Mapping Control 1 0: Input
1: Output
P8OUT.x 0
from Port Mapping Control 1

P8.0
P8DS.x
P8SEL.x P8.1
0: Low drive
P8.2
1: High drive
P8IN.x
EN
to Port Mapping Control D

P8DIR.x P8SEL.x
P8.0 (1) 0 P8.0(I/O) I: 0; O: 1 0
P8.1 (1) 1 P8.1(I/O) I: 0; O: 1 0
P8.2 (1) 2 P8.2(I/O) I: 0; O: 1 0

Port PU.0/DP, PU.1/DM, PUR USB Ports

PUSEL VUSB VSSU
PUOPE 0 Pad Logic

USB output enable 1
PUOUT0 0 PU.0/
USB DP output 1 DP
PUIN0
USB DP input
PUIPE
.
PUIN1
USB DM input
PUOUT1 0 PU.1/
USB DM output 1 DM
VUSB VSSU
Pad Logic
PUREN
“1” PUR
PUSEL
PURIN

Table 61. Port PU.0/DP, PU.1/DM Output Functions (1)

CONTROL BITS PIN NAME
PUSEL PUOPE PUOUT1 PUOUT0 PU.1/DM PU.0/DP
0 0 X X Output disabled Output disabled
0 1 0 0 Output low Output low
0 1 0 1 Output low Output high
0 1 1 0 Output high Output low
0 1 1 1 Output high Output high
1 X X X DM (2) DP (2)
(1) PU.1/DM and PU.0/DP inputs and outputs are supplied from VUSB. VUSB can be generated by the
device using the integrated 3.3-V LDO when enabled. VUSB can also be supplied externally when the
3.3-V LDO is not being used and is disabled.
(2) Output state set by the USB module.
Table 62. Port PU.0/DP, PU.1/DM Input Functions (1)

CONTROL BITS PIN NAME
PUSEL PUIPE PU.1/DM PU.0/DP
0 0 Input disabled Input disabled
0 1 Input enabled Input enabled
1 X DM input DP input
(1) PU.1/DM and PU.0/DP inputs and outputs are supplied from VUSB. VUSB can be generated by the
device using the integrated 3.3-V LDO when enabled. VUSB can also be supplied externally when the
3.3-V LDO is not being used and is disabled.
Table 63. Port PUR Input Functions

CONTROL BITS
FUNCTION
PUSEL PUREN
Input disabled
0 0
Pull up disabled
Input disabled
0 1
Pull up enabled
Input enabled
1 0
Pull up disabled
Input enabled
1 1
Pull up enabled

Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.0
DVSS 0
DVCC 1 1
PJDIR.0 0
DVCC 1
PJOUT.0 0
From JTAG 1
PJ.0/TDO
PJDS.0
From JTAG 0: Low drive
1: High drive
PJIN.0
EN
Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.x
DVSS 0
DVCC 1 1
PJDIR.x 0
DVSS 1
PJOUT.x 0
From JTAG 1
PJ.1/TDI/TCLK
PJDS.x
From JTAG PJ.2/TMS
0: Low drive
PJ.3/TCK
1: High drive
PJIN.x
EN
To JTAG D

Table 64. Port PJ (PJ.0 to PJ.3) Pin Functions

CONTROL BITS/
PIN NAME (PJ.x) x FUNCTION SIGNALS (1)
PJDIR.x
(2)
PJ.0/TDO 0 PJ.0 (I/O) I: 0; O: 1
TDO (3) X
PJ.1/TDI/TCLK 1 PJ.1 (I/O) (2) I: 0; O: 1
TDI/TCLK (3) (4)
X
(2)
PJ.2/TMS 2 PJ.2 (I/O) I: 0; O: 1
TMS (3) (4)
X
(2)
PJ.3/TCK 3 PJ.3 (I/O) I: 0; O: 1
TCK (3) (4)
X
(1) X = Don't care

(2) Default condition
(3) The pin direction is controlled by the JTAG module.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.

DEVICE DESCRIPTORS (TLV)
Table 65 and Table 66 list the complete contents of the device descriptor tag-length-value (TLV) structure for
each device type.
Table 65. MSP430F552x Device Descriptor Table (1)

Size F5529 F5528 F5527 F5526 F5525 F5524 F5522 F5521
Description Address
bytes Value Value Value Value Value Value Value Value
Info Block Info length 01A00h 1 06h 06h 06h 06h 06h 06h 06h 06h
CRC length 01A01h 1 06h 06h 06h 06h 06h 06h 06h 06h
CRC value 01A02h 2 per unit per unit per unit per unit per unit per unit per unit per unit
Device ID 01A04h 1 55h 55h 55h 55h 55h 55h 55h 55h
Device ID 01A05h 1 29h 28h 27h 26h 25h 24h 22h 21h
Hardware revision 01A06h 1 per unit per unit per unit per unit per unit per unit per unit per unit
Firmware revision 01A07h 1 per unit per unit per unit per unit per unit per unit per unit per unit
Die Record Die Record Tag 01A08h 1 08h 08h 08h 08h 08h 08h 08h 08h
Die Record length 01A09h 1 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah
Lot/Wafer ID 01A0Ah 4 per unit per unit per unit per unit per unit per unit per unit per unit
Die X position 01A0Eh 2 per unit per unit per unit per unit per unit per unit per unit per unit
Die Y position 01A10h 2 per unit per unit per unit per unit per unit per unit per unit per unit
Test results 01A12h 2 per unit per unit per unit per unit per unit per unit per unit per unit
ADC12
ADC12 Calibration Tag 01A14h 1 11h 11h 11h 11h 11h 11h 11h 11h
Calibration
ADC12 Calibration length 01A15h 1 10h 10h 10h 10h 10h 10h 10h 10h
ADC Gain Factor 01A16h 2 per unit per unit per unit per unit per unit per unit per unit per unit
ADC Offset 01A18h 2 per unit per unit per unit per unit per unit per unit per unit per unit
ADC 1.5-V Reference
01A1Ah 2 per unit per unit per unit per unit per unit per unit per unit per unit
Temp. Sensor 30°C
ADC 1.5-V Reference
01A1Ch 2 per unit per unit per unit per unit per unit per unit per unit per unit
Temp. Sensor 85°C
ADC 2.0-V Reference
01A1Eh 2 per unit per unit per unit per unit per unit per unit per unit per unit
Temp. Sensor 30°C
ADC 2.0-V Reference
01A20h 2 per unit per unit per unit per unit per unit per unit per unit per unit
Temp. Sensor 85°C
ADC 2.5-V Reference
Temp. Sensor 30°C
ADC 2.5-V Reference
Temp. Sensor 85°C
REF
REF Calibration Tag 01A26h 1 12h 12h 12h 12h 12h 12h 12h 12h
Calibration
REF Calibration length 01A27h 1 06h 06h 06h 06h 06h 06h 06h 06h
REF 1.5-V Reference
Factor
REF 2.0-V Reference
01A2Ah 2 per unit per unit per unit per unit per unit per unit per unit per unit
Factor
REF 2.5-V Reference
01A2Ch 2 per unit per unit per unit per unit per unit per unit per unit per unit
Factor
Peripheral
Peripheral Descriptor Tag 01A2Eh 1 02h 02h 02h 02h 02h 02h 02h 02h
Descriptor
Peripheral Descriptor
01A2Fh 1 63h 61h 65h 63h 63h 61h 61h 64h
Length
08h 08h 08h 08h 08h 08h 08h 08h
Memory 1 2
8Ah 8Ah 8Ah 8Ah 8Ah 8Ah 8Ah 8Ah
0Ch 0Ch 0Ch 0Ch 0Ch 0Ch 0Ch 0Ch
Memory 2 2
86h 86h 86h 86h 86h 86h 86h 86h
0Eh 0Eh 0Eh 0Eh 0Eh 0Eh 0Eh 0Eh
Memory 3 2
(1) NA = Not applicable, blank = unused and reads FFh.


Table 65. MSP430F552x Device Descriptor Table(1) (continued)

Size F5529 F5528 F5527 F5526 F5525 F5524 F5522 F5521
Description Address
12h 12h 12h 12h 12h 12h 12h 12h
Memory 4 2
2Eh 2Eh 2Dh 2Dh 2Ch 2Ch 2Eh 2Dh
22h 22h 2Ah 2Ah 22h 22h 40h 2Ah
Memory 5 2
96h 96h 22h 22h 94h 94h 92h 40h
95h 95h
Memory 6 1/2 N/A N/A N/A N/A N/A 92h
92h 92h
delimiter 1 00h 00h 00h 00h 00h 00h 00h 00h
Peripheral count 1 21h 20h 21h 20h 21h 20h 20h 21h
00h 00h 00h 00h 00h 00h 00h 00h
MSP430CPUXV2 2
23h 23h 23h 23h 23h 23h 23h 23h
00h 00h 00h 00h 00h 00h 00h 00h
JTAG 2
09h 09h 09h 09h 09h 09h 09h 09h
00h 00h 00h 00h 00h 00h 00h 00h
SBW 2
0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh
00h 00h 00h 00h 00h 00h 00h 00h
EEM-L 2
05h 05h 05h 05h 05h 05h 05h 05h
00h 00h 00h 00h 00h 00h 00h 00h
TI BSL 2
FCh FCh FCh FCh FCh FCh FCh FCh
10h 10h 10h 10h 10h 10h 10h 10h
SFR 2
41h 41h 41h 41h 41h 41h 41h 41h
02h 02h 02h 02h 02h 02h 02h 02h
PMM 2
30h 30h 30h 30h 30h 30h 30h 30h
02h 02h 02h 02h 02h 02h 02h 02h
FCTL 2
38h 38h 38h 38h 38h 38h 38h 38h
01h 01h 01h 01h 01h 01h 01h 01h
CRC16 2
00h 00h 00h 00h 00h 00h 00h 00h
CRC16_RB 2
3Dh 3Dh 3Dh 3Dh 3Dh 3Dh 3Dh 3Dh
00h 00h 00h 00h 00h 00h 00h 00h
RAMCTL 2
44h 44h 44h 44h 44h 44h 44h 44h
00h 00h 00h 00h 00h 00h 00h 00h
WDT_A 2
40h 40h 40h 40h 40h 40h 40h 40h
01h 01h 01h 01h 01h 01h 01h 01h
UCS 2
48h 48h 48h 48h 48h 48h 48h 48h
02h 02h 02h 02h 02h 02h 02h 02h
SYS 2
42h 42h 42h 42h 42h 42h 42h 42h
03h 03h 03h 03h 03h 03h 03h 03h
REF 2
A0h A0h A0h A0h A0h A0h A0h A0h
01h 01h 01h 01h 01h 01h 01h 01h
Port Mapping 2
10h 10h 10h 10h 10h 10h 10h 10h
04h 04h 04h 04h 04h 04h 04h 04h
Port 1/2 2
51h 51h 51h 51h 51h 51h 51h 51h
02h 02h 02h 02h 02h 02h 02h 02h
Port 3/4 2
52h 52h 52h 52h 52h 52h 52h 52h
02h 02h 02h 02h 02h 02h 02h 02h
Port 5/6 2
53h 53h 53h 53h 53h 53h 53h 53h
02h 02h 02h 02h
Port 7/8 2 N/A N/A N/A N/A
54h 54h 54h 54h
0Ch 0Eh 0Ch 0Eh 0Ch 0Eh 0Eh 0Ch
JTAG 2
5Fh 5Fh 5Fh 5Fh 5Fh 5Fh 5Fh 5Fh
02h 02h 02h 02h 02h 02h 02h 02h
TA0 2
62h 62h 62h 62h 62h 62h 62h 62h
04h 04h 04h 04h 04h 04h 04h 04h
TA1 2
61h 61h 61h 61h 61h 61h 61h 61h
04h 04h 04h 04h 04h 04h 04h 04h
TB0 2
67h 67h 67h 67h 67h 67h 67h 67h
04h 04h 04h 04h 04h 04h 04h 04h
TA2 2
61h 61h 61h 61h 61h 61h 61h 61h
RTC 2
68h 68h 68h 68h 68h 68h 68h 68h


Size F5529 F5528 F5527 F5526 F5525 F5524 F5522 F5521
Description Address
02h 02h 02h 02h 02h 02h 02h 02h
MPY32 2
85h 85h 85h 85h 85h 85h 85h 85h
04h 04h 04h 04h 04h 04h 04h 04h
DMA-3 2
47h 47h 47h 47h 47h 47h 47h 47h
USCI_A/B 2
90h 90h 90h 90h 90h 90h 90h 90h
04h 04h 04h 04h 04h 04h 04h 04h
USCI_A/B 2
90h 90h 90h 90h 90h 90h 90h 90h
10h 10h 10h 10h 10h 10h 10h 10h
ADC12_A 2
D1h D1h D1h D1h D1h D1h D1h D1h
COMP_B 2
A8h A8h A8h A8h A8h A8h A8h A8h
04h 04h 04h 04h 04h 04h 04h 04h
USB 2
98h 98h 98h 98h 98h 98h 98h 98h
Interrupts COMP_B 1 A8h A8h A8h A8h A8h A8h A8h A8h
TB0.CCIFG0 1 64h 64h 64h 64h 64h 64h 64h 64h
TB0.CCIFG1..6 1 65h 65h 65h 65h 65h 65h 65h 65h
WDTIFG 1 40h 40h 40h 40h 40h 40h 40h 40h
USCI_A0 1 90h 90h 90h 90h 90h 90h 90h 90h
USCI_B0 1 91h 91h 91h 91h 91h 91h 91h 91h
ADC12_A 1 D0h D0h D0h D0h D0h D0h D0h D0h
TA0.CCIFG0 1 60h 60h 60h 60h 60h 60h 60h 60h
TA0.CCIFG1..4 1 61h 61h 61h 61h 61h 61h 61h 61h
USB 1 98h 98h 98h 98h 98h 98h 98h 98h
DMA 1 46h 46h 46h 46h 46h 46h 46h 46h
P1 1 50h 50h 50h 50h 50h 50h 50h 50h
USCI_A1 1 92h 92h 92h 92h 92h 92h 92h 92h
USCI_B1 1 93h 93h 93h 93h 93h 93h 93h 93h
P2 1 51h 51h 51h 51h 51h 51h 51h 51h
RTC_A 1 68h 68h 68h 68h 68h 68h 68h 68h
delimiter 1 00h 00h 00h 00h 00h 00h 00h 00h
Table 66. MSP430F551x Device Descriptor Table (1)

Size F5519 F5517 F5515 F5514 F5513
Description Address
bytes Value Value Value Value Value
Info Block Info length 01A00h 1 55h 55h 55h 55h 55h
CRC length 01A01h 1 19h 17h 15h 14h 13h
CRC value 01A02h 2 per unit per unit per unit per unit per unit
Device ID 01A04h 1 22h 21h 55h 55h 20h
Device ID 01A05h 1 80h 80h 15h 14h 80h
Hardware revision 01A06h 1 per unit per unit per unit per unit per unit
Firmware revision 01A07h 1 per unit per unit per unit per unit per unit
Die Record Die Record Tag 01A08h 1 08h 08h 08h 08h 08h
Die Record length 01A09h 1 0Ah 0Ah 0Ah 0Ah 0Ah
Lot/Wafer ID 01A0Ah 4 per unit per unit per unit per unit per unit
Die X position 01A0Eh 2 per unit per unit per unit per unit per unit
(1) NA = Not applicable, blank = unused and reads FFh.



Size F5519 F5517 F5515 F5514 F5513
Description Address
Die Y position 01A10h 2 per unit per unit per unit per unit per unit
Test results 01A12h 2 per unit per unit per unit per unit per unit
ADC12 ADC12 Calibration
01A14h 1 05h 05h 11h 11h 05h
Calibration Tag
ADC12 Calibration
01A15h 1 10h 10h 10h 10h 10h
length
ADC Gain Factor 01A16h 2 blank blank blank blank blank
ADC Offset 01A18h 2 blank blank blank blank blank
ADC 1.5-V
Reference
01A1Ah 2 blank blank blank blank blank
Temp. Sensor
30°C
ADC 1.5-V
Reference
01A1Ch 2 blank blank blank blank blank
Temp. Sensor
85°C
ADC 2.0-V
Reference
01A1Eh 2 blank blank blank blank blank
Temp. Sensor
30°C
ADC 2.0-V
Reference
01A20h 2 blank blank blank blank blank
Temp. Sensor
85°C
ADC 2.5-V
Reference
Temp. Sensor
30°C
ADC 2.5-V
Reference
Temp. Sensor
85°C
REF REF Calibration
01A26h 1 12h 12h 12h 12h 12h
Calibration Tag
REF Calibration
01A27h 1 06h 06h 06h 06h 06h
length
REF 1.5-V
01A28h 2 per unit per unit per unit per unit per unit
Reference Factor
REF 2.0-V
01A2Ah 2 per unit per unit per unit per unit per unit
Reference Factor
REF 2.5-V
01A2Ch 2 per unit per unit per unit per unit per unit
Reference Factor
Peripheral Peripheral
01A2Eh 1 02h 02h 02h 02h 02h
Descriptor Descriptor Tag
Peripheral
01A2Fh 1 61h 63h 61h 5Fh 5Fh
Descriptor Length
08h 08h 08h 08h 08h
Memory 1 2
8Ah 8Ah 8Ah 8Ah 8Ah
0Ch 0Ch 0Ch 0Ch 0Ch
Memory 2 2
86h 86h 86h 86h 86h
0Eh 0Eh 0Eh 0Eh 0Eh
Memory 3 2
2Ah 2Ah 2Ah 2Ah 2Ah
12h 12h 12h 12h 12h
Memory 4 2
2Eh 2Dh 2Ch 2Ch 2Ch
22h 2Ah 22h 22h 40h
Memory 5 2
96h 22h 94h 94h 92h


Size F5519 F5517 F5515 F5514 F5513
Description Address
95h
Memory 6 1/2 N/A N/A N/A N/A
92h
delimiter 1 00h 00h 00h 00h 00h
Peripheral count 1 20h 20h 20h 1Fh 1Fh
00h 00h 00h 00h 00h
MSP430CPUXV2 2
23h 23h 23h 23h 23h
00h 00h 00h 00h 00h
JTAG 2
09h 09h 09h 09h 09h
00h 00h 00h 00h 00h
SBW 2
0Fh 0Fh 0Fh 0Fh 0Fh
00h 00h 00h 00h 00h
EEM-L 2
05h 05h 05h 05h 05h
00h 00h 00h 00h 00h
TI BSL 2
FCh FCh FCh FCh FCh
10h 10h 10h 10h 10h
SFR 2
41h 41h 41h 41h 41h
02h 02h 02h 02h 02h
PMM 2
30h 30h 30h 30h 30h
02h 02h 02h 02h 02h
FCTL 2
38h 38h 38h 38h 38h
01h 01h 01h 01h 01h
CRC16 2
3Ch 3Ch 3Ch 3Ch 3Ch
00h 00h 00h 00h 00h
CRC16_RB 2
3Dh 3Dh 3Dh 3Dh 3Dh
00h 00h 00h 00h 00h
RAMCTL 2
44h 44h 44h 44h 44h
00h 00h 00h 00h 00h
WDT_A 2
40h 40h 40h 40h 40h
01h 01h 01h 01h 01h
UCS 2
48h 48h 48h 48h 48h
02h 02h 02h 02h 02h
SYS 2
42h 42h 42h 42h 42h
03h 03h 03h 03h 03h
REF 2
A0h A0h A0h A0h A0h
01h 01h 01h 01h 01h
Port Mapping 2
10h 10h 10h 10h 10h
04h 04h 04h 04h 04h
Port 1/2 2
51h 51h 51h 51h 51h
02h 02h 02h 02h 02h
Port 3/4 2
52h 52h 52h 52h 52h
02h 02h 02h 02h 02h
Port 5/6 2
53h 53h 53h 53h 53h
02h 02h 02h
Port 7/8 2 N/A N/A
54h 54h 54h
0Ch 0Ch 0Ch 0Eh 0Eh
JTAG 2
5Fh 5Fh 5Fh 5Fh 5Fh
02h 02h 02h 02h 02h
TA0 2
62h 62h 62h 62h 62h
04h 04h 04h 04h 04h
TA1 2
61h 61h 61h 61h 61h
04h 04h 04h 04h 04h
TB0 2
67h 67h 67h 67h 67h
04h 04h 04h 04h 04h
TA2 2
61h 61h 61h 61h 61h


Size F5519 F5517 F5515 F5514 F5513
Description Address
0Ah 0Ah 0Ah 0Ah 0Ah
RTC 2
68h 68h 68h 68h 68h
02h 02h 02h 02h 02h
MPY32 2
85h 85h 85h 85h 85h
04h 04h 04h 04h 04h
DMA-3 2
47h 47h 47h 47h 47h
0Ch 0Ch 0Ch 0Ch 0Ch
USCI_A/B 2
90h 90h 90h 90h 90h
04h 04h 04h 04h 04h
USCI_A/B 2
90h 90h 90h 90h 90h
ADC12_A 2 N/A N/A N/A N/A N/A
2Ch 2Ch 2Ch 2Ch 2Ch
COMP_B 2
A8h A8h A8h A8h A8h
04h 04h 04h 04h 04h
USB 2
98h 98h 98h 98h 98h
Interrupts COMP_B 1 A8h A8h A8h A8h A8h
TB0.CCIFG0 1 64h 64h 64h 64h 64h
TB0.CCIFG1..6 1 65h 65h 65h 65h 65h
WDTIFG 1 40h 40h 40h 40h 40h
USCI_A0 1 90h 90h 90h 90h 90h
USCI_B0 1 91h 91h 91h 91h 91h
ADC12_A 1 01h 01h 01h 01h 01h
TA0.CCIFG0 1 60h 60h 60h 60h 60h
TA0.CCIFG1..4 1 61h 61h 61h 61h 61h
USB 1 98h 98h 98h 98h 98h
DMA 1 46h 46h 46h 46h 46h
TA1.CCIFG0 1 62h 62h 62h 62h 62h
TA1.CCIFG1..2 1 63h 63h 63h 63h 63h
P1 1 50h 50h 50h 50h 50h
USCI_A1 1 92h 92h 92h 92h 92h
USCI_B1 1 93h 93h 93h 93h 93h
TA1.CCIFG0 1 66h 66h 66h 66h 66h
TA1.CCIFG1..2 1 67h 67h 67h 67h 67h
P2 1 51h 51h 51h 51h 51h
RTC_A 1 68h 68h 68h 68h 68h
delimiter 1 00h 00h 00h 00h 00h

REVISION HISTORY
REVISION DESCRIPTION
SLAS590 Limited product preview release
SLAS590A Changes throughout for XMS430F5529 sampling
SLAS590B Changes throughout for updated preview
SLAS590C Changes throughout for updated preview
SLAS590D Production data release
Updated YFF and ZQE pinout drawings.

SLAS590E Changed Tstg maximum to 150°C in Absolute Maximum Ratings.
Changed fXT2,HF,SW MIN to 0.7 MHz in Crystal Oscillator, XT2.
SLAS590F Corrected terminal assignments for YFF package in Pin Designation – MSP430F5528IYFF, MSP430F5526IYFF,
MSP430F5524IYFF and Terminal Functions
Changed limits for wake-up time, LPM3/4 current, reference current, ADC12 maximum frequency, ADC linearity — see
the following tables:
Low-Power Mode Supply Currents (Into VCC) Excluding External Current
12-Bit ADC, Power Supply and Input Range Conditions
12-Bit ADC, Timing Parameters
SLAS590G
12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
REF, External Reference
REF, Built-In Reference
Changed notes regarding crystal capacitance in Crystal Oscillator, XT1, Low-Frequency Mode
Corrected lost and corrupted symbols throughout. Affected symbols include: Δ θ Ω → ≥ ≤ ≠

Changed ACLK signal description in Terminal Functions.
SLAS590H Changed note on 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference
Voltage.
Changed notes regarding UCA0CLK and UCB0CLK function on Table 50 and Table 51.
Changed MSP430F5528IYFF to Production Data.

Table 3, Changed PUR pin description.
USB BSL, Added note regarding PUR pin.
SLAS590I
Table 12, Changed SYSRSTIV interrupt event with value 1Ch to Reserved.
Recommended Operating Conditions, Added note regarding interaction between minimum VCC and SVSH.
12-Bit ADC, Temperature Sensor and Built-In VMID, Changed tSENSOR(sample) MIN to 100 µs, and changed note (2).
Recommended Operating Conditions, Added TYP test conditions

SLAS590J DCO Frequency, Added note (1)
Flash Memory, Restored Flash erase currents to previous values (changed from TBD).
SLAS590K Flash Memory, Changed IERASE and IMERASE values.
Table 2, Production release of F5226 and F5224 in YFF package.

SLAS590L Table 3, Added note regarding pullup resistor on RST/NMI/SBWTDIO pin.
Pin Designation – MSP430F5528IYFF..., Added ball-side view and changed top-side view.

PACKAGE OPTION ADDENDUM
www.ti.com 2-Dec-2014
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
MSP430F5513IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F5513
& no Sb/Br)
MSP430F5513IRGCT NRND VQFN RGC 64 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F5513
& no Sb/Br)
MSP430F5513IZQE ACTIVE BGA ZQE 80 360 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 M430F5513
MICROSTAR & no Sb/Br)
JUNIOR
MSP430F5513IZQER ACTIVE BGA ZQE 80 2500 Green (RoHS SNAGCU Level-3-260C-168 HR -40 to 85 M430F5513
JUNIOR
& no Sb/Br)
MSP430F5514IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F5514
& no Sb/Br)
JUNIOR
JUNIOR
MSP430F5515IPN ACTIVE LQFP PN 80 119 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F5515
& no Sb/Br)
MSP430F5515IPNR ACTIVE LQFP PN 80 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 M430F5515
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
Addendum-Page 1
(1) Drawing Qty (2) (6) (3) (4/5)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
JUNIOR
JUNIOR
& no Sb/Br)
& no Sb/Br)
MSP430F5524IYFFR ACTIVE DSBGA YFF 64 2500 Green (RoHS SNAGCU Level-1-260C-UNLIM M430F5524
& no Sb/Br)
MSP430F5524IYFFT NRND DSBGA YFF 64 250 Green (RoHS SNAGCU Level-1-260C-UNLIM M430F5524
& no Sb/Br)
JUNIOR
JUNIOR
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
MSP430F5526IYFFR ACTIVE DSBGA YFF 64 2500 Green (RoHS SNAGCU Level-1-260C-UNLIM M430F5526
& no Sb/Br)
Addendum-Page 2
(1) Drawing Qty (2) (6) (3) (4/5)
MSP430F5526IYFFT NRND DSBGA YFF 64 250 Green (RoHS SNAGCU Level-1-260C-UNLIM M430F5526
& no Sb/Br)
JUNIOR
JUNIOR
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
MSP430F5528IYFFR ACTIVE DSBGA YFF 64 2500 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 M430F5528
& no Sb/Br)
JUNIOR
JUNIOR
& no Sb/Br)
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
Addendum-Page 3
TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Jan-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430F5513IZQER BGA MI ZQE 80 2500 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q1
CROSTA
R JUNI
OR
MSP430F5514IRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2
CROSTA
R JUNI
OR
MSP430F5515IPNR LQFP PN 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 Q2
CROSTA
R JUNI
OR
MSP430F5524IYFFR DSBGA YFF 64 2500 330.0 12.4 3.86 3.86 0.69 8.0 12.0 Q2
MSP430F5524IYFFT DSBGA YFF 64 250 180.0 12.4 3.86 3.86 0.69 8.0 12.0 Q2
Pack Materials-Page 1
Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CROSTA
R JUNI
OR
MSP430F5526IYFFT DSBGA YFF 64 250 180.0 12.4 3.86 3.86 0.69 8.0 12.0 Q2
CROSTA
R JUNI
OR
CROSTA
R JUNI
OR
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430F5513IZQER BGA MICROSTAR ZQE 80 2500 338.1 338.1 20.6
JUNIOR
MSP430F5514IRGCT VQFN RGC 64 250 210.0 185.0 35.0
JUNIOR
MSP430F5515IPNR LQFP PN 80 1000 367.0 367.0 45.0
MSP430F5517IPNR LQFP PN 80 1000 367.0 367.0 45.0
MSP430F5519IPNR LQFP PN 80 1000 367.0 367.0 45.0
MSP430F5521IPNR LQFP PN 80 1000 367.0 367.0 45.0
JUNIOR
MSP430F5524IYFFR DSBGA YFF 64 2500 367.0 367.0 35.0
MSP430F5524IYFFT DSBGA YFF 64 250 210.0 185.0 35.0
JUNIOR
MSP430F5525IPNR LQFP PN 80 1000 367.0 367.0 45.0
MSP430F5526IYFFT DSBGA YFF 64 250 210.0 185.0 35.0
JUNIOR
MSP430F5527IPNR LQFP PN 80 1000 367.0 367.0 45.0
JUNIOR
MSP430F5529IPNR LQFP PN 80 1000 367.0 367.0 45.0
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80) PLASTIC QUAD FLATPACK
0,27
0,50 0,08 M
0,17
60 41
61 40
0,13 NOM
80 21
1 20 Gage Plane
9,50 TYP
12,20 0,25
SQ
11,80 0,05 MIN 0°– 7°
14,20
SQ
13,80
1,45 0,75
1,35 0,45
Seating Plane
1,60 MAX 0,08
4040135 / B 11/96
NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

D: Max = 3.79 mm, Min = 3.73 mm
E: Max = 3.79 mm, Min = 3.73 mm

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mps430 Datasheet

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MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526

MSP430F5525, MSP430F5524, MSP430F5522, MSP430F5521

MIXED SIGNAL MICROCONTROLLER

Table 1. Family Members

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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524

Table 2. Ordering Information (1)

Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 3

Functional Block Diagram – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN,

JTAG/ TA0 TA1 TA2 TB0 USCI_Ax: 12 Bit

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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524

Pin Designation – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN, MSP430F5521IPN

Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 5

Functional Block Diagram –

JTAG/ TA0 TA1 TA2 TB0 USCI_Ax: 12 Bit

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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524

Pin Designation – MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC,

Note: Power Pad connection

Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 7

Functional Block Diagram – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN

JTAG/ TA0 TA1 TA2 TB0 USCI_Ax:

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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524

Pin Designation – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN

Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 9

Functional Block Diagram – MSP430F5514IRGC, MSP430F5513IRGC, MSP430F5514IZQE,

JTAG/ TA0 TA1 TA2 TB0 USCI_Ax:

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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524

Pin Designation – MSP430F5514IRGC, MSP430F5513IRGC

Note: Power Pad connection

Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 11

Pin Designation – MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE,

P6.0 RST/NMI PJ.2 TEST AVSS2 VUSB VBUS PU.1 PU.0

P6.2 P6.1 PJ.3 P5.3 P5.2 V18 PUR VSSU VSSU

P6.4 P6.3 PJ.1 PJ.0 Rsvd P4.7 P4.6 P4.5

P6.6 P6.5 P6.7 Rsvd Rsvd Rsvd P4.4 P4.3 P4.2

P5.0 P5.1 Rsvd Rsvd Rsvd Rsvd P4.1 P4.0 DVCC2

P5.4 AVCC1 Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd DVSS2

P5.5 AVSS1 Rsvd P1.3 P1.6 P2.1 P3.4 P3.2 P3.3

DVCC1 P1.0 P1.1 P1.4 P1.7 P2.3 P2.7 P3.0 P3.1

DVSS1 VCORE P1.2 P1.5 P2.0 P2.2 P2.4 P2.5 P2.6

12 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated

Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524

Pin Designation – MSP430F5528IYFF, MSP430F5526IYFF, MSP430F5524IYFF

Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 13

Table 3. Terminal Functions

General-purpose digital I/O

General-purpose digital I/O

General-purpose digital I/O

General-purpose digital I/O

General-purpose digital I/O (not available on F5528, F5526, F5524,

General-purpose digital I/O (not available on F5528, F5526, F5524,

General-purpose digital I/O (not available on F5528, F5526, F5524,

General-purpose digital I/O (not available on F5528, F5526, F5524,

General-purpose digital I/O

General-purpose digital I/O