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Verilog 5 Tasks Functions

Tasks and functions allow breaking up complex Verilog code into smaller, more manageable pieces. Tasks can contain delays and have input, output, and in-out parameters, while functions cannot contain delays and only have inputs and outputs. Tasks are used more for testing while functions can be used for both design and testing code. The arguments of tasks are passed by value, while functions return a single value.

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Sruthi Paleti
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101 views

Verilog 5 Tasks Functions

Tasks and functions allow breaking up complex Verilog code into smaller, more manageable pieces. Tasks can contain delays and have input, output, and in-out parameters, while functions cannot contain delays and only have inputs and outputs. Tasks are used more for testing while functions can be used for both design and testing code. The arguments of tasks are passed by value, while functions return a single value.

Uploaded by

Sruthi Paleti
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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VERILOG – Tasks and Functions

• Both, tasks and Functions, allow you to execute common


procedures from different places in a program/code .
• They help to simplify the complex behavior of the design by
breaking up large procedures into smaller, more manageable
ones.
• A task describes a separate piece of functionality that is a
smaller part of a bigger system
• A task can contain delays, while a function cannot.

2/28/2017 ANAND S MOGHE 1


VERILOG – Tasks and Functions
• A function has only input parameters and it returns a single
value
• A task can have input, output and in-out parameters
(arguments)
• Tasks are used more in test-benches, while functions can be
used in design code and test-benches also
• Argu e ts are passed to the task/fu tio through pass y
value e ha is

2/28/2017 ANAND S MOGHE 2


Tasks and Functions
..... IR
always @(sys_clk) begin
PC
if (read_request == 1’b1) begin usage
read_mem (IR, PC ); clk
// …event and function calls….
end

task read_mem;
output [15:0] data_in;
input [15:0] addr; stack
definition
@(posedge clk) begin IR
…
PC
end
@(posedge read_grant) begin
ADDRESS = addr;
#15 data_in = data;
end
endtask
2/28/2017 ANAND S MOGHE 3
Tasks
• A task is enabled when the task name is encountered in the
Verilog description
• Task definition is contained within the definition of the
module.
• The arguments passed to the task are in the same order as
the task I/O declarations.
• You can use timing controls ( #DELAY , @, wait) freely in a
task.
• Arguments are passed by value to a task (or function).
-> This means that an argument to a task or a function cannot be
expected to change inside the task/function.

2/28/2017 ANAND S MOGHE 4


Functions
always @(sys_clk) begin
. . . usage
SW_IR = swap_bits(IR);
. . .
end
function width

function [15:0] swap_bits;


input [15:0] in_vec;

reg [15:0] temp_reg; definition

integer i;
begin
for (i=15; i>=0; i=i-1)
temp_reg[15-i] = in_vec[i]; Y = mux4_1(a,b,c,d,s);
swap_bits = temp_reg;
end
endfunction

2/28/2017 ANAND S MOGHE 5


Functions
Key features:
• A function definition cannot contain any timing-control statements (#, @,
wait). Function executes in zero simulation time.

• It must contain at least one input and does not contain any output or in-
out ports.
– A function returns only one value, which is the value of the function itself.
Therefore, arguments cannot be declared as output or in-out.

• The arguments passed to a function are in the same order as the function
parameter declarations

• The function definition must be contained within the module of the


definition.

• A function cannot enable a task. But it can call another function. A task
can enable a function.

2/28/2017 ANAND S MOGHE 6


Comparison of Tasks and Functions
Category Tasks Functions
Enabling (calling) A task call is a separate A function call is an operand in an
procedural statement. It cannot expression. It is called from within
be called from a continuous the expression and returns a value
assignment statement used in the expression. Functions
may be called from within procedural
and continuous assignments
statements
Inputs and outputs A task can have zero or more A function has at least one input. It
arguments of any type does not have any in-outs or outputs
Timing and event A task can contain timing and Functions may not contain these
controls (wait, @, , #) event control statements statements
Enabling other tasks A task can enable other tasks A function can enable other
and functions and functions functions but not other tasks
Values returned A task does not return a value. A function returns a single value to
However, values written into its the expression that called it. The
in-out or output ports are value to be returned is assigned to
copied back at the end of the the function identifier within the
task execution function
2/28/2017 ANAND S MOGHE 7
VERILOG – Tasks
Implication of static variables (arguments) in tasks.

1st invocation T=T1


(from initial block-1)
T=0
arg1, arg2, arg3

arg11, arg22, arg33

2nd invocation
(from initial block-2)

ANAND S MOGHE 8
VERILOG – (automatic )Tasks
Implication of static variables (arguments) in tasks.

1st invocation T=T1

T=0
arg1, arg2, arg3

arg11, arg22, arg33

2nd invocation

Solution: task automatic -- defines a task where arguments are passed


on a stack (automatic variables) and makes the task re-entrant.
ANAND S MOGHE 9
Use of the disable statement

task bus_request;
output good;
begin : bus_request_task
if (grt == 1’b1) begin
good = 1’b0;
disable bus_request_task;
end
req = 1’b1;
fork: wait_for_grt
#60 disable wait_for_grt;
@(posedge grt) disable wait_for_grt;
join
good = (grt == 1’b1)
end
endtask

2/28/2017 ANAND S MOGHE 10


Use of the disable statement

task bus_request;
output good;
begin : bus_request_task
if (grt == 1’b1) begin
good = 1’b0;
disable bus_request_task;
end
req = 1’b1;
fork: wait_for_grt
#60 disable wait_for_grt;
@(posedge grt) disable wait_for_grt;
join
good = (grt == 1’b1)
end
endtask

2/28/2017 ANAND S MOGHE 11


Use of the disable statement
• A task should never be disabled by a disable statement.
Disabling a task does not cause the endtask statement to get
executed sometimes, and the results can be incorrect.
• Only the named outermost begin-end block inside a task
should be disabled, because when a task is disabled, Verilog
does not specify the value of the output arguments of the
task. Thus, the output may differ between simulators when a
task is disabled.
• However, if the outermost begin-end block is disabled, then
the endtask statement gets executed on exiting from the task
and the output variables will get copied back correctly.

2/28/2017 ANAND S MOGHE 12

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