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Verilog Interview

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lakshmirandhawa143
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15 views

Verilog Interview

Uploaded by

lakshmirandhawa143
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 18

 Differentiate between == and ===.

 What are Blocking and non-blocking in Verilog?


 What is the Sensitivity list?
 Explain $monitor, $display and $strobe.
 What does timescale 1 Ns/1 Ps mean?
 What are the primary differences between Verilog's Task and
Function
 What are the 3 types of coding in Verilog?
 Can race conditions occur in Verilog? How to avoid race
conditions in Verilog
 Write a Verilog program to switch the contents of two registers
with and without a temporary register.
DIFFERENTIATE BETWEEN == AND ===.

== ===

Output can be 1,0 or X Output can be 0 or 1

It can compare 1s and 0s but not Xs Can also compare Xs


WHAT ARE BLOCKING AND NON-BLOCKING IN VERILOG?

 The blocking assignment completes the entire statement before the control goes

to the next statement. It behaves similarly to older programming languages. It is


symbolized as =.
 A non-blocking assignment evaluates the right-hand side for the current time

unit and the left-hand side later at the end of the time unit. It is symbolized as <=.
Always @ (a or b or c)
Begin
X <= a | b; 1. Evaluate a | b but defer assignment of x
Y <= a ^ b ^ c; 2. Evaluate a^b^c but defer assignment of y
Z <= b & ~c; 3. Evaluate b&(~c) but defer assignment of z
End 4. Assign x, y, and z with their new values
WHAT IS THE SENSITIVITY LIST?

 It specifies the list of the signals one wants to cause the code during the process

to be evaluated when it changes its state.


 Always block with a sensitivity list
module and_gate(input i1, i2, i3, output reg out);

always@(i1 or i2 or i3) begin


out = i1 & i2 & i3;
end Output:

At T = 0: i1 = 0, i2 = 0, i3 = 0, out = 0
// or At T = 5: i1 = 0, i2 = 1, i3 = 0, out = 0
At T = 13: i1 = 1, i2 = 1, i3 = 0, out = 0
//always @(*) out = i1 & i2 & i3;
At T = 16: i1 = 1, i2 = 1, i3 = 1, out = 1

endmodule
EXPLAIN $MONITOR, $DISPLAY AND $STROBE.

• These commands have similar syntax and show text on the screen during
simulation.

• $display and $strobe appear once when executed.

• $monitor appears every time a parameter is changed.


WHAT DOES TIMESCALE 1 NS/1 PS MEAN?

 It means all delays are interpreted in nanoseconds, and fractions are rounded off

to the nearest picosecond.


`timescale 1ns/1ns: Since precision =
1ns, the simulator will advance its time
if the delay value is greater or equal to
0.5ns. Thus, time advancement does not
happen for 0.45ns delay.
`timescale 1ns/1ps: Since
precision = 1ps, the simulator
will advance for all the cases.
WHAT ARE THE PRIMARY DIFFERENCES BETWEEN VERILOG'S TASK AND
FUNCTION
Task Function

Can have zero or more than one argument. It needs to have at least one argument.

A function cannot have a delay statement. It should


A task can have delay statements inside it.
return a value at the same time step.

A Task Does not have a return type. However, output


A function does have a return type.
arguments help return value.

A task can return more than one values as there can


A function can return only one value at a time
be any number of output arguments.

A function can only call another function from its


A task can call another function or a task from its
body. A task cannot be called as it can consume time,
body.
and function is not allowed to consume time.
Write a Verilog program to switch the contents of two registers with and
without a temporary register.

An example of a Verilog code that


switches the contents of two registers Without a temporary register, a Verilog
with a temporary register: program can swap the contents of two
registers:
always @ (posedge clock)
begin always @ (posedge clock)
temp=y; begin
y=x; x <= y;
x=temp; y <= x;
end. end
WHEN SHOULD YOU USE TASKS INSTEAD OF FUNCTIONS?

 You should use tasks instead of functions in Verilog when you need to perform a
sequence of procedural actions or when you require multiple input/output
variables.
 Tasks are more suitable for modeling complex behavior. They can contain both
procedural statements and timing controls, allowing you to model more
complicated processes.
CAN RACE CONDITIONS OCCUR IN VERILOG? HOW TO AVOID RACE
CONDITIONS IN VERILOG

 Yes, race conditions can occur in Verilog. A race condition arises due to concurrent events happening in
different orders, and the final outcome depends on the order of timing of these events.

 To avoid race conditions:


1. Use non-blocking assignments for sequential logic.
2. Avoid mixing blocking and non-blocking assignments within the same always block.
3. Use separate always blocks for combinational and sequential logic.
4. Ensure proper clock domain crossing techniques when dealing with multiple clock domains.
5. Use the $strobe system task instead of $display for monitoring signals that may have multiple events in the
same simulation time step.
WHAT ARE THE 3 TYPES OF CODING IN VERILOG?

 Verilog, a hardware description language, has three main types of coding:


structural coding, behavioral coding, and register transfer level (RTL) coding.
Structural focuses on component connections, behavioral on functionality, and
RTL on data flow.

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