VLSI

(Very-Large-Scale Integration)
LABORATORY MANUAL
(R16) III – B. Tech., ii-Semester
ECE

Name of the Student:

H. T. No: Academic Year:

 JAWAHARLAL NEHRU TE CHNOLOGICAL UNIVERSITY: KAKINADA
KAKINADA - 533 003, Andhra Pradesh, India
ELECTRONICS AND COMMUNICATION ENGINEERING

III Year - II Semester TPC

032

VLSI Laboratory

Note: The students are required to design the schematic diagrams using CMOS logic and to draw the layout
diagrams to perform the following experiments using 130nm technology with the Industry standard EDA Tools.

List of Experiments:

i. Design and Implementation of an Universal Gates

ii. Design and Implementation of an Inverter
iii. Design and Implementation of Full Adder
iv. Design and Implementation of Full Subtractor
v. Design and Implementation of Decoder
vi. Design and Implementation of RS-Latch
vii. Design and Implementation of D-Latch
viii. Design and Implementation asynchronous counter
ix. Design and Implementation of static RAM cell
x. Design and Implementation of 8 bit DAC using R-2R latter network

Software Required:
i. Mentor Graphics Software / Equivalent Industry Standard Software.
ii. Personal computer system with necessary software to run the programs and to implement.
 RAMACHANRDA COLLEGE OF ENGINEERING
ELURU – 534 007, West Godavari District, Andhra Pradesh
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI (Very-Large-Scale Integration) LABORATORY MANUAL
(R16) III – B. Tech., ii-Semester
Index
S. No. Name of the Experiment Date Marks Signature

Design and implementation of an

1.
inverter
Design and implementation of universal
2.
gates
Design and implementation of full
3.
adder
Design and implementation of full
4.
subtractor

5. Design and Implementation of Decoder

Design and implementation of RS-latch

6.

Design and implementation of D-latch

7.

Design and implementation

8.
asynchronous counter
Design and Implementation of static
9.
RAM cell
Design and Implementation of 8 bit DAC
10.
using R-2R latter network

Additional Experiment
Design and Implementation of ring
11.
oscillator
Design and Implementation of
12.
differential amplifier
 DEPARTMENT OF ELECTRONICS & COMMUNICATIONS ENGINEERING

VISION & MISSION

To produce innovative, ethical and socially responsible graduates in the field of

Vision
Electronics and Communication Engineering who can address the global and
environmental challenges through excellence in technical education and research.
• To provide creative learning environment to the students by offering state-of-the-art
infrastructure, core instruction and highly qualified and motivated faculty.
• To adapt the learners to use new technologies in Electronics and Communication
Engineering field by engaging in cutting-edge research through collaborations with
Mission
industry and academia.
• To imbibe self- learning attitude, entrepreneur skills, professional ethics and
leadership qualities among the graduates to make them globa lly competent.
• To extend the benefits of the technology to solve the environmental and societal
challenges.
 RAMACHANRDA COLLEGE OF ENGINEERING
ELURU – 534 007, West Godavari District, Andhra Pradesh
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

PEO No.  PEO Description

PEO 1  Develop a solid foundation in Mathematics, Science and Technology to solve
Electronics and Communication engineering problems.
PEO 2  Identify, analyze and apply core engineering concepts to develop novel products
and solutions for real life problems.
PEO 3  Pursue higher studies, research & development and other creative efforts in
science & technology and keep abreast of latest technological developments.
PEO 4  Inculcate professional and ethical attitude, effective communication skills, team
spirit and leadership qualities.
PEO 5  Contribute to the needs of the society in solving technical problems using
Electronics & Communication Engineering principles, tools and practices.

PO STATEMENT
PO No
Engineering knowledge: Apply the knowledge of mathematics, science, engineering
PO1 fundamentals, and an engineering specialization for the solution of complex engineering
problems.
Problem analysis: Identify, formulate, research literature, and analyse complex engineering
PO2 problems reaching substantiated conclusions using first principles of mathematics, natural
sciences, and engineering sciences.
Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
PO3 consideration for public health and safety, and cultural, societal, and environmental
considerations.
Conduct investigations of complex problems: Use research-based knowledge and research
PO4 methods including design of experiments, analysis and interpretation of data and synthesis of
the information to provide valid conclusions.
Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
PO5 engineering and IT tools, including prediction and modelling to complex engineering activities,
with an understanding of the limitations.
The engineer and society: Apply reasoning informed by the contextual knowledge to assess
PO6 societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to
the professional engineering practice.
Environment and sustainability: Understand the impact of the professional engineering
PO7 solutions in societal and environmental contexts, and demonstrate the knowledge of, and need
for sustainable development.
Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
PO8 norms of the engineering practice.
Individual and team work: Function effectively as an individual, and as a member or leader
PO9 in diverse teams, and in multidisciplinary settings.
Communication: Communicate effectively on complex engineering activities with the
engineering community and with t h e society at large, such as, being able to comprehend and
PO10 write effective reports and design documentation, make effective presentations, and give and
receive clear instructions.
Project management and finance: Demonstrate knowledge and understanding of the
PO11 engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
Life-long learning: Recognize the need for, and have the preparation and ability to engage in
PO12 independent and life-long learning in the broadest context of technological change.
GENERAL INSTRUCTIONS:
1. The experiments have been designed to be performed with in the 3-hour
laboratory time.
2. To successfully complete the experiment in one lab turn, come prepared to the
laboratory.
3. Read the experiment in advance.
4. List and collect the components for the experiment.
5. Be sure that the specifications and values of the components are as per
design.
6. Follow the experimental steps judiciously.
7. Record stepwise observations using proper test instruments.
8. Get the observation signed by the instructor.
9. Always take safety precautions while performing experiments.

GUIDANCE FOR THE LABORATORY REPORT:

1. Format of the report
Expt. No: Date: Expt. Title:
Objective:
List of instruments and
components: Theory in brief
Procedure, Observations, Graph if any
Result
2. Write the experimental observations and measurements stepwise.
3. Plot the graph neatly. Always label the axes and indicate units too. Wherever
frequency response is to be drawn, use the semi-log graph paper.
4. Compare the results with theoretical values with remarks/comments.
5. Wherever necessary, sketch the circuit diagram neatly and label the components.
 Dept. of ECE VLSI Lab

Design and Implementation of an Inverter

AIM: To design and Implementation of an Inverter
TOOLS: Mentor Graphics - Pyxis, AMS, Calibre.

CIRCUIT DIAGRAM:

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PROCEDURE:
1. Connect the Circuit as shown in the circuit diagram using Pyxis Schematic tool

2. Enter into Simulation mode.

3. Setup the Analysis and library.

4. Setup the required analysis.

5. Probe the required Voltages

6. Run the simulation.

7. Observe the waveforms in EZ wave.

8. Draw the layout using Pysis Layout.

9. Perform Routing using IRoute

10. Perform DRC, LVS, PEX.

Result:

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Layout:

Result Verification Environment:

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Experiment Practice & Viva Answers
Experiment Practice & Viva Answers
Dept. of ECE VLSI Lab

Design and Implementation Universal Gates

Aim: To design and implementation of universal gates

Tools: Mentor Graphics-Pyxis, AMS, Calibre

(i). NAND Gate:

Circuit Diagram:

PROCEDURE:
1. Connect the Circuit as shown in the circuit diagram using Pyxis Schematic tool

2. Enter into Simulation mode.

3. Setup the Analysis and library.

4. Setup the required analysis.

5. Probe the required Voltages

6. Run the simulation.

7. Observe the waveforms in EZ wave.

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Testbench:

Result:

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NOR Gate:

Testbench:

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Experiment Practice & Viva Answers
Experiment Practice & Viva Answers
Dept. of ECE VLSI Lab

Design and Implementation of Full Adder

AIM: To design and Implementation of an Fulladder
TOOLS: Mentor Graphics - Pyxis, AMS, Calibre.

CIRCUIT DIAGRAM:

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Testbench:

Result:

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Experiment Practice & Viva Answers
Experiment Practice & Viva Answers
Dept. of ECE VLSI Lab

Design and Implementation of Full Subtractor

AIM: To design and Implementation of an Full-subtractor
TOOLS: Mentor Graphics - Pyxis, AMS, Calibre.

CIRCUIT DIAGRAM:

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Testbench:

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Experiment Practice & Viva Answers
Experiment Practice & Viva Answers
Dept. of ECE VLSI Lab

Design and Implementation of Decoder

AIM: To design and Implementation of Decoder
TOOLS: Mentor Graphics - Pyxis, AMS, Calibre.

CIRCUIT DIAGRAM:

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Test:

Result:

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Experiment Practice & Viva Answers
Experiment Practice & Viva Answers
Dept. of ECE VLSI Lab

Design and Implementation of RS-Latch

AIM: To design and Implementation of RS Latch
TOOLS: Mentor Graphics - Pyxis, AMS, Calibre.

CIRCUIT DIAGRAM:

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Testbench:

Result:

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Experiment Practice & Viva Answers
Experiment Practice & Viva Answers
Dept. of ECE VLSI Lab

Design and Implementation of D-Latch

AIM: To design and Implementation of an D-Latch
TOOLS: Mentor Graphics - Pyxis, AMS, Calibre.

CIRCUIT DIAGRAM:

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Testbench:

Result:

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Experiment Practice & Viva Answers
Experiment Practice & Viva Answers
Dept. of ECE VLSI Lab

Design and Implementation of Asynchronous Counter

AIM: To design and Implementation of an Asynchronous Counter
TOOLS: Mentor Graphics - Pyxis, AMS, Calibre.

CIRCUIT DIAGRAM:

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Testbench:

Result:

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Experiment Practice & Viva Answers
Experiment Practice & Viva Answers
Dept. of ECE VLSI Lab

Design and Implementation of Static-Ram Cell

AIM: To design and Implementation of Static Ram Cell
TOOLS: Mentor Graphics - Pyxis, AMS, Calibre.

CIRCUIT DIAGRAM:

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Test:

Result:

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Experiment Practice & Viva Answers
Experiment Practice & Viva Answers
Dept. of ECE VLSI Lab

Design a Decodernd Implementation of 8 bit DAC using R-2R

AIM: To Design and Implementation of 8 bit DAC using R-2R latter network
TOOLS: Mentor Graphics - Pyxis, AMS, Calibre.

CIRCUIT DIAGRAM:

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Test:

Result:

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Experiment Practice & Viva Answers
Experiment Practice & Viva Answers
Dept. of ECE VLSI Lab

Design and Implementation of an Ring Oscillator

Additional Experiment
AIM: To design and Implementation of Ring Oscillator
Counter
TOOLS: Mentor Graphics - Pyxis, AMS, Calibre.

CIRCUIT DIAGRAM:

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Result:

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Experiment Practice & Viva Answers
Experiment Practice & Viva Answers
Dept. of ECE VLSI Lab

Design and Implementation of Differential Amplifier

Additional Experiment
AIM: To design and Implementation of an Differential Amplifier
TOOLS: Mentor Graphics - Pyxis, AMS, Calibre.

CIRCUIT DIAGRAM:

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Testbench:

Result:

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Experiment Practice & Viva Answers
Experiment Practice & Viva Answers
VIVA QUESTIONS EXPERIMENT WISE

Experiment 1:
1. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
2. What are set up time & hold time constraints? What do they signify?
3. What is Body Effect?
4. Why is the substrate in NMOS connected to Ground and in PMOS to VDD?
5. What happens when the PMOS and NMOS are interchanged with one another in an inverter?
6. What is latch up?
7. Explain sizing of the inverter?
8. What is the fundamental difference between a MOSFET and BJT ?
9. What is Noise Margin? Explain the procedure to determine Noise Margin
10. Explain sizing of the inverter?

Experiment 2:
1. Why is NAND gate preferred over NOR gate for fabrication?
2. Why are pMOS transistor networks generally used to produce high signals, while nMOS networks are
used to product low signals?
3. What’s the difference between Testing & Verification?
4. What are four generations of Integration Circuits?
5. What is Intrinsic and Extrinsic Semiconductor?
6. What is CMOS Technology?
7. Give the variety of Integrated Circuits?
8. Why NMOS technology is preferred more than PMOS technology?
9. What are the different MOS layers?
10. What are the different layers in MOS transistor?

Experiment 3:
1. Give the advantages of IC?
2. Half-adders have a major limitation in that they cannot
3. Write sum and carry expression of full adder
4. How fulladder can realize by using half adder
5. Draw the cmos implementation of full adder.
6. Difference between half adder and a full adder
7. Design full adder cum Subtractor using mode control
8. Design a full adder using two half adder and suitable gate
9. What are the different operating regions for an MOS transistor?
10. What is Enhancement mode transistor?

Experiment 4:
1. Write difference and borrow expression of full subtractor
1. How full subtractor can realize by using half subtractor
2. Draw the cmos implementation of full subtractor
3. What are the steps involved in manufacturing of IC?
4. What is meant by Epitaxy?
5. What is BiCMOS Technology?
6. What is Silicide?
7. What is Channel-length modulation?
8. What is Latch – up?
9. What is RTL

Experiment 5:
1. The truth table for an S-R flip-flop has how many VALID entries?
2. When both inputs of a J-K flip-flop cycle, the output will
3. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
4. The logic circuits whose outputs at any instant of time depends only on the present input but also on the
past outputs are called
5. The sequential circuit is also called
6. What is demarcation line?
7. What are LVS and DRL tools?
8. What are the cells available in primitive library?
9. Why is not NAND gate preferred over NOR gate for fabrication?
10. What is the fundamental difference between a MOSFET and BJT ?
Experiment 6:
1. What is a trigger pulse?
2. The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?
3. What is clock skew
4. Distinguish edge and level triggering
5. Why edge triggering is preferred
6. What is race around condition
7. What’s the difference between Testing & Verification?
8. Mention what is the difference between the TTL chips and CMOS chips?
9. Explain why present VLSI circuits use MOSFETs instead of BJTs?
10. What is the fundamental difference between a MOSFET and BJT ?

Experiment 7:
1. Distinguish ram and rom
2. What is flash memory?
3. Give examples of secondary memory
4. What are the advantages of 2d decoding?
5. Explan operation of dynamic cell
6. What is the major difference between SRAM and DRAM?
7. What is a major disadvantage of RAM?
8. What are the differences among EPROM, EEPROM, and flash memory?
9. What are the key properties of semiconductor memory?
10. How does SDRAM differ from ordinary DRAM?

Experiment 8:
1. Define differential amplifier
2. define CMRR
3. Define ‘slew rate’. When does it start showing its effect on amplifier performance.
4. Define an ideal operational amplifier
5. What is tail current?
6. In what different configurations can a differential amplifier be used?
7. What reasons would you assign for very wide use of op amps in analog and digital circuits?
8. How does input off-set voltage in an op amp arise?
9. The difference between the input and output voltage are -1v and 17v. Calculate the closed loop voltage
gain of differential amplifier with one op-amp?
10. Why differential amplifiers are preferred for instrumentation and industrial applications?

Experiment 9:
1. What is a transceiver circuit?
2. What is the function of a buffer circuit?
3. Why NAND & NOR gates are called universal gates?
4. Realize the EX – OR gates using minimum number of NAND gates?
5. List four Basic Flip-flop applications?
6. What advantage does a J-K Flip-flop have over an S-R?
7. What is meant by Race around condition?
8. Design a ring counter using D flip flop
9. Design a Johnson counter using D flip flop
10. Design a ring counter/Johnson counter with mode control using JK flip flop

Experiment 10:
1. Difference between Decoder and Demultiplexer
2. Difference between encoder and multiplexer 3. Implement the function F (A, B, C)∑m
= (0, 1, 3, 4)
using multiplexer.
3. Design an 8:1 multiplexer 5. Design an 1 to 16 Demultiplexer
4. Design a full adder using multiplexer
5. Design an up counter using T flip flop
6. Design an up counter using D flip flop
7. Explain what is multiplexer?
8. Design a counter counts from 1 to 10 (reset to 1, after 10)
9. Implement D-latch using 2*1 MUX
10. Design 3:6 decoders
Dept. of ECE VLSI Lab

CMOS-NAND

D-LATCH

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DIFFERENTIAL AMPLIFIER

FULL ADDER

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FULL-SUBTRACTOR

INVERTER

NOR

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SR-LATCH

SRAM

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INSTRUCTION MANUAL
DESIGN AND SIMULATION
USING
MENTOR GRAPHICS TOOL

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Type the following commands in the sequential order

RightClick , select Open in Terminal

1. csh

2. source .cshrc

3. lmgrd

4. lmstat

5. dmgr_ic

The Pyxis window will be opened as in terminal to Run Pyxis shown below

File -> New -> Project

Type the Project Name and give the Project location

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Browse Technology library generic13 from new_pdk

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Click on Add standard libraries

Click New Library

Give Name

Click on new schematic in tool bar

Give cell name and schematic name.

On Clicking Finish the following window will open

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Click on I+

Select MGC_DESIGN_KIT

Place nmos and pmos

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Add-> Generate symbol

Click OK

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Go for new library under same project

Give cell and schematic names

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Click on I+ add instance

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Place the symbol generated from the old library

Place DC voltage source, Pulse voltage source and connect the circuit as shown.

Check/save

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Click on Setup simulation

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Click on libraries -> edit scenario

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Unselect all except TT-> Click on ADD

Give new lib name -> OK

Select new lib

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Click on Apply

Run simulator

Click on EZwave-> recent WDB

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Close the window

For layout designing (Schematic Driven approach)

Click on the cell where the schematics without voltages are present and click new layout as below

Give names for Layout and cell

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Click OK

Select MOSFETs and click Inst to place Layout of MOSFET

Layout of PMOS

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Pick and place ports

Select M1 metal type

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Place all ports

Add -> Device

Press ‘Q’

Select device name as Gb_p

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Move psub to nmos

And nwell to pmos

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Select Iroute

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Select Add-> Text on ports

Select M1 metal

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Tools-> calibre->Run DRC

Run DRC
Tools-> calibre->Run LVS
Run LVS
Tools-> calibre->Run Pex
Run Pex
Start RVE

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