Asynchronous and Synchronous Transmission
Asynchronous and Synchronous Transmission
Asynchronous and Synchronous Transmission
Techniques
CEN 220/CIS 192 Advanced Data Communications and Networking
Data and Computer Communications, W. Stallings 9/E, Chapter 6
Digital Data Communications Techniques
A conversation forms a two-way communication
link; there is a measure of symmetry between the
two parties, and messages pass to and fro. There is
a continual stimulus-response, cyclic action;
remarks call up other remarks, and the behavior of
the two individuals becomes concerted,
co-operative, and directed toward some goal. This
is true communication.
—On Human Communication,
Colin Cherry
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Asynchronous and Synchronous
Transmission
Timing problems require a mechanism to synchronize the
transmitter and receiver
receiver samples stream at bit intervals
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Asynchronous Transmission
Data are transmitted one character at a time
– each character is 5 to 8 bits in length
– receiver has the opportunity to resynchronize at the
beginning of each new character
Simple and cheap
– requires overhead of 2 or 3 bits per character (~20%)
The larger the block of bits, the greater the cumulative
timing error
Good for data with large gaps (keyboard)
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Asynchronous Transmission
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Synchronous Transmission
Block of bits transmitted in a steady stream without start
and stop codes
Clocks must be synchronized to prevent drift
can use separate clock line
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Types of Error
An error occurs when a bit is altered between
transmission and reception
binary 1 is transmitted and binary 0 is received or
binary 0 is transmitted and binary 1 is received
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Error Detection
Regardless of design you will have errors
Can detect errors by using an error-detecting code added
by the transmitter
• code is also referred to as check bits
Recalculated and checked by receiver
Still chance of undetected error
Parity
parity bit set so character has even (even parity) or odd
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Parity Check
The simplest error detecting scheme is to append
a parity bit to the end of a block of data
If any even number of bits are inverted due to
error, an undetected error occurs
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Error Detection Process
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Cyclic Redundancy Check (CRC)
One of most common and powerful checks
For block of k bits transmitter generates an n bit frame
check sequence (fcs)
Transmits k+n bits which is exactly divisible by some
predetermined number
Receiver divides frame by that number
if no remainder, assume no error
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Error Correction
Correction of detected errors usually requires data
block to be retransmitted
Not appropriate for wireless applications
bit error rate is high causing lots of retransmissions
propagation delay long (satellite) compared with frame
transmission time, resulting in retransmission of frame in
error plus many subsequent frames
Need to correct errors on basis of bits received
codeword
on the transmission end each k-bit block of data is mapped
into an n-bit block (n > k) using a forward error correction
(FEC) encoder
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Error Correction Process
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How Error Correction Works
Adds redundancy to transmitted message
redundancy makes it possible to deduce original
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Line Configuration - Topology
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Line Configuration - Topology
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Line Configuration - Duplex
Data exchanges classified as half or full duplex
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Half duplex (two-way alternate)
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only one station may transmit at a time
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requires one data path
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Full duplex (two-way simultaneous)
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simultaneous transmission and reception between two
stations
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requires two data paths
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separate media or frequencies used for each direction
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Summary
Asynchronous and synchronous transmission
asynchronous
• data transmitted one character at a time
synchronous
• block of bits transmitted in steady stream without start and stop codes
Error detection and correction
single bit error and error burst
error detecting codes
• parity and cyclic redundancy check (CRC)
Line configurations
topology
full duplex and half duplex
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