Smart Lowside Power Switch Hitfet BSP 75N: Data Sheet Rev. 1.4
Smart Lowside Power Switch Hitfet BSP 75N: Data Sheet Rev. 1.4
Smart Lowside Power Switch Hitfet BSP 75N: Data Sheet Rev. 1.4
Features
• Logic Level Input
• Input protection (ESD)
• Thermal shutdown with auto restart
• Overload protection
• Short circuit protection
• Overvoltage protection
• Current limitation
• Green Product (RoHS compliant)
• AEC Stress Test Qualification
Application
• All kinds of resistive, inductive and capacitive loads in switching applications
• µC compatible power switch for 12 V and 24 V DC applications and for 42 Volt
Powernet
• Replaces electromechanical relays and discrete circuits
General Description
N channel vertical power FET in Smart Power Technology. Fully protected by embedded
protection functions.
Product Summary
Parameter Symbol Value Unit
Continuous drain source voltage VDS 60 V
On-state resistance RDS(ON) 550 mΩ
Current limitation ID(lim) 1 A
Nominal load current ID(Nom) 0.7 A
Clamping energy EAS 550 mJ
Vbb
HITFET M
Logic OUTPUT
Stage
Over voltage
Protection
DRAIN
dV/dt
IN limitation
Short circuit
Over Protection
temperature
ESD Protection Current
Limitation
SOURCE
1 IN
SOURCE
TAB
2 DRAIN
3 SOURCE
Circuit Description
The BSP 75N is a monolithic power switch in Smart Power Technology (SPT) with a
logic level input, an open drain DMOS output stage and integrated protection functions.
It is designed for all kind of resistive and inductive loads (relays, solenoid) in automotive
and industrial applications.
Protection Functions
• Over voltage protection: An internal clamp limits the output voltage at VDS(AZ) (min.
60V) when inductive loads are switched off.
• Current limitation: By means of an internal current measurement the drain current is
limited at ID(lim) (1.4 - 1.5 A typ.). If the current limitation is active the device operates
in the linear region, so power dissipation may exceed the capability of the heatsink.
This operation leads to an increasing junction temperature until the over temperature
threshold is reached.
• Over temperature and short circuit protection: This protection is based on sensing
the chip temperature. The location of the sensor ensures a fast and accurate junction
temperature detection. Over temperature shutdown occurs at minimum 150 °C. A
hysteresis of typ. 10 K enables an automatic restart by cooling.
The device is ESD protected according Human Body Model (4 kV) and load dump
protected (see Maximum Ratings).
Thermal Resistance
Electrical Characteristics
Tj = 25 °C, unless otherwise specified
Parameter Sym- Limit Values Unit Test Conditions
bol min. typ. max.
Static Characteristics
Dynamic Characteristics 1)
Protection Functions2)
Inverse Diode
EMC-Characteristics
The following EMC-Characteristics outline the behavior of typical devices. They are not
part of any production test.
Table 1 Test Conditions
Parameter Symbol Value Unit Remark
Temperature TA 23 ±5 °C –
Supply Voltage VS 13.5 V –
Load RL 27 Ω ohmic
Operation mode PWM – – fINx=100Hz, D=0.5
DC – – ON / OFF
DUT specific VIN(’HIGH’)=5V
Conducted Susceptibility
PULSE Acc. 47A/658/CD IEC 62132-4 (Direct
VBB Power Injection)
Direct Power Injection: Forward Power
RL CW
BSP75N
Failure Criteria: Amplitude or frequency
IN DRAIN variation max. 10% at OUT
SOURCE
Typ. Vbb Susceptibility at DC-ON/OFF
and at PWM
40
Figure 3 Test circuit for ISO pulse
35
30
Conducted Emissions
25
20
15
70
60
50
150Ω / 8-H
dBµV
40
30 VBB
20
150Ω / 13-N BAN
10
-10
BSP75N RL
-20
0,1 1 10 100 1000
f / MHz IN DRAIN
SOURCE HF
VBB
IN DRAIN
1)
SOURCE 150Ω-Network For defined de coupling and high reproducibility a
defined choke (5µH at 1MHz) is inserted in the
Vbb-Line.
2)
Broadband Artificial Network (short: BAN) consists
of the same choke (5µH at 1MHz) and the same
Figure 4 Test circuit for conducted 150 Ohm-matching network as for emission
measurement for defined de coupling and high
emission 1) reproducibility.
Block diagram
VBB
ID
uC Vcc BSP75N
IIN HITFET Px.1 IN D
IN DRAIN Vbb GND SOURCE
IN
SOURCE
LOAD
Drain
VAZ
VDS
Power
DMOS Source
ID
Timing diagrams
VIN
VIN
t
ID(lim)
t
ID
VDS
t
t
ϑj
thermal hysteresis
ID 0.9*ID
t
0.1*ID
t Figure 11 Short circuit
ton toff
VIN
VDS(AZ) t
VDS VBB
t
ID
1,6
W 800
m ax.
700
m a x.
1,2 600
500 typ .
0,8 400
300
0,4 200
100
0 0
0 25 50 75 1 00 °C
125 15 0 -5 0 -2 5 0 25 50 7 5 1 0 0 1°C
25 150
T Amb T j
Ω
m 00
12
V2
typ .
10 00
m a x.
1 ,5
8 00
typ .
6 00
1
4 00
0 ,5
2 00
0 0
-50 -2 5 0 25 50 °C 15 0
75 1 00 125 -5 0 -2 5 0 25 50 75 1 0 0 1°C
25 150
T j T j
5 Typ. on-state resistance RON = f(VIN); 6 Typ. current limitation ID(lim) = f(Tj);
ID = 0.7 A; Tj = 25 °C VDS = 12 V, VIN = 10 V
2000 2
R ON
I D (lim )
typ . typ .
5 0Ω0
1m 1A,5
1000 1
500 0 ,5
0 0
0 2 4 6 V
8 10 -5 0 -2 5 0 25 50 75 1 0 0 1°C
25 150
V IN T j
typ .
1A,5
10
K /W
1
D=
0 .5
0 .2
1 0 .1
0 ,5 0 .0 5
0 .0 2
0 .0 1
0
0
0 2 4 6 V
8 10 0 ,1
0 ,0 0 0 0 1 0 ,0 0 1 0 ,1 10 1 0 0s0 100000
V IN tP
4 B
15˚ MAX.
3.5 ±0.2
1 2 3 7 ±0.3
0.5 MIN.
0.7 ±0.1 2.3 0.28 ±0.04
4.6 0...10˚
0.25 M A
0.25 M B
GPS05560
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page: http://www.infineon.com/packages. Dimensions in mm
Revision History
2 Revision History
Edition 2008-07-10
Published by Infineon Technologies AG,
81726 Munich, Germany
© Infineon Technologies AG 2008.
All Rights Reserved.
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