Standard Cell Development for Digital Design Implementation

Version 1.0

June 5, 2007 1
1.0 Introduction
In modern ASIC designs, standard cell methodology are practiced with a sizeable library (or libraries) of cells.
The library usually contains multiple implementations of the same logic function, differing in area and speed.
This variety enhances the efficiency of automated synthesis, place and route (SPR) tools. It also gives designs
greater freedom to perform implementation trade-off (area vs speed vs power consumption). A complete group
of standard cell descriptions is referred as asic library kit in this document. Commerically available EDA tools
use the asic library kit to automate synthesis, placement and routing of digital ASIC. The asic library(along with
the design netlist format) is the basis for exchanging design information between different phases of design flow.

The asic library kit for integrated circuit design’s for DallasSemiconductor/Maxim designers comes from four
different sources. Dallas EDA develops, maintains and releases asic library kits for E35, D6 and 3V cells for T18
process. SunnyVale EDA owns the S4, S45, S8 library kits. High Frequency group owns mbic3, f60 library kits
for design use. Asic libray kits are also downloaded and maintained from external foundries like Taiwan Semi-
conductor and Charter Semiconductor

Often times we hear questions from engineers as to what cells are available in the library for their design use. It
becomes difficult to look at the long list of library cells and identify for the existence of a particular cell in the
library. It becomes much easier for the users of the standard cell libraries if a common standard is maintained
across different libraries. The goal of this document is to provide a standard set of rules that can be applied to all
internally developed asic libraries. This document also includes standard layout guidelines required to build an
efficient asic library for digital design implementation.

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2.0 SPEC
Before the standard cells are developed process integrator defines the characteristics of the standard cell library
required to successfully complete the design targeted to a particular technology node. Initial objective specifica-
tion referred as IOS will include the target PDK data for the development of the standard cells. This document
covers the specifics related to library naming guidelines.

2.1 List of Cells in the Library

The process integrator identifies the cell list for the standard cell library which covers all logic required to start
his design. Based on the spec requirements for the designs each logic cell will require multiple drive strength
with various input combinations. General library requirements defined in the cell list category are listed in Table
1. Comments are listed based on general requirements for each group of library cells.

TABLE 1. Cell List

Cell Comment
Simple Gates Require 2,3,4 input gates
with 1X, 2X, 4X drive
• AND gate strengths.
• NAND
• OR
• NOR
• Exclusive OR
Complex Gates Multiple drive strengths
required with various input
• Input AND into combinations
input OR(AO cells)
• Input AND into
input OR(AOI cells)
• Input OR into input
NAND(OAI cells)
• Half Adder
• Full Adder
• Half Subtractor
• Full Subtractor

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TABLE 1. Cell List

Cell Comment
Inverting Drivers wp=3; wn=1 for 1X drive
strength
• Inverters
wp=9, wn=3 for 3X drive
strength
Internal Stage Drivers
wp=27, wn=9 for 9X drive
• 1X3, 2X3, 3X3 strength
stage buffers
• 1X3, 2X3, 3X3
stage inverters
Multiplexers and Decoders Transmission gate based
• 2:1, 4:1 multiplexer
• A or not B decoder
• A not and B decoder
Sequential Logic Scan equivalent for the
available flops.
• D-type F/F without
set and reset. Out-
put is Q
• D-type F/F with
active low reset.
Output is Q.
• D-type buffered F/F
with active low set.
Output is Q
• D-type latch with-
out set and reset.
Output is Q.
Power Cells TIEHI and TIELO cells
with different drive
• Core cell resistive strengths.
tie-up to core VDD
• Core cell resistive
tie down to core
VSS
Special Cells Filler and Filler Decoupling
Cells
• Filler Cells
Bus holder cells
• Filler Decoupling
cells
• BUS Holder cells

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2.2 Naming Conventions for Standard Cells
Every standard cell library released by the EDA group is used by several Business units across the company and
as the requests to add more cells into the library come from different directions it is very important to maintain
the standard naming guidelines to avoid potential problems during design of the library cell and to avoid redu-
duncy of the work done by the library group.A common naming standard should include the logic function, num-
ber of inputs and drive strength associated with a particular cell. This helps the engineers involved during various
stages of the design flow to identify cells to fix any potential issues during the design stage. Each standard cell
will use common naming standards based on the logic implemented for a particular cell. Standard cells are
grouped into three categories which will have naming guidelines associated with respect to their category. A fur-
ther breakdown of the categories and their associated logic names is listed in table 3.

TABLE 2. Standard Naming Guidelines

Category Naming standards

Combinational <logic><inputs>X<drivestrength>
Sequential <Logic><special inputs><output>X<number>
Power cells <function>X<pitchsize>

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2.2.1 Logic Name

A standard cell is a group of transistor and interconnect structures, which provide a boolean logic function(e.g.
AND, OR.), a storage function(flipflop or latch), or special function power cells (e.g TIEhi, TIELO, FILLER,
DECOUPLE). This boolean logic, storage function or special function is used as a logic name for the cell names.
It is required to have the common boolean logic names for the standard cells across different libraries to make it
easier for the users to identify the available cells in the libraries. Each logic name for a particular function is
listed in table 3. This table should be used as standard naming guidelines to name the standard cells in the library
being developed.
TABLE 3. Cell Codes

Code Description Code Description

AND And Gate SUB Subtractor
NAND Nand Gate DFF Static D Flip-Flop
OR Or Gate DFFN Static -ve edge triggered D Flip Flop
NOR Nor Gate JKFF JK-type Flip Flop
XOR XOR gate TFF Static T Flip Flop
NOR Nor Gate EDFF D-enabled Flip Flop
BUF Buffer SDFF Multiplexed Scan D Flip Flop
CLKBUF Balanced Buffer(Clock Buffer) SEDFF Multiplex Scan D-enable Flip Flop
TBUF Tri State buffer LAT Transparent D latch
INV Inverter TLAT D -latch with output enable
TINV Tri State inverter RSLAT RS-type Latch
CLKINV Clock Inverter (Clock trees) MUX Multiplexer
DLY Delay Cell MUXI Inverting multiplexer
AO AND-OR logic DEC Decoder
AOI AND-OR-Invert Gate TIELO TIE LO cell
OA OR-AND Gate TIEHI TIE HI cell
OAI OR-AND-Invert Gate HOLD Bus Holder
ADDF Full Adder BH Bus Holder
ADDH Half Adder FILLDECAP Decoupling Filler Cell
SUB Subtractor FILL Filler Cell

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2.2.2 Inputs

For a typical boolean logic function, many different cells exist that are functionally equivalent. Each cell will
have boolean logic performed on certain number of inputs. It is essential to append the number of inputs to the
boolean logic name of the cell to keep the user informed about the different options(e.g. choose between single
stage vs multi stage logic) available for the boolean function.
TABLE 4.

Logic
Function Inputs Drive Cell Name
AND 2 1X AND2X1
OR 3 2X OR3X2
NAND 3 4X NAND3X4

e.g AND2X1

Flipflops and Latch cell names should include all the inputs that affect the outcome of the output state of the stor-
age element. Inputs that are propagated to the outputs are embedded into the storage element name(like D-FF,
JK-FF etc.). Inputs that affect the outcome of the output state like set and reset pins should follow the storage
name of the cell. The table 3 below lists the naming guidelines for the storage elements depending on set and
reset inputs.

.
TABLE 5. Storage Elements Name

Edge
Storage Sensitivit
function y Set Reset 1X Drive Cell Name
DFF -ve X X DFFNSRX1
DFF +ve X X DFFSRX1
JKFF +ve X JKFFRX1

2.2.3 Outputs

Standard cell library consists of variety of the sequential elements, both positive edge triggered and negative edge
triggered with multiple outputs available for each sequential element. It is essential to encode this information
into the standard cell name for the users to identify these cells for the design use. Table 5 lists the naming guide-
lines used to encode the outputs into the sequential elements name.
TABLE 6.

Storage Drive
Function Output Strength Cell Name
DFF Q 1X DFFQX1
DFFN QN 1X DFFNQNX1
DFF Q and QN 1X DFFX1

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2.2.4 Drive Strength

Cell libraries determine the overall performance of the integrated circuit design. Designers rely on logic cells
with a wide range of drive strengths to meet and optimize design constraints. It is important to encode the drive
strength information into the standard cell name for the users to identify the logic cells

Drive strength is determined from the ratio of the n-channel and p-channel transistors. Normally we ratio the
sizes of the n-channel and p-channel transistors in an inverter so that both types of transistors have the same
resistance, or drive strength. Mobility of electrons in n-channel is about twice of mobility of holes in p-channel,
for this reason we have to make the shape factor W/L of the p-channel transistor in an inverter about twice that of
the n-channel transistor. Since the transistor lengths are equal for both types of transistors, the ratio of the widths
of the transistors is used to determine the drive strength for the logic cell. We use the minimum sized inverter n-
channel to p-channel ratio as 1X drive strength. More detail information about drive strengths will be explained
in section 5.2

Table 5 lists the logic cells with drive strength encoded into the cell name.
TABLE 7.

Logic
Function Inputs Drive Strengths Cell Name
AND 2 1X AND2X1
AND 2 2X AND2X2
INV 1 1X INVX1

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TABLE 8. Naming Standards
Cat- Logic name Inputs Out- Drive Example Encoded description
egor puts Strength Name
y
Simple Cells
AND 2,3,4 X1, X2 AND2X1 <logic><inputs><drivestrngth>
NAND 2,3,4 X1,X2. NAND2X1
NOR 2,3,4 X1,X2. NOR2X1
OR 2,3,4 X1,X2. OR2X1
XOR 2,3,4 X1, X2 XOR2X1
Complex Cells
AO 1 AND X1,X2 AO21X1 <logic><inputs><drivestrngth>
group, 2
AND
group and
so on.
AOI 2 input X1, X2 AOI21X1
AND, 2
input
NOR
OA 1 OR X1,X2 OA21X1
group, 2
OR group
OAI 1 or more X1,X2 OAI22X1
OR
groups
ADDF X1,X2. ADDFHX1
ADDH X1,X2. ADDHX1
SUB X1, X2,. SUBX1
Inverting Drivers and Delay Cells
INV X1,X2. INVX1 <logic><inputs><drivestrngth>
DLY X1, X2 DLYX1
BUF 3X1 BUF3X1 <logic><inputs><drivestrngth>
INV 3X1 INV3X1
Multiplexers and Decoders
MUX 2,4,8 X1,X2,X4. MUX2X1 <logic><inputs><drivestrngth>
DEC 8,4,2 X1,X2,X4 DEC8X1 <logic><inputs><drivestrngth>

Sequential Cells
DFF Single Q X1,X2,X4. DFFQX1 <logic><inputs><drivestrngth>
output
DFFR Single X1, X2, X4. DFFRX1
Output Q,
active
reset

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TABLE 8. Naming Standards
DFFSR active set X1, X2,X4 DFFSRX1
and reset
DFFY Single X1,X2,X4 DFFYQX1
output Q
EDFF single X1, X2, X4 EDFFQX1
output Q
ESDFF Single X1,X2,X4 ESDFFQX1
output Q
LAT SIngle X1,X2,X4 LATQX1
Output Q
LATN Single X1,X2,X4 LATNQX1
Output Q
LATR Single X1,X2 LATRQX1
Output Q
LATS Single X1, X2... LATSX1
Output Q

Power Cells
TIEHI TIEHI <logic>X<pitchsize>
TIELO TIELO
FILL one pitch, two FILLX1,
pitch,... FILLX2
FILLDECAP one pitch, two FILLDECAP
pitch X1,
FILLDECAP
X2,.

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2.3 Layout Guidelines
This section describes general set of recommendations for library engineers when drawing the layouts for the
standard cells. The guidelines are independent of any CAD tool or silicon process.

2.3.1 Stick Diagram

The table below has the color coded descriptions for the layers used for stick diagrams.

TABLE 9. Color Coded Table for Stick Diagrams

Description Color/Shape
Diffusion Yellow
Aluminum metal Red
Poly Green

With a good transistor level schematic, the next step is to plan the layout. One of the best planning tools is the
“stick diagram”. The stick diagram shows all layers and relative placement except for well ties. It does not show
transistor sizes, wire lengths, wire widths and tub boundaries.
• Assign preferred direction to each layer
• Group n-channel and p-channel transistors
• Determine input/output port location.

A NAND gate stick diagram will be shown here. The example below isn’t the only correct way to draw a stick
diagram.

Two draw stick diagram draw two horizontal lines representing the diffusion for transistors.

PDIFF

NDIFF

Next draw a vertical line for each input. These vertical lines should cross the horizontal P and N diffusion lines.
Intersection of the horizontal and vertical lines represents a transistor. Each vertical line represents the input sig-
nals and are the gate of each transistor.

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 A B

PDIFF

NDIFF

Look at the transistor level schematic and plan out VSS and VDD signals on the stick diagram.

VDD A B VDD

VSS

“When a signal connects to diffusion it adds capacitance. This is good for power and ground, but bad on signal
nets. So plan your stick diagram accordingly to have fewer connections for out signal “Y”.

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This is the stick diagram for a NAND gate.

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2.3.2 Routing Grids

“Minimizing Cell Size does not necessarily minimize die size. Optimize the routing grid than worry about
the cell size”

Layout techniques implemented to draw a standard has a direct impact on the area of the design. Essential guide-
lines have to be determined for the library based on the process profile to improve the design flow for place and
route tools. The following guidelines are identified and explained as necessary in the following sections.

Before the standard cell is drawn both horizontal and vertical routing grid has to be determined for the horizontal
and vertical metal layers. The router uses these routing grids to connect to the pins inside the standard cell. Rout-
ing grid spacing is usually determined as line-on-line, line-on-via or via-on-via spacing. Standard cell layouts
which use via-on-via spacing rules for routing grid achieve higher row utilization numbers for the design which
means that although the layout of the cell might be larger with via-on-via the overall design size after the routing
stage of the design is smaller than the design which uses cells with line-on-line spacing rules.The following
equations show how the routing grid is calculated for all three cases.

Line – on – Line = HalfMetalWidth + MetalSpacing + HalfMetalWidth

Line – on – Via = HalfMetalWidth + MetalSpacing + HalfVia ( includingOverhang )
Via – on – Via = HalfVia ( includingOverlap ) + MetalSpacing + HalfVia ( includingOverlap ) )

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Line-On-Line Line-On-Via Via-On-Via

Routing Grid Spacing

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The routing grid determined from above rules will be used by the router to route to the pins inside the standard
cell. The routing grid is always defined with respect to the cell origin. Typical routing grid structure used by the
router to connect to the pins is shown below

Horizontal Grid Without Offset Vertical Grid without Offset

Origin Origin

Grids can be offset from the origin, however by exactly half the grid spacing. This adds one more channel to the
pins for routing. A typical routing grid with offset and without offset is shown below

Origin Origin

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When calculating the grid for metal layers it is essential to keep the ratio of the pitch values between same direc-
tion layers as close as possible. If the metal3 ratio is same as metal1 the routing tracks for metal3 are same as
metal1. This is good for technologies which allow stacked via. This will help the router do an efficient job since
it will have more options. The figures below show the cases where metal3 pitch ratio with metal1 is 2:1 and 3:1.
As the ratios get bigger and bigger the routing tracks for the layers decrease and impact the die size achieved by
the router. Hence it is very important to look at the pitch values for all the metal layers before deriving the pitch
value for metal1 and drawing the layout.

M1

M1, M3

This case is better for Routing

M1

M1, M3

M1

Avoid Large ratios for pitch

M1

M1, M3

M1

June 5, 2007 17
2.3.3 Pin Placement

Pin placement techniques discussed here will maximize the pin accessibility for the router. It is recommend to
follow these guidelines when drawing the pins in the standard cell layout.
• All the pins for the standard cells should be placed at the intersection of the horizontal and vertical grid inter-
section as shown in the example here

GOOD

BAD

BAD
June 5, 2007 18
• Stagger pins in X and Y direction. This maximizes the pin accessibility for the router. The routing density for
the first case shown below is 3 and the routing density for the second case shown below is 1. This shows that
staggering of pins helps the router to achieve better results.

Avoid this case

GOOD

• Declare complete geometry of the pin as pin.

• Avoid geometries on same layer close to the pin specifically for clock pins on a flop. This helps the router
minimize the wire length required to route to the pin.

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With the staggering of pins the router has more options to route to the pins inside the cell. It can use both hori-
zontal and vertical routing tracks efficiently to route the pins. If the pins are not staggered it makes the designs
with high row utilizations unroutable.

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2.3.4 Fault Analysis

This concentrates on the standard cell design styles that are easily testable for defects that cause shorts. A
NAND gate cell level design guideline is demonstrated here and can be applied to the standard cells wherever it
is applicable

Consider the short across its inputs in the figure shown below. Circuit simulations will show for most driving
cells the shorts exhibit wired AND behavior make the short undetectable by observing the logic values at the
output of the gate.

A X
Y
B
X

If the inputs and outputs of the NAND gate were designed as shown in the first case below, there is a possibility
of a defect causing the difficult-to-detect short to occur. However, if the NAND gate was designed as shown in
second case, the short cannot occur since a defect large enough to short inputs A and B together would also
short Y. However a short between either input and q is possible. This usually results in the input value dominat-
ing the output value. In effect any test that defects an input stuck-at 0 or 1 will detect short between that input
and the output Y.

A B Y A Y B

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2.3.5 Wire Usage

The table below shows the parasitics associated with the layers used to build transistors.
TABLE 10.

Resistanc Capacita
Layer e nce Connects to
M1 low low ndiff,pdiff, poly,M2
Poly medium low gate,M1
ndiff medium high S/D, M1
pdiff medium high S/D, M1

• Diffusion Layer
Has high capacitance and should only be used to connect to the transistors
• Poly Layer
Resistance is high for this layer. Use only as a gate forming layer. Do not use this layer as jumpers between
layers and for signal net routing.
• Metal Layer
Metal layer is the only conductor that can connect to poly and diffusion. Use metal layer for signal nets, power
and ground routing within the standard cell

2.3.6 Design Rules

The following set of design guidelines should be followed when drawing a standard cell layout.

• P-N spacing is large so keep pmos together and nmos together. Share diffusion wherever possible for the
devices. Draw the pMos groups close to the power rail and nMos groups close to the ground rail.

2.3.7 Determine the cell pitch

The width of the standard cell should be an integer multiple of the vertical routing grid. This ensures that the
cells placed on this placement grid will have all the pins aligned on the vertical routing grid as shown in figure
below.
The height of the cell should be an integer multiple of the horizontal routing grid. This ensures that the cells
placed on this placement grid will have all the pins of the standard cell aligned properly with the horizontal
routing grid as shown in fig below.
Typically all the standard cells in a particular library should have a fixed height. The height of the standard cell
library is determined from the spacing rules required by pMos and nMos groups and also from the power
requirements(width of power and ground lines) for a particular process.
With the cell width being the multiple of the vertical routing grid and the cell height being the multiple of hor-
izontal grid you can achieve better placement and routing results from auto placers and routers.

June 5, 2007 22
 Cell Placed on Grid

Pins on Grid

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2.3.8 Transistor Layout

Use as many contacts as possible for wider transistors

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2.3.9 Transistor Folding

• Achieves better aspect ratio for large devices.

• Reduces diffusion are when you fold devices.

The figures below show the reduction in diffusion area from transistor folding.

32/2

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16/2 16/2

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8/2 8/2 8/2 8/2

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2.3.10 Power and Ground

Resistance of power and ground supply lines must be very small. Use wide metals for power and ground pins.All
power and ground pins must have the same offset from the cell origin, otherwise when the placer abuts the cells
on the placement grid it creates DRC violations. The figure below shows the placement of the standard cells on
grid.

Cell Placed on Grid

FollowPins

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 Cell Placed on Grid

FollowPins

CELL A

CELL B

When cells boundaries are abutted the power/ground pins are not abutted and not connected.

June 5, 2007 29
2.4 Library Development Flow
Dallas EDA groups develop maintain and release libraries for internal processes like D6, E35 and support librar-
ies from external foundry processes such as Taiwan semiconductor and Charter semiconductor. A graphical rep-
resentation of the Dallas Semiconductor library flow is shown here.

Generate Schematic

Functional/Timing Checks

Draw Layout

DRC

LVS

Extract Layout

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Characterize Timing Models Technology

Generate functional Models Abstracts

Characterize Noise Models InterConnect Rules

Characterize Power Models Extraction Models

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3.0 Conclusion
The general consensus from the designers is to have a common standard for the library development between dif-
ferent EDA groups and the one that matches closely with the libraries released from the external foundries. This
document addresses the issue to have a common naming standards and development strategies for developing
brand new libraries. This document should be used as a general guideline for developing a standard cell library
for a particular technology. Naming standards for standard cells discussed in earlier sections should be adhered to
strictly when developing cells for a new library. The layout guidelines discussed in earlier sections are good strat-
egies for drawing efficient layouts and covers efficiency requirements for place and route flow as well.

June 5, 2007 32